1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; This test makes sure that div instructions are properly eliminated. 3 4; RUN: opt < %s -instcombine -S | FileCheck %s 5 6define i32 @test1(i32 %A) { 7; CHECK-LABEL: @test1( 8; CHECK-NEXT: ret i32 %A 9; 10 %B = sdiv i32 %A, 1 ; <i32> [#uses=1] 11 ret i32 %B 12} 13 14define i32 @test2(i32 %A) { 15 ; => Shift 16; CHECK-LABEL: @test2( 17; CHECK-NEXT: [[B:%.*]] = lshr i32 %A, 3 18; CHECK-NEXT: ret i32 [[B]] 19; 20 %B = udiv i32 %A, 8 ; <i32> [#uses=1] 21 ret i32 %B 22} 23 24define i32 @test3(i32 %A) { 25 ; => 0, don't need to keep traps 26; CHECK-LABEL: @test3( 27; CHECK-NEXT: ret i32 0 28; 29 %B = sdiv i32 0, %A ; <i32> [#uses=1] 30 ret i32 %B 31} 32 33define i32 @test4(i32 %A) { 34 ; 0-A 35; CHECK-LABEL: @test4( 36; CHECK-NEXT: [[B:%.*]] = sub i32 0, %A 37; CHECK-NEXT: ret i32 [[B]] 38; 39 %B = sdiv i32 %A, -1 ; <i32> [#uses=1] 40 ret i32 %B 41} 42 43define i32 @test5(i32 %A) { 44; CHECK-LABEL: @test5( 45; CHECK-NEXT: ret i32 0 46; 47 %B = udiv i32 %A, -16 ; <i32> [#uses=1] 48 %C = udiv i32 %B, -4 ; <i32> [#uses=1] 49 ret i32 %C 50} 51 52define i1 @test6(i32 %A) { 53; CHECK-LABEL: @test6( 54; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %A, 123 55; CHECK-NEXT: ret i1 [[TMP1]] 56; 57 %B = udiv i32 %A, 123 ; <i32> [#uses=1] 58 ; A < 123 59 %C = icmp eq i32 %B, 0 ; <i1> [#uses=1] 60 ret i1 %C 61} 62 63define i1 @test7(i32 %A) { 64; CHECK-LABEL: @test7( 65; CHECK-NEXT: [[A_OFF:%.*]] = add i32 %A, -20 66; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[A_OFF]], 10 67; CHECK-NEXT: ret i1 [[TMP1]] 68; 69 %B = udiv i32 %A, 10 ; <i32> [#uses=1] 70 ; A >= 20 && A < 30 71 %C = icmp eq i32 %B, 2 ; <i1> [#uses=1] 72 ret i1 %C 73} 74 75define <2 x i1> @test7vec(<2 x i32> %A) { 76; CHECK-LABEL: @test7vec( 77; CHECK-NEXT: [[A_OFF:%.*]] = add <2 x i32> %A, <i32 -20, i32 -20> 78; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <2 x i32> [[A_OFF]], <i32 10, i32 10> 79; CHECK-NEXT: ret <2 x i1> [[TMP1]] 80; 81 %B = udiv <2 x i32> %A, <i32 10, i32 10> 82 %C = icmp eq <2 x i32> %B, <i32 2, i32 2> 83 ret <2 x i1> %C 84} 85 86define i1 @test8(i8 %A) { 87; CHECK-LABEL: @test8( 88; CHECK-NEXT: [[C:%.*]] = icmp ugt i8 %A, -11 89; CHECK-NEXT: ret i1 [[C]] 90; 91 %B = udiv i8 %A, 123 ; <i8> [#uses=1] 92 ; A >= 246 93 %C = icmp eq i8 %B, 2 ; <i1> [#uses=1] 94 ret i1 %C 95} 96 97define <2 x i1> @test8vec(<2 x i8> %A) { 98; CHECK-LABEL: @test8vec( 99; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i8> %A, <i8 -11, i8 -11> 100; CHECK-NEXT: ret <2 x i1> [[C]] 101; 102 %B = udiv <2 x i8> %A, <i8 123, i8 123> 103 %C = icmp eq <2 x i8> %B, <i8 2, i8 2> 104 ret <2 x i1> %C 105} 106 107define i1 @test9(i8 %A) { 108; CHECK-LABEL: @test9( 109; CHECK-NEXT: [[C:%.*]] = icmp ult i8 %A, -10 110; CHECK-NEXT: ret i1 [[C]] 111; 112 %B = udiv i8 %A, 123 ; <i8> [#uses=1] 113 ; A < 246 114 %C = icmp ne i8 %B, 2 ; <i1> [#uses=1] 115 ret i1 %C 116} 117 118define <2 x i1> @test9vec(<2 x i8> %A) { 119; CHECK-LABEL: @test9vec( 120; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i8> %A, <i8 -10, i8 -10> 121; CHECK-NEXT: ret <2 x i1> [[C]] 122; 123 %B = udiv <2 x i8> %A, <i8 123, i8 123> 124 %C = icmp ne <2 x i8> %B, <i8 2, i8 2> 125 ret <2 x i1> %C 126} 127 128define i32 @test10(i32 %X, i1 %C) { 129; CHECK-LABEL: @test10( 130; CHECK-NEXT: [[R_V:%.*]] = select i1 %C, i32 6, i32 3 131; CHECK-NEXT: [[R:%.*]] = lshr i32 %X, [[R:%.*]].v 132; CHECK-NEXT: ret i32 [[R]] 133; 134 %V = select i1 %C, i32 64, i32 8 ; <i32> [#uses=1] 135 %R = udiv i32 %X, %V ; <i32> [#uses=1] 136 ret i32 %R 137} 138 139define i32 @test11(i32 %X, i1 %C) { 140; CHECK-LABEL: @test11( 141; CHECK-NEXT: [[B_V:%.*]] = select i1 %C, i32 10, i32 5 142; CHECK-NEXT: [[B:%.*]] = lshr i32 %X, [[B:%.*]].v 143; CHECK-NEXT: ret i32 [[B]] 144; 145 %A = select i1 %C, i32 1024, i32 32 ; <i32> [#uses=1] 146 %B = udiv i32 %X, %A ; <i32> [#uses=1] 147 ret i32 %B 148} 149 150; PR2328 151define i32 @test12(i32 %x) nounwind { 152; CHECK-LABEL: @test12( 153; CHECK-NEXT: ret i32 1 154; 155 %tmp3 = udiv i32 %x, %x ; 1 156 ret i32 %tmp3 157} 158 159define i32 @test13(i32 %x) nounwind { 160; CHECK-LABEL: @test13( 161; CHECK-NEXT: ret i32 1 162; 163 %tmp3 = sdiv i32 %x, %x ; 1 164 ret i32 %tmp3 165} 166 167define i32 @test14(i8 %x) nounwind { 168; CHECK-LABEL: @test14( 169; CHECK-NEXT: ret i32 0 170; 171 %zext = zext i8 %x to i32 172 %div = udiv i32 %zext, 257 ; 0 173 ret i32 %div 174} 175 176; PR9814 177define i32 @test15(i32 %a, i32 %b) nounwind { 178; CHECK-LABEL: @test15( 179; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, -2 180; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]] 181; CHECK-NEXT: ret i32 [[DIV2]] 182; 183 %shl = shl i32 1, %b 184 %div = lshr i32 %shl, 2 185 %div2 = udiv i32 %a, %div 186 ret i32 %div2 187} 188 189define <2 x i64> @test16(<2 x i64> %x) nounwind { 190; CHECK-LABEL: @test16( 191; CHECK-NEXT: [[DIV:%.*]] = udiv <2 x i64> %x, <i64 192, i64 192> 192; CHECK-NEXT: ret <2 x i64> [[DIV]] 193; 194 %shr = lshr <2 x i64> %x, <i64 5, i64 5> 195 %div = udiv <2 x i64> %shr, <i64 6, i64 6> 196 ret <2 x i64> %div 197} 198 199define <2 x i64> @test17(<2 x i64> %x) nounwind { 200; CHECK-LABEL: @test17( 201; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i64> %x, <i64 -3, i64 -4> 202; CHECK-NEXT: ret <2 x i64> [[DIV]] 203; 204 %neg = sub nsw <2 x i64> zeroinitializer, %x 205 %div = sdiv <2 x i64> %neg, <i64 3, i64 4> 206 ret <2 x i64> %div 207} 208 209define <2 x i64> @test18(<2 x i64> %x) nounwind { 210; CHECK-LABEL: @test18( 211; CHECK-NEXT: [[DIV:%.*]] = sub <2 x i64> zeroinitializer, %x 212; CHECK-NEXT: ret <2 x i64> [[DIV]] 213; 214 %div = sdiv <2 x i64> %x, <i64 -1, i64 -1> 215 ret <2 x i64> %div 216} 217 218define i32 @test19(i32 %x) { 219; CHECK-LABEL: @test19( 220; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %x, 1 221; CHECK-NEXT: [[A:%.*]] = zext i1 [[TMP1]] to i32 222; CHECK-NEXT: ret i32 [[A]] 223; 224 %A = udiv i32 1, %x 225 ret i32 %A 226} 227 228define i32 @test20(i32 %x) { 229; CHECK-LABEL: @test20( 230; CHECK-NEXT: [[TMP1:%.*]] = add i32 %x, 1 231; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3 232; CHECK-NEXT: [[A:%.*]] = select i1 [[TMP2]], i32 %x, i32 0 233; CHECK-NEXT: ret i32 [[A]] 234; 235 %A = sdiv i32 1, %x 236 ret i32 %A 237} 238 239define i32 @test21(i32 %a) { 240; CHECK-LABEL: @test21( 241; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 3 242; CHECK-NEXT: ret i32 [[DIV]] 243; 244 %shl = shl nsw i32 %a, 2 245 %div = sdiv i32 %shl, 12 246 ret i32 %div 247} 248 249define i32 @test22(i32 %a) { 250; CHECK-LABEL: @test22( 251; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 4 252; CHECK-NEXT: ret i32 [[DIV]] 253; 254 %mul = mul nsw i32 %a, 3 255 %div = sdiv i32 %mul, 12 256 ret i32 %div 257} 258 259define i32 @test23(i32 %a) { 260; CHECK-LABEL: @test23( 261; CHECK-NEXT: [[DIV:%.*]] = udiv i32 %a, 3 262; CHECK-NEXT: ret i32 [[DIV]] 263; 264 %shl = shl nuw i32 %a, 2 265 %div = udiv i32 %shl, 12 266 ret i32 %div 267} 268 269define i32 @test24(i32 %a) { 270; CHECK-LABEL: @test24( 271; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, 2 272; CHECK-NEXT: ret i32 [[DIV]] 273; 274 %mul = mul nuw i32 %a, 3 275 %div = udiv i32 %mul, 12 276 ret i32 %div 277} 278 279define i32 @test25(i32 %a) { 280; CHECK-LABEL: @test25( 281; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 1 282; CHECK-NEXT: ret i32 [[DIV]] 283; 284 %shl = shl nsw i32 %a, 2 285 %div = sdiv i32 %shl, 2 286 ret i32 %div 287} 288 289define i32 @test26(i32 %a) { 290; CHECK-LABEL: @test26( 291; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 2 292; CHECK-NEXT: ret i32 [[DIV]] 293; 294 %mul = mul nsw i32 %a, 12 295 %div = sdiv i32 %mul, 3 296 ret i32 %div 297} 298 299define i32 @test27(i32 %a) { 300; CHECK-LABEL: @test27( 301; CHECK-NEXT: [[DIV:%.*]] = shl nuw i32 %a, 1 302; CHECK-NEXT: ret i32 [[DIV]] 303; 304 %shl = shl nuw i32 %a, 2 305 %div = udiv i32 %shl, 2 306 ret i32 %div 307} 308 309define i32 @test28(i32 %a) { 310; CHECK-LABEL: @test28( 311; CHECK-NEXT: [[DIV:%.*]] = mul nuw i32 %a, 12 312; CHECK-NEXT: ret i32 [[DIV]] 313; 314 %mul = mul nuw i32 %a, 36 315 %div = udiv i32 %mul, 3 316 ret i32 %div 317} 318 319define i32 @test29(i32 %a) { 320; CHECK-LABEL: @test29( 321; CHECK-NEXT: [[MUL_LOBIT:%.*]] = and i32 %a, 1 322; CHECK-NEXT: ret i32 [[MUL_LOBIT]] 323; 324 %mul = shl nsw i32 %a, 31 325 %div = sdiv i32 %mul, -2147483648 326 ret i32 %div 327} 328 329define i32 @test30(i32 %a) { 330; CHECK-LABEL: @test30( 331; CHECK-NEXT: ret i32 %a 332; 333 %mul = shl nuw i32 %a, 31 334 %div = udiv i32 %mul, -2147483648 335 ret i32 %div 336} 337 338define <2 x i32> @test31(<2 x i32> %x) { 339; CHECK-LABEL: @test31( 340; CHECK-NEXT: ret <2 x i32> zeroinitializer 341; 342 %shr = lshr <2 x i32> %x, <i32 31, i32 31> 343 %div = udiv <2 x i32> %shr, <i32 2147483647, i32 2147483647> 344 ret <2 x i32> %div 345} 346 347define i32 @test32(i32 %a, i32 %b) { 348; CHECK-LABEL: @test32( 349; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, %b 350; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[SHL]], 2 351; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]] 352; CHECK-NEXT: ret i32 [[DIV2]] 353; 354 %shl = shl i32 2, %b 355 %div = lshr i32 %shl, 2 356 %div2 = udiv i32 %a, %div 357 ret i32 %div2 358} 359 360define <2 x i64> @test33(<2 x i64> %x) nounwind { 361; CHECK-LABEL: @test33( 362; CHECK-NEXT: [[DIV:%.*]] = udiv exact <2 x i64> %x, <i64 192, i64 192> 363; CHECK-NEXT: ret <2 x i64> [[DIV]] 364; 365 %shr = lshr exact <2 x i64> %x, <i64 5, i64 5> 366 %div = udiv exact <2 x i64> %shr, <i64 6, i64 6> 367 ret <2 x i64> %div 368} 369 370define <2 x i64> @test34(<2 x i64> %x) nounwind { 371; CHECK-LABEL: @test34( 372; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i64> %x, <i64 -3, i64 -4> 373; CHECK-NEXT: ret <2 x i64> [[DIV]] 374; 375 %neg = sub nsw <2 x i64> zeroinitializer, %x 376 %div = sdiv exact <2 x i64> %neg, <i64 3, i64 4> 377 ret <2 x i64> %div 378} 379 380define i32 @test35(i32 %A) { 381; CHECK-LABEL: @test35( 382; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647 383; CHECK-NEXT: [[MUL:%.*]] = udiv exact i32 [[AND]], 2147483647 384; CHECK-NEXT: ret i32 [[MUL]] 385; 386 %and = and i32 %A, 2147483647 387 %mul = sdiv exact i32 %and, 2147483647 388 ret i32 %mul 389} 390 391define i32 @test36(i32 %A) { 392; CHECK-LABEL: @test36( 393; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647 394; CHECK-NEXT: [[MUL:%.*]] = lshr exact i32 [[AND]], %A 395; CHECK-NEXT: ret i32 [[MUL]] 396; 397 %and = and i32 %A, 2147483647 398 %shl = shl nsw i32 1, %A 399 %mul = sdiv exact i32 %and, %shl 400 ret i32 %mul 401} 402 403; FIXME: Vector should get same transform as scalar. 404 405define <2 x i32> @test36vec(<2 x i32> %A) { 406; CHECK-LABEL: @test36vec( 407; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %A, <i32 2147483647, i32 2147483647> 408; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw <2 x i32> <i32 1, i32 1>, %A 409; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], [[SHL]] 410; CHECK-NEXT: ret <2 x i32> [[MUL]] 411; 412 %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647> 413 %shl = shl nsw <2 x i32> <i32 1, i32 1>, %A 414 %mul = sdiv exact <2 x i32> %and, %shl 415 ret <2 x i32> %mul 416} 417 418define i32 @test37(i32* %b) { 419; CHECK-LABEL: @test37( 420; CHECK-NEXT: entry: 421; CHECK-NEXT: store i32 0, i32* %b, align 4 422; CHECK-NEXT: br i1 undef, label %lor.rhs, label %lor.end 423; CHECK: lor.rhs: 424; CHECK-NEXT: br label %lor.end 425; CHECK: lor.end: 426; CHECK-NEXT: ret i32 0 427; 428entry: 429 store i32 0, i32* %b, align 4 430 %0 = load i32, i32* %b, align 4 431 br i1 undef, label %lor.rhs, label %lor.end 432 433lor.rhs: ; preds = %entry 434 %mul = mul nsw i32 undef, %0 435 br label %lor.end 436 437lor.end: ; preds = %lor.rhs, %entry 438 %t.0 = phi i32 [ %0, %entry ], [ %mul, %lor.rhs ] 439 %div = sdiv i32 %t.0, 2 440 ret i32 %div 441} 442 443; We can perform the division in the smaller type. 444 445define i32 @shrink(i8 %x) { 446; CHECK-LABEL: @shrink( 447; CHECK-NEXT: [[TMP1:%.*]] = sdiv i8 %x, 127 448; CHECK-NEXT: [[DIV:%.*]] = sext i8 [[TMP1]] to i32 449; CHECK-NEXT: ret i32 [[DIV]] 450; 451 %conv = sext i8 %x to i32 452 %div = sdiv i32 %conv, 127 453 ret i32 %div 454} 455 456; Division in the smaller type can lead to more optimizations. 457 458define i32 @zap(i8 %x) { 459; CHECK-LABEL: @zap( 460; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 %x, -128 461; CHECK-NEXT: [[DIV:%.*]] = zext i1 [[TMP1]] to i32 462; CHECK-NEXT: ret i32 [[DIV]] 463; 464 %conv = sext i8 %x to i32 465 %div = sdiv i32 %conv, -128 466 ret i32 %div 467} 468 469; Splat constant divisors should get the same folds. 470 471define <3 x i32> @shrink_vec(<3 x i8> %x) { 472; CHECK-LABEL: @shrink_vec( 473; CHECK-NEXT: [[TMP1:%.*]] = sdiv <3 x i8> %x, <i8 127, i8 127, i8 127> 474; CHECK-NEXT: [[DIV:%.*]] = sext <3 x i8> [[TMP1]] to <3 x i32> 475; CHECK-NEXT: ret <3 x i32> [[DIV]] 476; 477 %conv = sext <3 x i8> %x to <3 x i32> 478 %div = sdiv <3 x i32> %conv, <i32 127, i32 127, i32 127> 479 ret <3 x i32> %div 480} 481 482define <2 x i32> @zap_vec(<2 x i8> %x) { 483; CHECK-LABEL: @zap_vec( 484; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, <i8 -128, i8 -128> 485; CHECK-NEXT: [[DIV:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32> 486; CHECK-NEXT: ret <2 x i32> [[DIV]] 487; 488 %conv = sext <2 x i8> %x to <2 x i32> 489 %div = sdiv <2 x i32> %conv, <i32 -128, i32 -128> 490 ret <2 x i32> %div 491} 492 493; But we can't do this if the signed constant won't fit in the original type. 494 495define i32 @shrink_no(i8 %x) { 496; CHECK-LABEL: @shrink_no( 497; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32 498; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 128 499; CHECK-NEXT: ret i32 [[DIV]] 500; 501 %conv = sext i8 %x to i32 502 %div = sdiv i32 %conv, 128 503 ret i32 %div 504} 505 506define i32 @shrink_no2(i8 %x) { 507; CHECK-LABEL: @shrink_no2( 508; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32 509; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], -129 510; CHECK-NEXT: ret i32 [[DIV]] 511; 512 %conv = sext i8 %x to i32 513 %div = sdiv i32 %conv, -129 514 ret i32 %div 515} 516 517; 17 bits are needed to represent 65535 as a signed value, so this shouldn't fold. 518 519define i32 @shrink_no3(i16 %x) { 520; CHECK-LABEL: @shrink_no3( 521; CHECK-NEXT: [[CONV:%.*]] = sext i16 %x to i32 522; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 65535 523; CHECK-NEXT: ret i32 [[DIV]] 524; 525 %conv = sext i16 %x to i32 526 %div = sdiv i32 %conv, 65535 527 ret i32 %div 528} 529 530