1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes 2; RUN: opt -attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=9 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM 3; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=14 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM 4; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM 5; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-disable=false -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM 6 7; FIXME: CGSCC is not looking at callees and calleers even though it could be allowed. 8 9define i32 @test0(i32* %p) { 10; CHECK-LABEL: define {{[^@]+}}@test0 11; CHECK-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 12; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[P]], align 4, !range !0 13; CHECK-NEXT: ret i32 [[A]] 14; 15 %a = load i32, i32* %p, !range !0 16 ret i32 %a 17} 18 19define i32 @test0-range-check(i32* %p) { 20; IS__TUNIT____-LABEL: define {{[^@]+}}@test0-range-check 21; IS__TUNIT____-SAME: (i32* nocapture nofree readonly align 4 [[P:%.*]]) 22; IS__TUNIT____-NEXT: [[A:%.*]] = tail call i32 @test0(i32* nocapture nofree readonly align 4 [[P]]) #4, !range !0 23; IS__TUNIT____-NEXT: ret i32 [[A]] 24; 25; IS__CGSCC____-LABEL: define {{[^@]+}}@test0-range-check 26; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 27; IS__CGSCC____-NEXT: [[A:%.*]] = tail call i32 @test0(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 28; IS__CGSCC____-NEXT: ret i32 [[A]] 29; 30 %a = tail call i32 @test0(i32* %p) 31 ret i32 %a 32} 33 34declare void @use3-dummy(i1, i1, i1) 35define void @use3(i1, i1, i1) { 36; CHECK-LABEL: define {{[^@]+}}@use3 37; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]], i1 [[TMP2:%.*]]) 38; CHECK-NEXT: tail call void @use3-dummy(i1 [[TMP0]], i1 [[TMP1]], i1 [[TMP2]]) 39; CHECK-NEXT: ret void 40; 41 tail call void @use3-dummy(i1 %0, i1 %1, i1 %2) 42 ret void 43} 44 45; TEST0 icmp test 46define void @test0-icmp-check(i32* %p){ 47 ; ret = [0, 10) 48; IS__TUNIT____-LABEL: define {{[^@]+}}@test0-icmp-check 49; IS__TUNIT____-SAME: (i32* nocapture nofree readonly align 4 [[P:%.*]]) 50; IS__TUNIT____-NEXT: [[RET:%.*]] = tail call i32 @test0(i32* nocapture nofree readonly align 4 [[P]]) #4, !range !0 51; IS__TUNIT____-NEXT: [[CMP_EQ_2:%.*]] = icmp eq i32 [[RET]], 9 52; IS__TUNIT____-NEXT: [[CMP_EQ_3:%.*]] = icmp eq i32 [[RET]], 8 53; IS__TUNIT____-NEXT: [[CMP_EQ_4:%.*]] = icmp eq i32 [[RET]], 1 54; IS__TUNIT____-NEXT: [[CMP_EQ_5:%.*]] = icmp eq i32 [[RET]], 0 55; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 [[CMP_EQ_2]], i1 [[CMP_EQ_3]]) 56; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_EQ_4]], i1 [[CMP_EQ_5]], i1 false) 57; IS__TUNIT____-NEXT: [[CMP_NE_2:%.*]] = icmp ne i32 [[RET]], 9 58; IS__TUNIT____-NEXT: [[CMP_NE_3:%.*]] = icmp ne i32 [[RET]], 8 59; IS__TUNIT____-NEXT: [[CMP_NE_4:%.*]] = icmp ne i32 [[RET]], 1 60; IS__TUNIT____-NEXT: [[CMP_NE_5:%.*]] = icmp ne i32 [[RET]], 0 61; IS__TUNIT____-NEXT: tail call void @use3(i1 true, i1 [[CMP_NE_2]], i1 [[CMP_NE_3]]) 62; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_NE_4]], i1 [[CMP_NE_5]], i1 true) 63; IS__TUNIT____-NEXT: [[CMP_UGT_3:%.*]] = icmp ugt i32 [[RET]], 8 64; IS__TUNIT____-NEXT: [[CMP_UGT_4:%.*]] = icmp ugt i32 [[RET]], 1 65; IS__TUNIT____-NEXT: [[CMP_UGT_5:%.*]] = icmp ugt i32 [[RET]], 0 66; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 false, i1 [[CMP_UGT_3]]) 67; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_UGT_4]], i1 [[CMP_UGT_5]], i1 false) 68; IS__TUNIT____-NEXT: [[CMP_UGE_2:%.*]] = icmp uge i32 [[RET]], 9 69; IS__TUNIT____-NEXT: [[CMP_UGE_3:%.*]] = icmp uge i32 [[RET]], 8 70; IS__TUNIT____-NEXT: [[CMP_UGE_4:%.*]] = icmp uge i32 [[RET]], 1 71; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 [[CMP_UGE_2]], i1 [[CMP_UGE_3]]) 72; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_UGE_4]], i1 true, i1 false) 73; IS__TUNIT____-NEXT: [[CMP_SGT_3:%.*]] = icmp sgt i32 [[RET]], 8 74; IS__TUNIT____-NEXT: [[CMP_SGT_4:%.*]] = icmp sgt i32 [[RET]], 1 75; IS__TUNIT____-NEXT: [[CMP_SGT_5:%.*]] = icmp sgt i32 [[RET]], 0 76; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 false, i1 [[CMP_SGT_3]]) 77; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_SGT_4]], i1 [[CMP_SGT_5]], i1 true) 78; IS__TUNIT____-NEXT: [[CMP_GTE_2:%.*]] = icmp sge i32 [[RET]], 9 79; IS__TUNIT____-NEXT: [[CMP_GTE_3:%.*]] = icmp sge i32 [[RET]], 8 80; IS__TUNIT____-NEXT: [[CMP_GTE_4:%.*]] = icmp sge i32 [[RET]], 1 81; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 [[CMP_GTE_2]], i1 [[CMP_GTE_3]]) 82; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_GTE_4]], i1 true, i1 true) 83; IS__TUNIT____-NEXT: [[CMP_SLT_2:%.*]] = icmp slt i32 [[RET]], 9 84; IS__TUNIT____-NEXT: [[CMP_SLT_3:%.*]] = icmp slt i32 [[RET]], 8 85; IS__TUNIT____-NEXT: [[CMP_SLT_4:%.*]] = icmp slt i32 [[RET]], 1 86; IS__TUNIT____-NEXT: tail call void @use3(i1 true, i1 [[CMP_SLT_2]], i1 [[CMP_SLT_3]]) 87; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_SLT_4]], i1 false, i1 false) 88; IS__TUNIT____-NEXT: [[CMP_LTE_3:%.*]] = icmp sle i32 [[RET]], 8 89; IS__TUNIT____-NEXT: [[CMP_LTE_4:%.*]] = icmp sle i32 [[RET]], 1 90; IS__TUNIT____-NEXT: [[CMP_LTE_5:%.*]] = icmp sle i32 [[RET]], 0 91; IS__TUNIT____-NEXT: tail call void @use3(i1 true, i1 true, i1 [[CMP_LTE_3]]) 92; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_LTE_4]], i1 [[CMP_LTE_5]], i1 false) 93; IS__TUNIT____-NEXT: ret void 94; 95; IS__CGSCC____-LABEL: define {{[^@]+}}@test0-icmp-check 96; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 97; IS__CGSCC____-NEXT: [[RET:%.*]] = tail call i32 @test0(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 98; IS__CGSCC____-NEXT: [[CMP_EQ_1:%.*]] = icmp eq i32 [[RET]], 10 99; IS__CGSCC____-NEXT: [[CMP_EQ_2:%.*]] = icmp eq i32 [[RET]], 9 100; IS__CGSCC____-NEXT: [[CMP_EQ_3:%.*]] = icmp eq i32 [[RET]], 8 101; IS__CGSCC____-NEXT: [[CMP_EQ_4:%.*]] = icmp eq i32 [[RET]], 1 102; IS__CGSCC____-NEXT: [[CMP_EQ_5:%.*]] = icmp eq i32 [[RET]], 0 103; IS__CGSCC____-NEXT: [[CMP_EQ_6:%.*]] = icmp eq i32 [[RET]], -1 104; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_EQ_1]], i1 [[CMP_EQ_2]], i1 [[CMP_EQ_3]]) 105; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_EQ_4]], i1 [[CMP_EQ_5]], i1 [[CMP_EQ_6]]) 106; IS__CGSCC____-NEXT: [[CMP_NE_1:%.*]] = icmp ne i32 [[RET]], 10 107; IS__CGSCC____-NEXT: [[CMP_NE_2:%.*]] = icmp ne i32 [[RET]], 9 108; IS__CGSCC____-NEXT: [[CMP_NE_3:%.*]] = icmp ne i32 [[RET]], 8 109; IS__CGSCC____-NEXT: [[CMP_NE_4:%.*]] = icmp ne i32 [[RET]], 1 110; IS__CGSCC____-NEXT: [[CMP_NE_5:%.*]] = icmp ne i32 [[RET]], 0 111; IS__CGSCC____-NEXT: [[CMP_NE_6:%.*]] = icmp ne i32 [[RET]], -1 112; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_NE_1]], i1 [[CMP_NE_2]], i1 [[CMP_NE_3]]) 113; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_NE_4]], i1 [[CMP_NE_5]], i1 [[CMP_NE_6]]) 114; IS__CGSCC____-NEXT: [[CMP_UGT_1:%.*]] = icmp ugt i32 [[RET]], 10 115; IS__CGSCC____-NEXT: [[CMP_UGT_2:%.*]] = icmp ugt i32 [[RET]], 9 116; IS__CGSCC____-NEXT: [[CMP_UGT_3:%.*]] = icmp ugt i32 [[RET]], 8 117; IS__CGSCC____-NEXT: [[CMP_UGT_4:%.*]] = icmp ugt i32 [[RET]], 1 118; IS__CGSCC____-NEXT: [[CMP_UGT_5:%.*]] = icmp ugt i32 [[RET]], 0 119; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGT_1]], i1 [[CMP_UGT_2]], i1 [[CMP_UGT_3]]) 120; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGT_4]], i1 [[CMP_UGT_5]], i1 false) 121; IS__CGSCC____-NEXT: [[CMP_UGE_1:%.*]] = icmp uge i32 [[RET]], 10 122; IS__CGSCC____-NEXT: [[CMP_UGE_2:%.*]] = icmp uge i32 [[RET]], 9 123; IS__CGSCC____-NEXT: [[CMP_UGE_3:%.*]] = icmp uge i32 [[RET]], 8 124; IS__CGSCC____-NEXT: [[CMP_UGE_4:%.*]] = icmp uge i32 [[RET]], 1 125; IS__CGSCC____-NEXT: [[CMP_UGE_6:%.*]] = icmp uge i32 [[RET]], -1 126; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGE_1]], i1 [[CMP_UGE_2]], i1 [[CMP_UGE_3]]) 127; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGE_4]], i1 true, i1 [[CMP_UGE_6]]) 128; IS__CGSCC____-NEXT: [[CMP_SGT_1:%.*]] = icmp sgt i32 [[RET]], 10 129; IS__CGSCC____-NEXT: [[CMP_SGT_2:%.*]] = icmp sgt i32 [[RET]], 9 130; IS__CGSCC____-NEXT: [[CMP_SGT_3:%.*]] = icmp sgt i32 [[RET]], 8 131; IS__CGSCC____-NEXT: [[CMP_SGT_4:%.*]] = icmp sgt i32 [[RET]], 1 132; IS__CGSCC____-NEXT: [[CMP_SGT_5:%.*]] = icmp sgt i32 [[RET]], 0 133; IS__CGSCC____-NEXT: [[CMP_SGT_6:%.*]] = icmp sgt i32 [[RET]], -1 134; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SGT_1]], i1 [[CMP_SGT_2]], i1 [[CMP_SGT_3]]) 135; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SGT_4]], i1 [[CMP_SGT_5]], i1 [[CMP_SGT_6]]) 136; IS__CGSCC____-NEXT: [[CMP_GTE_1:%.*]] = icmp sge i32 [[RET]], 10 137; IS__CGSCC____-NEXT: [[CMP_GTE_2:%.*]] = icmp sge i32 [[RET]], 9 138; IS__CGSCC____-NEXT: [[CMP_GTE_3:%.*]] = icmp sge i32 [[RET]], 8 139; IS__CGSCC____-NEXT: [[CMP_GTE_4:%.*]] = icmp sge i32 [[RET]], 1 140; IS__CGSCC____-NEXT: [[CMP_GTE_5:%.*]] = icmp sge i32 [[RET]], 0 141; IS__CGSCC____-NEXT: [[CMP_GTE_6:%.*]] = icmp sge i32 [[RET]], -1 142; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_GTE_1]], i1 [[CMP_GTE_2]], i1 [[CMP_GTE_3]]) 143; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_GTE_4]], i1 [[CMP_GTE_5]], i1 [[CMP_GTE_6]]) 144; IS__CGSCC____-NEXT: [[CMP_SLT_1:%.*]] = icmp slt i32 [[RET]], 10 145; IS__CGSCC____-NEXT: [[CMP_SLT_2:%.*]] = icmp slt i32 [[RET]], 9 146; IS__CGSCC____-NEXT: [[CMP_SLT_3:%.*]] = icmp slt i32 [[RET]], 8 147; IS__CGSCC____-NEXT: [[CMP_SLT_4:%.*]] = icmp slt i32 [[RET]], 1 148; IS__CGSCC____-NEXT: [[CMP_SLT_5:%.*]] = icmp slt i32 [[RET]], 0 149; IS__CGSCC____-NEXT: [[CMP_SLT_6:%.*]] = icmp slt i32 [[RET]], -1 150; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SLT_1]], i1 [[CMP_SLT_2]], i1 [[CMP_SLT_3]]) 151; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SLT_4]], i1 [[CMP_SLT_5]], i1 [[CMP_SLT_6]]) 152; IS__CGSCC____-NEXT: [[CMP_LTE_1:%.*]] = icmp sle i32 [[RET]], 10 153; IS__CGSCC____-NEXT: [[CMP_LTE_2:%.*]] = icmp sle i32 [[RET]], 9 154; IS__CGSCC____-NEXT: [[CMP_LTE_3:%.*]] = icmp sle i32 [[RET]], 8 155; IS__CGSCC____-NEXT: [[CMP_LTE_4:%.*]] = icmp sle i32 [[RET]], 1 156; IS__CGSCC____-NEXT: [[CMP_LTE_5:%.*]] = icmp sle i32 [[RET]], 0 157; IS__CGSCC____-NEXT: [[CMP_LTE_6:%.*]] = icmp sle i32 [[RET]], -1 158; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_LTE_1]], i1 [[CMP_LTE_2]], i1 [[CMP_LTE_3]]) 159; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_LTE_4]], i1 [[CMP_LTE_5]], i1 [[CMP_LTE_6]]) 160; IS__CGSCC____-NEXT: ret void 161; 162 %ret = tail call i32 @test0(i32 *%p) 163 164 ; ret = [0, 10), eq 165 %cmp-eq-1 = icmp eq i32 %ret, 10 166 %cmp-eq-2 = icmp eq i32 %ret, 9 167 %cmp-eq-3 = icmp eq i32 %ret, 8 168 %cmp-eq-4 = icmp eq i32 %ret, 1 169 %cmp-eq-5 = icmp eq i32 %ret, 0 170 %cmp-eq-6 = icmp eq i32 %ret, -1 171 tail call void @use3(i1 %cmp-eq-1, i1 %cmp-eq-2, i1 %cmp-eq-3) 172 tail call void @use3(i1 %cmp-eq-4, i1 %cmp-eq-5, i1 %cmp-eq-6) 173 174 ; ret = [0, 10), ne 175 %cmp-ne-1 = icmp ne i32 %ret, 10 176 %cmp-ne-2 = icmp ne i32 %ret, 9 177 %cmp-ne-3 = icmp ne i32 %ret, 8 178 %cmp-ne-4 = icmp ne i32 %ret, 1 179 %cmp-ne-5 = icmp ne i32 %ret, 0 180 %cmp-ne-6 = icmp ne i32 %ret, -1 181 tail call void @use3(i1 %cmp-ne-1, i1 %cmp-ne-2, i1 %cmp-ne-3) 182 tail call void @use3(i1 %cmp-ne-4, i1 %cmp-ne-5, i1 %cmp-ne-6) 183 184 ; ret = [0, 10), ugt 185 %cmp-ugt-1 = icmp ugt i32 %ret, 10 186 %cmp-ugt-2 = icmp ugt i32 %ret, 9 187 %cmp-ugt-3 = icmp ugt i32 %ret, 8 188 %cmp-ugt-4 = icmp ugt i32 %ret, 1 189 %cmp-ugt-5 = icmp ugt i32 %ret, 0 190 %cmp-ugt-6 = icmp ugt i32 %ret, -1 191 tail call void @use3(i1 %cmp-ugt-1, i1 %cmp-ugt-2, i1 %cmp-ugt-3) 192 tail call void @use3(i1 %cmp-ugt-4, i1 %cmp-ugt-5, i1 %cmp-ugt-6) 193 194 ; ret = [0, 10), uge 195 %cmp-uge-1 = icmp uge i32 %ret, 10 196 %cmp-uge-2 = icmp uge i32 %ret, 9 197 %cmp-uge-3 = icmp uge i32 %ret, 8 198 %cmp-uge-4 = icmp uge i32 %ret, 1 199 %cmp-uge-5 = icmp uge i32 %ret, 0 200 %cmp-uge-6 = icmp uge i32 %ret, -1 201 tail call void @use3(i1 %cmp-uge-1, i1 %cmp-uge-2, i1 %cmp-uge-3) 202 tail call void @use3(i1 %cmp-uge-4, i1 %cmp-uge-5, i1 %cmp-uge-6) 203 204 ; ret = [0, 10), sgt 205 %cmp-sgt-1 = icmp sgt i32 %ret, 10 206 %cmp-sgt-2 = icmp sgt i32 %ret, 9 207 %cmp-sgt-3 = icmp sgt i32 %ret, 8 208 %cmp-sgt-4 = icmp sgt i32 %ret, 1 209 %cmp-sgt-5 = icmp sgt i32 %ret, 0 210 %cmp-sgt-6 = icmp sgt i32 %ret, -1 211 tail call void @use3(i1 %cmp-sgt-1, i1 %cmp-sgt-2, i1 %cmp-sgt-3) 212 tail call void @use3(i1 %cmp-sgt-4, i1 %cmp-sgt-5, i1 %cmp-sgt-6) 213 214 ; ret = [0, 10), sge 215 %cmp-gte-1 = icmp sge i32 %ret, 10 216 %cmp-gte-2 = icmp sge i32 %ret, 9 217 %cmp-gte-3 = icmp sge i32 %ret, 8 218 %cmp-gte-4 = icmp sge i32 %ret, 1 219 %cmp-gte-5 = icmp sge i32 %ret, 0 220 %cmp-gte-6 = icmp sge i32 %ret, -1 221 tail call void @use3(i1 %cmp-gte-1, i1 %cmp-gte-2, i1 %cmp-gte-3) 222 tail call void @use3(i1 %cmp-gte-4, i1 %cmp-gte-5, i1 %cmp-gte-6) 223 224 ; ret = [0, 10), slt 225 %cmp-slt-1 = icmp slt i32 %ret, 10 226 %cmp-slt-2 = icmp slt i32 %ret, 9 227 %cmp-slt-3 = icmp slt i32 %ret, 8 228 %cmp-slt-4 = icmp slt i32 %ret, 1 229 %cmp-slt-5 = icmp slt i32 %ret, 0 230 %cmp-slt-6 = icmp slt i32 %ret, -1 231 tail call void @use3(i1 %cmp-slt-1, i1 %cmp-slt-2, i1 %cmp-slt-3) 232 tail call void @use3(i1 %cmp-slt-4, i1 %cmp-slt-5, i1 %cmp-slt-6) 233 234 ; ret = [0, 10), sle 235 %cmp-lte-1 = icmp sle i32 %ret, 10 236 %cmp-lte-2 = icmp sle i32 %ret, 9 237 %cmp-lte-3 = icmp sle i32 %ret, 8 238 %cmp-lte-4 = icmp sle i32 %ret, 1 239 %cmp-lte-5 = icmp sle i32 %ret, 0 240 %cmp-lte-6 = icmp sle i32 %ret, -1 241 tail call void @use3(i1 %cmp-lte-1, i1 %cmp-lte-2, i1 %cmp-lte-3) 242 tail call void @use3(i1 %cmp-lte-4, i1 %cmp-lte-5, i1 %cmp-lte-6) 243 244 ret void 245} 246define i32 @test1(i32* %p) { 247; CHECK-LABEL: define {{[^@]+}}@test1 248; CHECK-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 249; CHECK-NEXT: [[LOAD_10_100:%.*]] = load i32, i32* [[P]], align 4, !range !1 250; CHECK-NEXT: [[ADD_10_THEN_20_110:%.*]] = add i32 [[LOAD_10_100]], 10 251; CHECK-NEXT: [[MUL_10_THEN_200_1091:%.*]] = mul i32 [[ADD_10_THEN_20_110]], 10 252; CHECK-NEXT: ret i32 [[MUL_10_THEN_200_1091]] 253; 254 %load-10-100 = load i32, i32* %p, !range !1 255 %add-10-then-20-110 = add i32 %load-10-100, 10 256 %mul-10-then-200-1091 = mul i32 %add-10-then-20-110, 10 257 ret i32 %mul-10-then-200-1091 258} 259 260define i1 @test1-check(i32* %p) { 261; 262; IS__TUNIT____-LABEL: define {{[^@]+}}@test1-check 263; IS__TUNIT____-SAME: (i32* nocapture nofree readonly align 4 [[P:%.*]]) 264; IS__TUNIT____-NEXT: [[RES:%.*]] = tail call i32 @test1(i32* nocapture nofree readonly align 4 [[P]]) #4, !range !2 265; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp eq i32 [[RES]], 500 266; IS__TUNIT____-NEXT: ret i1 [[CMP]] 267; 268; IS__CGSCC____-LABEL: define {{[^@]+}}@test1-check 269; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 270; IS__CGSCC____-NEXT: [[RES:%.*]] = tail call i32 @test1(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 271; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp eq i32 [[RES]], 500 272; IS__CGSCC____-NEXT: ret i1 [[CMP]] 273; 274 %res = tail call i32 @test1(i32* %p) 275 %cmp = icmp eq i32 %res, 500 276 ret i1 %cmp 277} 278 279; TEST2 280; int test2(int *p) { return *p == 0 ? 4 : 3; } 281; int test2_check(int *p) { 282; int call = test2(p); 283; if (call == 5) { 284; // dead block 285; return 2; 286; } else { 287; return 3; 288; } 289; } 290 291define i32 @test2(i32* %p) { 292; CHECK-LABEL: define {{[^@]+}}@test2 293; CHECK-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 294; CHECK-NEXT: entry: 295; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P]], align 4 296; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP0]], 0 297; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 4, i32 3 298; CHECK-NEXT: ret i32 [[COND]] 299; 300entry: 301 %0 = load i32, i32* %p, align 4 302 %tobool = icmp eq i32 %0, 0 303 %cond = select i1 %tobool, i32 4, i32 3 304 ret i32 %cond 305} 306 307define i32 @test2_check(i32* %p) { 308; IS__TUNIT____-LABEL: define {{[^@]+}}@test2_check 309; IS__TUNIT____-SAME: (i32* nocapture nofree readnone align 4 [[P:%.*]]) 310; IS__TUNIT____-NEXT: entry: 311; IS__TUNIT____-NEXT: br label [[IF_THEN:%.*]] 312; IS__TUNIT____: if.then: 313; IS__TUNIT____-NEXT: br label [[RETURN:%.*]] 314; IS__TUNIT____: if.end: 315; IS__TUNIT____-NEXT: unreachable 316; IS__TUNIT____: return: 317; IS__TUNIT____-NEXT: ret i32 2 318; 319; IS__CGSCC____-LABEL: define {{[^@]+}}@test2_check 320; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 321; IS__CGSCC____-NEXT: entry: 322; IS__CGSCC____-NEXT: [[CALL:%.*]] = tail call i32 @test2(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 323; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp slt i32 [[CALL]], 5 324; IS__CGSCC____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 325; IS__CGSCC____: if.then: 326; IS__CGSCC____-NEXT: br label [[RETURN:%.*]] 327; IS__CGSCC____: if.end: 328; IS__CGSCC____-NEXT: br label [[RETURN]] 329; IS__CGSCC____: return: 330; IS__CGSCC____-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 2, [[IF_THEN]] ], [ 3, [[IF_END]] ] 331; IS__CGSCC____-NEXT: ret i32 [[RETVAL_0]] 332; 333entry: 334 %call = tail call i32 @test2(i32* %p) 335 %cmp = icmp slt i32 %call, 5 336 br i1 %cmp, label %if.then, label %if.end 337 338if.then: ; preds = %entry 339 br label %return 340 341if.end: ; preds = %entry 342 br label %return 343 344return: ; preds = %if.end, %if.then 345 %retval.0 = phi i32 [ 2, %if.then ], [ 3, %if.end ] 346 ret i32 %retval.0 347} 348 349; TEST 3 SECV test 350 351; void unkown(); 352; int r1(unsigned int u){ 353; int sum = 0; 354; for(int i = 0; i<100;i++){ 355; sum += i; 356; } 357; // sum = 50 * 49 / 2 358; if(sum > 10000){ 359; // dead block 360; return 20; 361; }else { 362; return 10; 363; } 364; } 365; void f1(int u){ 366; if(r1(u) > 15){ 367; // deadblock 368; unkown(); 369; }else { 370; return; 371; } 372; } 373 374declare dso_local void @unkown() 375 376define internal i32 @r1(i32) local_unnamed_addr { 377; IS________OPM-LABEL: define {{[^@]+}}@r1() local_unnamed_addr 378; IS________OPM-NEXT: br label [[TMP4:%.*]] 379; IS________OPM: 1: 380; IS________OPM-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP7:%.*]], 10000 381; IS________OPM-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[F:%.*]] 382; IS________OPM: 3: 383; IS________OPM-NEXT: ret i32 20 384; IS________OPM: f: 385; IS________OPM-NEXT: ret i32 10 386; IS________OPM: 4: 387; IS________OPM-NEXT: [[TMP5:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP8:%.*]], [[TMP4]] ] 388; IS________OPM-NEXT: [[TMP6:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[TMP7]], [[TMP4]] ] 389; IS________OPM-NEXT: [[TMP7]] = add nuw nsw i32 [[TMP5]], [[TMP6]] 390; IS________OPM-NEXT: [[TMP8]] = add nuw nsw i32 [[TMP5]], 1 391; IS________OPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 100 392; IS________OPM-NEXT: br i1 [[TMP9]], label [[TMP1:%.*]], label [[TMP4]] 393; 394; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@r1() local_unnamed_addr 395; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] 396; IS__CGSCC_NPM: 1: 397; IS__CGSCC_NPM-NEXT: br label [[F:%.*]] 398; IS__CGSCC_NPM: 2: 399; IS__CGSCC_NPM-NEXT: unreachable 400; IS__CGSCC_NPM: f: 401; IS__CGSCC_NPM-NEXT: ret i32 10 402; IS__CGSCC_NPM: 3: 403; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[TMP3]] ] 404; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[TMP6:%.*]], [[TMP3]] ] 405; IS__CGSCC_NPM-NEXT: [[TMP6]] = add nuw nsw i32 [[TMP4]], [[TMP5]] 406; IS__CGSCC_NPM-NEXT: [[TMP7]] = add nuw nsw i32 [[TMP4]], 1 407; IS__CGSCC_NPM-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 100 408; IS__CGSCC_NPM-NEXT: br i1 [[TMP8]], label [[TMP1:%.*]], label [[TMP3]] 409; 410 br label %5 411 4122: ; preds = %5 413 %3 = icmp sgt i32 %8, 10000 414 br i1 %3, label %4, label %f 4154: 416 ret i32 20 417f: 418 ret i32 10 4195: ; preds = %5, %1 420 %6 = phi i32 [ 0, %1 ], [ %9, %5 ] 421 %7 = phi i32 [ 0, %1 ], [ %8, %5 ] 422 %8 = add nuw nsw i32 %6, %7 423 %9 = add nuw nsw i32 %6, 1 424 %10 = icmp eq i32 %9, 100 425 br i1 %10, label %2, label %5 426} 427 428define void @f1(i32){ 429; IS________OPM-LABEL: define {{[^@]+}}@f1 430; IS________OPM-SAME: (i32 [[TMP0:%.*]]) 431; IS________OPM-NEXT: [[TMP2:%.*]] = tail call i32 @r1() 432; IS________OPM-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 15 433; IS________OPM-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP5:%.*]] 434; IS________OPM: 4: 435; IS________OPM-NEXT: tail call void @unkown() 436; IS________OPM-NEXT: br label [[TMP5]] 437; IS________OPM: 5: 438; IS________OPM-NEXT: ret void 439; 440; IS________NPM-LABEL: define {{[^@]+}}@f1 441; IS________NPM-SAME: (i32 [[TMP0:%.*]]) 442; IS________NPM-NEXT: br label [[TMP3:%.*]] 443; IS________NPM: 2: 444; IS________NPM-NEXT: unreachable 445; IS________NPM: 3: 446; IS________NPM-NEXT: ret void 447; 448 %2 = tail call i32 @r1(i32 %0) 449 %3 = icmp sgt i32 %2, 15 450 br i1 %3, label %4, label %5 451 4524: ; preds = %1 453 tail call void @unkown() 454 br label %5 455 4565: ; preds = %1, %4 457 ret void 458} 459 460; TEST4 LVI test 461 462; f1 463; int test4-f1(int u){ 464; if(u>=0) { 465; return u; 466; }else{ 467; return 0; 468; } 469; } 470define dso_local i32 @test4-f1(i32 %u) { 471; CHECK-LABEL: define {{[^@]+}}@test4-f1 472; CHECK-SAME: (i32 [[U:%.*]]) 473; CHECK-NEXT: entry: 474; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[U]], -1 475; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[RETURN:%.*]] 476; CHECK: if.then: 477; CHECK-NEXT: br label [[RETURN]] 478; CHECK: return: 479; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[U]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ] 480; CHECK-NEXT: ret i32 [[RETVAL_0]] 481; 482; FIXME: RETVAL_0 >= 0 483entry: 484 %cmp = icmp sgt i32 %u, -1 485 br i1 %cmp, label %if.then, label %return 486 487if.then: ; preds = %entry 488 br label %return 489 490return: ; preds = %entry, %if.then 491 %retval.0 = phi i32 [ %u, %if.then ], [ 0, %entry ] 492 ret i32 %retval.0 493} 494 495 496define dso_local i32 @test4-g1(i32 %u) { 497; CHECK-LABEL: define {{[^@]+}}@test4-g1 498; CHECK-SAME: (i32 [[U:%.*]]) 499; CHECK-NEXT: entry: 500; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @test4-f1(i32 [[U]]) 501; CHECK-NEXT: ret i32 [[CALL]] 502; 503; FIXME: %call should have range [0, inf] 504 505entry: 506 %call = tail call i32 @test4-f1(i32 %u) 507 ret i32 %call 508} 509 510; f2 511; int test4-f1(int u){ 512; if(u>-1) { 513; return u+1; 514; }else{ 515; return 1; 516; } 517; } 518define dso_local i32 @test4-f2(i32 %u) { 519; CHECK-LABEL: define {{[^@]+}}@test4-f2 520; CHECK-SAME: (i32 [[U:%.*]]) 521; CHECK-NEXT: entry: 522; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[U]], -1 523; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] 524; CHECK: if.then: 525; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[U]], 1 526; CHECK-NEXT: br label [[RETURN:%.*]] 527; CHECK: if.else: 528; CHECK-NEXT: br label [[RETURN]] 529; CHECK: return: 530; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ 1, [[IF_ELSE]] ] 531; CHECK-NEXT: ret i32 [[RETVAL_0]] 532; 533entry: 534 %cmp = icmp sgt i32 %u, -1 535 br i1 %cmp, label %if.then, label %if.else 536 537if.then: ; preds = %entry 538 %add = add nuw nsw i32 %u, 1 539 br label %return 540 541if.else: ; preds = %entry 542 br label %return 543 544return: ; preds = %if.else, %if.then 545 %retval.0 = phi i32 [ %add, %if.then ], [ 1, %if.else ] 546 ret i32 %retval.0 547} 548 549 550define dso_local i32 @test4-g2(i32 %u) { 551; NOT_TUNIT_NPM-LABEL: define {{[^@]+}}@test4-g2 552; NOT_TUNIT_NPM-SAME: (i32 [[U:%.*]]) 553; NOT_TUNIT_NPM-NEXT: entry: 554; NOT_TUNIT_NPM-NEXT: [[CALL:%.*]] = tail call i32 @test4-f2(i32 [[U]]) 555; NOT_TUNIT_NPM-NEXT: ret i32 [[CALL]] 556; 557; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@test4-g2 558; IS__TUNIT_NPM-SAME: (i32 [[U:%.*]]) 559; IS__TUNIT_NPM-NEXT: entry: 560; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = tail call i32 @test4-f2(i32 [[U]]) #2, !range !3 561; IS__TUNIT_NPM-NEXT: ret i32 [[CALL]] 562; 563entry: 564 %call = tail call i32 @test4-f2(i32 %u) 565 ret i32 %call 566} 567 568define dso_local i32 @test-5() { 569; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@test-5() 570; IS__TUNIT_OPM-NEXT: entry: 571; IS__TUNIT_OPM-NEXT: [[CALL:%.*]] = call i32 @rec(i32 0), !range !3 572; IS__TUNIT_OPM-NEXT: ret i32 [[CALL]] 573; 574; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@test-5() 575; IS__TUNIT_NPM-NEXT: entry: 576; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = call i32 @rec(i32 0), !range !4 577; IS__TUNIT_NPM-NEXT: ret i32 [[CALL]] 578; 579; IS__CGSCC____-LABEL: define {{[^@]+}}@test-5() 580; IS__CGSCC____-NEXT: entry: 581; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32 @rec(i32 0) 582; IS__CGSCC____-NEXT: ret i32 [[CALL]] 583; 584entry: 585 %call = call i32 @rec(i32 0) 586 ret i32 %call 587} 588define internal i32 @rec(i32 %depth) { 589; CHECK-LABEL: define {{[^@]+}}@rec 590; CHECK-SAME: (i32 [[DEPTH:%.*]]) 591; CHECK-NEXT: entry: 592; CHECK-NEXT: [[CALL:%.*]] = call i32 @foo(i32 [[DEPTH]]) 593; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL]], 0 594; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 595; CHECK: if.then: 596; CHECK-NEXT: br label [[RETURN:%.*]] 597; CHECK: if.end: 598; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[DEPTH]], 10 599; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN1:%.*]], label [[IF_END3:%.*]] 600; CHECK: if.then1: 601; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[DEPTH]], 1 602; CHECK-NEXT: [[CALL2:%.*]] = call i32 @rec(i32 [[ADD]]) 603; CHECK-NEXT: br label [[IF_END3]] 604; CHECK: if.end3: 605; CHECK-NEXT: br label [[RETURN]] 606; CHECK: return: 607; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_THEN]] ], [ 1, [[IF_END3]] ] 608; CHECK-NEXT: ret i32 [[RETVAL_0]] 609; 610entry: 611 %call = call i32 @foo(i32 %depth) 612 %tobool = icmp ne i32 %call, 0 613 br i1 %tobool, label %if.then, label %if.end 614 615if.then: ; preds = %entry 616 br label %return 617 618if.end: ; preds = %entry 619 %cmp = icmp slt i32 %depth, 10 620 br i1 %cmp, label %if.then1, label %if.end3 621 622if.then1: ; preds = %if.end 623 %add = add nsw i32 %depth, 1 624 %call2 = call i32 @rec(i32 %add) 625 br label %if.end3 626 627if.end3: ; preds = %if.then1, %if.end 628 br label %return 629 630return: ; preds = %if.end3, %if.then 631 %retval.0 = phi i32 [ 0, %if.then ], [ 1, %if.end3 ] 632 ret i32 %retval.0 633} 634declare dso_local i32 @foo(i32) 635 636 637; Examples taken from https://llvm.discourse.group/t/impossible-condition-optimization/461/1 638; 639; The important part is that we return a constant (false) 640; 641; { 642 643; FIXME: All but the return is not needed anymore 644define dso_local zeroext i1 @phi(i32 %arg) { 645; CHECK-LABEL: define {{[^@]+}}@phi 646; CHECK-SAME: (i32 [[ARG:%.*]]) 647; CHECK-NEXT: bb: 648; CHECK-NEXT: [[TMP:%.*]] = icmp sgt i32 [[ARG]], 5 649; CHECK-NEXT: br i1 [[TMP]], label [[BB1:%.*]], label [[BB2:%.*]] 650; CHECK: bb1: 651; CHECK-NEXT: br label [[BB3:%.*]] 652; CHECK: bb2: 653; CHECK-NEXT: br label [[BB3]] 654; CHECK: bb3: 655; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[ARG]], 10 656; CHECK-NEXT: br i1 [[TMP4]], label [[BB5:%.*]], label [[BB7:%.*]] 657; CHECK: bb5: 658; CHECK-NEXT: br label [[BB9:%.*]] 659; CHECK: bb7: 660; CHECK-NEXT: br label [[BB9]] 661; CHECK: bb9: 662; CHECK-NEXT: br label [[BB12:%.*]] 663; CHECK: bb11: 664; CHECK-NEXT: unreachable 665; CHECK: bb12: 666; CHECK-NEXT: br label [[BB13:%.*]] 667; CHECK: bb13: 668; CHECK-NEXT: ret i1 false 669; 670bb: 671 %tmp = icmp sgt i32 %arg, 5 672 br i1 %tmp, label %bb1, label %bb2 673 674bb1: ; preds = %bb 675 br label %bb3 676 677bb2: ; preds = %bb 678 br label %bb3 679 680bb3: ; preds = %bb2, %bb1 681 %.02 = phi i32 [ 1, %bb1 ], [ 2, %bb2 ] 682 %tmp4 = icmp sgt i32 %arg, 10 683 br i1 %tmp4, label %bb5, label %bb7 684 685bb5: ; preds = %bb3 686 %tmp6 = add nsw i32 %.02, 1 687 br label %bb9 688 689bb7: ; preds = %bb3 690 %tmp8 = add nsw i32 %.02, 2 691 br label %bb9 692 693bb9: ; preds = %bb7, %bb5 694 %.01 = phi i32 [ %tmp6, %bb5 ], [ %tmp8, %bb7 ] 695 %tmp10 = icmp eq i32 %.01, 5 696 br i1 %tmp10, label %bb11, label %bb12 697 698bb11: ; preds = %bb9 699 br label %bb13 700 701bb12: ; preds = %bb9 702 br label %bb13 703 704bb13: ; preds = %bb12, %bb11 705 %.0 = phi i1 [ true, %bb11 ], [ false, %bb12 ] 706 ret i1 %.0 707} 708 709define dso_local i1 @select(i32 %a) local_unnamed_addr #0 { 710; CHECK-LABEL: define {{[^@]+}}@select 711; CHECK-SAME: (i32 [[A:%.*]]) local_unnamed_addr 712; CHECK-NEXT: entry: 713; CHECK-NEXT: ret i1 false 714; 715entry: 716 %cmp = icmp sgt i32 %a, 5 717 %. = select i1 %cmp, i32 1, i32 2 718 %cmp1 = icmp sgt i32 %a, 10 719 %y.0.v = select i1 %cmp1, i32 1, i32 2 720 %y.0 = add nuw nsw i32 %., %y.0.v 721 %cmp6 = icmp eq i32 %y.0, 5 722 ret i1 %cmp6 723} 724 725define dso_local i32 @select_zext(i32 %a) local_unnamed_addr #0 { 726; CHECK-LABEL: define {{[^@]+}}@select_zext 727; CHECK-SAME: (i32 [[A:%.*]]) local_unnamed_addr 728; CHECK-NEXT: entry: 729; CHECK-NEXT: ret i32 0 730; 731entry: 732 %cmp = icmp sgt i32 %a, 5 733 %. = select i1 %cmp, i32 1, i32 2 734 %cmp1 = icmp sgt i32 %a, 10 735 %y.0.v = select i1 %cmp1, i32 1, i32 2 736 %y.0 = add nuw nsw i32 %., %y.0.v 737 %cmp6 = icmp eq i32 %y.0, 5 738 %.13 = zext i1 %cmp6 to i32 739 ret i32 %.13 740} 741 742; FIXME: We do not look through the ptr casts here. 743define dso_local i64 @select_int2ptr_bitcast_ptr2int(i32 %a) local_unnamed_addr #0 { 744; CHECK-LABEL: define {{[^@]+}}@select_int2ptr_bitcast_ptr2int 745; CHECK-SAME: (i32 [[A:%.*]]) local_unnamed_addr 746; CHECK-NEXT: entry: 747; CHECK-NEXT: [[I2P:%.*]] = inttoptr i1 false to i1* 748; CHECK-NEXT: [[BC:%.*]] = bitcast i1* [[I2P]] to i32* 749; CHECK-NEXT: [[P2I:%.*]] = ptrtoint i32* [[BC]] to i64 750; CHECK-NEXT: ret i64 [[P2I]] 751; 752entry: 753 %cmp = icmp sgt i32 %a, 5 754 %. = select i1 %cmp, i32 1, i32 2 755 %cmp1 = icmp sgt i32 %a, 10 756 %y.0.v = select i1 %cmp1, i32 1, i32 2 757 %y.0 = add nuw nsw i32 %., %y.0.v 758 %cmp6 = icmp eq i32 %y.0, 5 759 %i2p = inttoptr i1 %cmp6 to i1* 760 %bc = bitcast i1* %i2p to i32* 761 %p2i = ptrtoint i32* %bc to i64 762 ret i64 %p2i 763} 764 765; } 766 767define i1 @f_fcmp(float %a, float %b) { 768; CHECK-LABEL: define {{[^@]+}}@f_fcmp 769; CHECK-SAME: (float [[A:%.*]], float [[B:%.*]]) 770; CHECK-NEXT: [[R:%.*]] = fcmp uge float [[A]], [[B]] 771; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 772; CHECK-NEXT: ret i1 [[S]] 773; 774 %r = fcmp uge float %a, %b 775 %s = select i1 %r, i1 %r, i1 0 776 ret i1 %s 777} 778define i1 @d_fcmp(double %a, double %b) { 779; CHECK-LABEL: define {{[^@]+}}@d_fcmp 780; CHECK-SAME: (double [[A:%.*]], double [[B:%.*]]) 781; CHECK-NEXT: [[R:%.*]] = fcmp oeq double [[A]], [[B]] 782; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 783; CHECK-NEXT: ret i1 [[S]] 784; 785 %r = fcmp oeq double %a, %b 786 %s = select i1 %r, i1 %r, i1 0 787 ret i1 %s 788} 789define i1 @dp_icmp(double* %a, double* %b) { 790; CHECK-LABEL: define {{[^@]+}}@dp_icmp 791; CHECK-SAME: (double* nofree readnone [[A:%.*]], double* nofree readnone [[B:%.*]]) 792; CHECK-NEXT: [[R:%.*]] = icmp sge double* [[A]], [[B]] 793; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 794; CHECK-NEXT: ret i1 [[S]] 795; 796 %r = icmp sge double* %a, %b 797 %s = select i1 %r, i1 %r, i1 0 798 ret i1 %s 799} 800define i1 @ip_icmp(i8* %a, i8* %b) { 801; CHECK-LABEL: define {{[^@]+}}@ip_icmp 802; CHECK-SAME: (i8* nofree readnone [[A:%.*]], i8* nofree readnone [[B:%.*]]) 803; CHECK-NEXT: [[R:%.*]] = icmp ult i8* [[A]], [[B]] 804; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 805; CHECK-NEXT: ret i1 [[S]] 806; 807 %r = icmp ult i8* %a, %b 808 %s = select i1 %r, i1 %r, i1 0 809 ret i1 %s 810} 811define i1 @fcmp_caller(float %fa, float %fb, double %da, double %db, double* %dpa, double* %dpb, i8* %ipa, i8* %ipb) { 812; CHECK-LABEL: define {{[^@]+}}@fcmp_caller 813; CHECK-SAME: (float [[FA:%.*]], float [[FB:%.*]], double [[DA:%.*]], double [[DB:%.*]], double* nofree readnone [[DPA:%.*]], double* nofree readnone [[DPB:%.*]], i8* nofree readnone [[IPA:%.*]], i8* nofree readnone [[IPB:%.*]]) 814; CHECK-NEXT: [[R1:%.*]] = call i1 @f_fcmp(float [[FA]], float [[FB]]) 815; CHECK-NEXT: [[R2:%.*]] = call i1 @d_fcmp(double [[DA]], double [[DB]]) 816; CHECK-NEXT: [[R3:%.*]] = call i1 @dp_icmp(double* noalias nofree readnone [[DPA]], double* noalias nofree readnone [[DPB]]) 817; CHECK-NEXT: [[R4:%.*]] = call i1 @ip_icmp(i8* noalias nofree readnone [[IPA]], i8* noalias nofree readnone [[IPB]]) 818; CHECK-NEXT: [[O1:%.*]] = or i1 [[R1]], [[R2]] 819; CHECK-NEXT: [[O2:%.*]] = or i1 [[R3]], [[R4]] 820; CHECK-NEXT: [[O3:%.*]] = or i1 [[O1]], [[O2]] 821; CHECK-NEXT: ret i1 [[O3]] 822; 823 %r1 = call i1 @f_fcmp(float %fa, float %fb) 824 %r2 = call i1 @d_fcmp(double %da, double %db) 825 %r3 = call i1 @dp_icmp(double* %dpa, double* %dpb) 826 %r4 = call i1 @ip_icmp(i8* %ipa, i8* %ipb) 827 %o1 = or i1 %r1, %r2 828 %o2 = or i1 %r3, %r4 829 %o3 = or i1 %o1, %o2 830 ret i1 %o3 831} 832 833define i8 @ret_two() { 834; CHECK-LABEL: define {{[^@]+}}@ret_two() 835; CHECK-NEXT: ret i8 2 836; 837 ret i8 2 838} 839define i8 @ret_undef() { 840; CHECK-LABEL: define {{[^@]+}}@ret_undef() 841; CHECK-NEXT: ret i8 undef 842; 843 ret i8 undef 844} 845 846; Verify we collapse undef to a value and return something non-undef here. 847define i8 @undef_collapse_1() { 848; CHECK-LABEL: define {{[^@]+}}@undef_collapse_1() 849; CHECK-NEXT: ret i8 0 850; 851 %c = call i8 @ret_undef() 852 %s = shl i8 %c, 2 853 ret i8 %s 854} 855 856; Verify we collapse undef to a value and return something non-undef here. 857define i8 @undef_collapse_2() { 858; CHECK-LABEL: define {{[^@]+}}@undef_collapse_2() 859; CHECK-NEXT: ret i8 0 860; 861 %c = call i8 @ret_two() 862 %s = shl i8 undef, %c 863 ret i8 %s 864} 865 866define i8 @undef_collapse_caller() { 867; 868; IS__TUNIT____-LABEL: define {{[^@]+}}@undef_collapse_caller() 869; IS__TUNIT____-NEXT: ret i8 0 870; 871; IS__CGSCC____-LABEL: define {{[^@]+}}@undef_collapse_caller() 872; IS__CGSCC____-NEXT: [[C1:%.*]] = call i8 @undef_collapse_1() 873; IS__CGSCC____-NEXT: [[C2:%.*]] = call i8 @undef_collapse_2() 874; IS__CGSCC____-NEXT: [[A:%.*]] = add i8 [[C1]], [[C2]] 875; IS__CGSCC____-NEXT: ret i8 [[A]] 876; 877 %c1 = call i8 @undef_collapse_1() 878 %c2 = call i8 @undef_collapse_2() 879 %a = add i8 %c1, %c2 880 ret i8 %a 881} 882 883define i32 @ret1or2(i1 %c) { 884; CHECK-LABEL: define {{[^@]+}}@ret1or2 885; CHECK-SAME: (i1 [[C:%.*]]) 886; CHECK-NEXT: [[S:%.*]] = select i1 [[C]], i32 1, i32 2 887; CHECK-NEXT: ret i32 [[S]] 888; 889 %s = select i1 %c, i32 1, i32 2 890 ret i32 %s 891} 892define i1 @callee_range_1(i1 %c1, i1 %c2, i1 %c3) { 893; 894; IS__TUNIT____-LABEL: define {{[^@]+}}@callee_range_1 895; IS__TUNIT____-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]], i1 [[C3:%.*]]) 896; IS__TUNIT____-NEXT: ret i1 true 897; 898; IS__CGSCC____-LABEL: define {{[^@]+}}@callee_range_1 899; IS__CGSCC____-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]], i1 [[C3:%.*]]) 900; IS__CGSCC____-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) 901; IS__CGSCC____-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) 902; IS__CGSCC____-NEXT: [[INDIRECTION:%.*]] = select i1 [[C3]], i32 [[R1]], i32 [[R2]] 903; IS__CGSCC____-NEXT: [[A:%.*]] = add i32 [[R1]], [[INDIRECTION]] 904; IS__CGSCC____-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 4 905; IS__CGSCC____-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 906; IS__CGSCC____-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 907; IS__CGSCC____-NEXT: ret i1 [[F]] 908; 909 %r1 = call i32 @ret1or2(i1 %c1) 910 %r2 = call i32 @ret1or2(i1 %c2) 911 %indirection = select i1 %c3, i32 %r1, i32 %r2 912 %a = add i32 %r1, %indirection 913 %i1 = icmp sle i32 %a, 4 914 %i2 = icmp sge i32 %a, 2 915 %f = and i1 %i1, %i2 916 ret i1 %f 917} 918 919define i1 @callee_range_2(i1 %c1, i1 %c2) { 920; 921; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@callee_range_2 922; IS__TUNIT_OPM-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]]) 923; IS__TUNIT_OPM-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) #2, !range !4 924; IS__TUNIT_OPM-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) #3, !range !4 925; IS__TUNIT_OPM-NEXT: [[A:%.*]] = add i32 [[R1]], [[R2]] 926; IS__TUNIT_OPM-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 3 927; IS__TUNIT_OPM-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 928; IS__TUNIT_OPM-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 929; IS__TUNIT_OPM-NEXT: ret i1 [[F]] 930; 931; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@callee_range_2 932; IS__TUNIT_NPM-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]]) 933; IS__TUNIT_NPM-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) #2, !range !5 934; IS__TUNIT_NPM-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) #3, !range !5 935; IS__TUNIT_NPM-NEXT: [[A:%.*]] = add i32 [[R1]], [[R2]] 936; IS__TUNIT_NPM-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 3 937; IS__TUNIT_NPM-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 938; IS__TUNIT_NPM-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 939; IS__TUNIT_NPM-NEXT: ret i1 [[F]] 940; 941; IS__CGSCC____-LABEL: define {{[^@]+}}@callee_range_2 942; IS__CGSCC____-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]]) 943; IS__CGSCC____-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) 944; IS__CGSCC____-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) 945; IS__CGSCC____-NEXT: [[A:%.*]] = add i32 [[R1]], [[R2]] 946; IS__CGSCC____-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 3 947; IS__CGSCC____-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 948; IS__CGSCC____-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 949; IS__CGSCC____-NEXT: ret i1 [[F]] 950; 951 %r1 = call i32 @ret1or2(i1 %c1) 952 %r2 = call i32 @ret1or2(i1 %c2) 953 %a = add i32 %r1, %r2 954 %i1 = icmp sle i32 %a, 3 955 %i2 = icmp sge i32 %a, 2 956 %f = and i1 %i1, %i2 957 ret i1 %f 958} 959 960 961define i32 @ret100() { 962; CHECK-LABEL: define {{[^@]+}}@ret100() 963; CHECK-NEXT: ret i32 100 964; 965 ret i32 100 966} 967 968define i1 @ctx_adjustment(i32 %V) { 969; 970; IS________OPM-LABEL: define {{[^@]+}}@ctx_adjustment 971; IS________OPM-SAME: (i32 [[V:%.*]]) 972; IS________OPM-NEXT: [[C1:%.*]] = icmp sge i32 [[V]], 100 973; IS________OPM-NEXT: br i1 [[C1]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] 974; IS________OPM: if.true: 975; IS________OPM-NEXT: br label [[END:%.*]] 976; IS________OPM: if.false: 977; IS________OPM-NEXT: br label [[END]] 978; IS________OPM: end: 979; IS________OPM-NEXT: [[PHI:%.*]] = phi i32 [ [[V]], [[IF_TRUE]] ], [ 100, [[IF_FALSE]] ] 980; IS________OPM-NEXT: [[C2:%.*]] = icmp sge i32 [[PHI]], 100 981; IS________OPM-NEXT: ret i1 [[C2]] 982; 983; IS________NPM-LABEL: define {{[^@]+}}@ctx_adjustment 984; IS________NPM-SAME: (i32 [[V:%.*]]) 985; IS________NPM-NEXT: [[C1:%.*]] = icmp sge i32 [[V]], 100 986; IS________NPM-NEXT: br i1 [[C1]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] 987; IS________NPM: if.true: 988; IS________NPM-NEXT: br label [[END:%.*]] 989; IS________NPM: if.false: 990; IS________NPM-NEXT: br label [[END]] 991; IS________NPM: end: 992; IS________NPM-NEXT: ret i1 true 993; 994 %c1 = icmp sge i32 %V, 100 995 br i1 %c1, label %if.true, label %if.false 996if.true: 997 br label %end 998if.false: 999 %call = call i32 @ret100() 1000 br label %end 1001end: 1002 %phi = phi i32 [ %V, %if.true ], [ %call, %if.false ] 1003 %c2 = icmp sge i32 %phi, 100 1004 ret i1 %c2 1005} 1006 1007 1008!0 = !{i32 0, i32 10} 1009!1 = !{i32 10, i32 100} 1010 1011; NOT_TUNIT____: !0 = !{i32 0, i32 10} 1012; NOT_TUNIT____: !1 = !{i32 10, i32 100} 1013; NOT_TUNIT____-NOT: !2 1014 1015; IS__TUNIT_OPM: !0 = !{i32 0, i32 10} 1016; IS__TUNIT_OPM: !1 = !{i32 10, i32 100} 1017; IS__TUNIT_OPM: !2 = !{i32 200, i32 1091} 1018; IS__TUNIT_OPM: !3 = !{i32 0, i32 2} 1019; IS__TUNIT_OPM: !4 = !{i32 1, i32 3} 1020; IS__TUNIT_OPM-NOT: !5 1021 1022; IS__TUNIT_NPM: !0 = !{i32 0, i32 10} 1023; IS__TUNIT_NPM: !1 = !{i32 10, i32 100} 1024; IS__TUNIT_NPM: !2 = !{i32 200, i32 1091} 1025; IS__TUNIT_NPM: !3 = !{i32 1, i32 -2147483648} 1026; IS__TUNIT_NPM: !4 = !{i32 0, i32 2} 1027; IS__TUNIT_NPM: !5 = !{i32 1, i32 3} 1028; IS__TUNIT_NPM-NOT: !6 1029