1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes 2; RUN: opt -attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=8 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM 3; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=15 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM 4; RUN: opt -attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM 5; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM 6 7; FIXME: CGSCC is not looking at callees and calleers even though it could be allowed. 8 9define i32 @test0(i32* %p) { 10; CHECK-LABEL: define {{[^@]+}}@test0 11; CHECK-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 12; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[P]], align 4, !range !0 13; CHECK-NEXT: ret i32 [[A]] 14; 15 %a = load i32, i32* %p, !range !0 16 ret i32 %a 17} 18 19define i32 @test0-range-check(i32* %p) { 20; IS__TUNIT____-LABEL: define {{[^@]+}}@test0-range-check 21; IS__TUNIT____-SAME: (i32* nocapture nofree readonly align 4 [[P:%.*]]) 22; IS__TUNIT____-NEXT: [[A:%.*]] = tail call i32 @test0(i32* nocapture nofree readonly align 4 [[P]]) #4, !range !0 23; IS__TUNIT____-NEXT: ret i32 [[A]] 24; 25; IS__CGSCC____-LABEL: define {{[^@]+}}@test0-range-check 26; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 27; IS__CGSCC____-NEXT: [[A:%.*]] = tail call i32 @test0(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 28; IS__CGSCC____-NEXT: ret i32 [[A]] 29; 30 %a = tail call i32 @test0(i32* %p) 31 ret i32 %a 32} 33 34declare void @use3-dummy(i1, i1, i1) 35define void @use3(i1, i1, i1) { 36; CHECK-LABEL: define {{[^@]+}}@use3 37; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]], i1 [[TMP2:%.*]]) 38; CHECK-NEXT: tail call void @use3-dummy(i1 [[TMP0]], i1 [[TMP1]], i1 [[TMP2]]) 39; CHECK-NEXT: ret void 40; 41 tail call void @use3-dummy(i1 %0, i1 %1, i1 %2) 42 ret void 43} 44 45; TEST0 icmp test 46define void @test0-icmp-check(i32* %p){ 47 ; ret = [0, 10) 48; IS__TUNIT____-LABEL: define {{[^@]+}}@test0-icmp-check 49; IS__TUNIT____-SAME: (i32* nocapture nofree readonly align 4 [[P:%.*]]) 50; IS__TUNIT____-NEXT: [[RET:%.*]] = tail call i32 @test0(i32* nocapture nofree readonly align 4 [[P]]) #4, !range !0 51; IS__TUNIT____-NEXT: [[CMP_EQ_2:%.*]] = icmp eq i32 [[RET]], 9 52; IS__TUNIT____-NEXT: [[CMP_EQ_3:%.*]] = icmp eq i32 [[RET]], 8 53; IS__TUNIT____-NEXT: [[CMP_EQ_4:%.*]] = icmp eq i32 [[RET]], 1 54; IS__TUNIT____-NEXT: [[CMP_EQ_5:%.*]] = icmp eq i32 [[RET]], 0 55; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 [[CMP_EQ_2]], i1 [[CMP_EQ_3]]) 56; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_EQ_4]], i1 [[CMP_EQ_5]], i1 false) 57; IS__TUNIT____-NEXT: [[CMP_NE_2:%.*]] = icmp ne i32 [[RET]], 9 58; IS__TUNIT____-NEXT: [[CMP_NE_3:%.*]] = icmp ne i32 [[RET]], 8 59; IS__TUNIT____-NEXT: [[CMP_NE_4:%.*]] = icmp ne i32 [[RET]], 1 60; IS__TUNIT____-NEXT: [[CMP_NE_5:%.*]] = icmp ne i32 [[RET]], 0 61; IS__TUNIT____-NEXT: tail call void @use3(i1 true, i1 [[CMP_NE_2]], i1 [[CMP_NE_3]]) 62; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_NE_4]], i1 [[CMP_NE_5]], i1 true) 63; IS__TUNIT____-NEXT: [[CMP_UGT_3:%.*]] = icmp ugt i32 [[RET]], 8 64; IS__TUNIT____-NEXT: [[CMP_UGT_4:%.*]] = icmp ugt i32 [[RET]], 1 65; IS__TUNIT____-NEXT: [[CMP_UGT_5:%.*]] = icmp ugt i32 [[RET]], 0 66; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 false, i1 [[CMP_UGT_3]]) 67; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_UGT_4]], i1 [[CMP_UGT_5]], i1 false) 68; IS__TUNIT____-NEXT: [[CMP_UGE_2:%.*]] = icmp uge i32 [[RET]], 9 69; IS__TUNIT____-NEXT: [[CMP_UGE_3:%.*]] = icmp uge i32 [[RET]], 8 70; IS__TUNIT____-NEXT: [[CMP_UGE_4:%.*]] = icmp uge i32 [[RET]], 1 71; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 [[CMP_UGE_2]], i1 [[CMP_UGE_3]]) 72; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_UGE_4]], i1 true, i1 false) 73; IS__TUNIT____-NEXT: [[CMP_SGT_3:%.*]] = icmp sgt i32 [[RET]], 8 74; IS__TUNIT____-NEXT: [[CMP_SGT_4:%.*]] = icmp sgt i32 [[RET]], 1 75; IS__TUNIT____-NEXT: [[CMP_SGT_5:%.*]] = icmp sgt i32 [[RET]], 0 76; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 false, i1 [[CMP_SGT_3]]) 77; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_SGT_4]], i1 [[CMP_SGT_5]], i1 true) 78; IS__TUNIT____-NEXT: [[CMP_GTE_2:%.*]] = icmp sge i32 [[RET]], 9 79; IS__TUNIT____-NEXT: [[CMP_GTE_3:%.*]] = icmp sge i32 [[RET]], 8 80; IS__TUNIT____-NEXT: [[CMP_GTE_4:%.*]] = icmp sge i32 [[RET]], 1 81; IS__TUNIT____-NEXT: tail call void @use3(i1 false, i1 [[CMP_GTE_2]], i1 [[CMP_GTE_3]]) 82; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_GTE_4]], i1 true, i1 true) 83; IS__TUNIT____-NEXT: [[CMP_SLT_2:%.*]] = icmp slt i32 [[RET]], 9 84; IS__TUNIT____-NEXT: [[CMP_SLT_3:%.*]] = icmp slt i32 [[RET]], 8 85; IS__TUNIT____-NEXT: [[CMP_SLT_4:%.*]] = icmp slt i32 [[RET]], 1 86; IS__TUNIT____-NEXT: tail call void @use3(i1 true, i1 [[CMP_SLT_2]], i1 [[CMP_SLT_3]]) 87; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_SLT_4]], i1 false, i1 false) 88; IS__TUNIT____-NEXT: [[CMP_LTE_3:%.*]] = icmp sle i32 [[RET]], 8 89; IS__TUNIT____-NEXT: [[CMP_LTE_4:%.*]] = icmp sle i32 [[RET]], 1 90; IS__TUNIT____-NEXT: [[CMP_LTE_5:%.*]] = icmp sle i32 [[RET]], 0 91; IS__TUNIT____-NEXT: tail call void @use3(i1 true, i1 true, i1 [[CMP_LTE_3]]) 92; IS__TUNIT____-NEXT: tail call void @use3(i1 [[CMP_LTE_4]], i1 [[CMP_LTE_5]], i1 false) 93; IS__TUNIT____-NEXT: ret void 94; 95; IS__CGSCC____-LABEL: define {{[^@]+}}@test0-icmp-check 96; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 97; IS__CGSCC____-NEXT: [[RET:%.*]] = tail call i32 @test0(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 98; IS__CGSCC____-NEXT: [[CMP_EQ_1:%.*]] = icmp eq i32 [[RET]], 10 99; IS__CGSCC____-NEXT: [[CMP_EQ_2:%.*]] = icmp eq i32 [[RET]], 9 100; IS__CGSCC____-NEXT: [[CMP_EQ_3:%.*]] = icmp eq i32 [[RET]], 8 101; IS__CGSCC____-NEXT: [[CMP_EQ_4:%.*]] = icmp eq i32 [[RET]], 1 102; IS__CGSCC____-NEXT: [[CMP_EQ_5:%.*]] = icmp eq i32 [[RET]], 0 103; IS__CGSCC____-NEXT: [[CMP_EQ_6:%.*]] = icmp eq i32 [[RET]], -1 104; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_EQ_1]], i1 [[CMP_EQ_2]], i1 [[CMP_EQ_3]]) 105; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_EQ_4]], i1 [[CMP_EQ_5]], i1 [[CMP_EQ_6]]) 106; IS__CGSCC____-NEXT: [[CMP_NE_1:%.*]] = icmp ne i32 [[RET]], 10 107; IS__CGSCC____-NEXT: [[CMP_NE_2:%.*]] = icmp ne i32 [[RET]], 9 108; IS__CGSCC____-NEXT: [[CMP_NE_3:%.*]] = icmp ne i32 [[RET]], 8 109; IS__CGSCC____-NEXT: [[CMP_NE_4:%.*]] = icmp ne i32 [[RET]], 1 110; IS__CGSCC____-NEXT: [[CMP_NE_5:%.*]] = icmp ne i32 [[RET]], 0 111; IS__CGSCC____-NEXT: [[CMP_NE_6:%.*]] = icmp ne i32 [[RET]], -1 112; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_NE_1]], i1 [[CMP_NE_2]], i1 [[CMP_NE_3]]) 113; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_NE_4]], i1 [[CMP_NE_5]], i1 [[CMP_NE_6]]) 114; IS__CGSCC____-NEXT: [[CMP_UGT_1:%.*]] = icmp ugt i32 [[RET]], 10 115; IS__CGSCC____-NEXT: [[CMP_UGT_2:%.*]] = icmp ugt i32 [[RET]], 9 116; IS__CGSCC____-NEXT: [[CMP_UGT_3:%.*]] = icmp ugt i32 [[RET]], 8 117; IS__CGSCC____-NEXT: [[CMP_UGT_4:%.*]] = icmp ugt i32 [[RET]], 1 118; IS__CGSCC____-NEXT: [[CMP_UGT_5:%.*]] = icmp ugt i32 [[RET]], 0 119; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGT_1]], i1 [[CMP_UGT_2]], i1 [[CMP_UGT_3]]) 120; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGT_4]], i1 [[CMP_UGT_5]], i1 false) 121; IS__CGSCC____-NEXT: [[CMP_UGE_1:%.*]] = icmp uge i32 [[RET]], 10 122; IS__CGSCC____-NEXT: [[CMP_UGE_2:%.*]] = icmp uge i32 [[RET]], 9 123; IS__CGSCC____-NEXT: [[CMP_UGE_3:%.*]] = icmp uge i32 [[RET]], 8 124; IS__CGSCC____-NEXT: [[CMP_UGE_4:%.*]] = icmp uge i32 [[RET]], 1 125; IS__CGSCC____-NEXT: [[CMP_UGE_6:%.*]] = icmp uge i32 [[RET]], -1 126; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGE_1]], i1 [[CMP_UGE_2]], i1 [[CMP_UGE_3]]) 127; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_UGE_4]], i1 true, i1 [[CMP_UGE_6]]) 128; IS__CGSCC____-NEXT: [[CMP_SGT_1:%.*]] = icmp sgt i32 [[RET]], 10 129; IS__CGSCC____-NEXT: [[CMP_SGT_2:%.*]] = icmp sgt i32 [[RET]], 9 130; IS__CGSCC____-NEXT: [[CMP_SGT_3:%.*]] = icmp sgt i32 [[RET]], 8 131; IS__CGSCC____-NEXT: [[CMP_SGT_4:%.*]] = icmp sgt i32 [[RET]], 1 132; IS__CGSCC____-NEXT: [[CMP_SGT_5:%.*]] = icmp sgt i32 [[RET]], 0 133; IS__CGSCC____-NEXT: [[CMP_SGT_6:%.*]] = icmp sgt i32 [[RET]], -1 134; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SGT_1]], i1 [[CMP_SGT_2]], i1 [[CMP_SGT_3]]) 135; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SGT_4]], i1 [[CMP_SGT_5]], i1 [[CMP_SGT_6]]) 136; IS__CGSCC____-NEXT: [[CMP_GTE_1:%.*]] = icmp sge i32 [[RET]], 10 137; IS__CGSCC____-NEXT: [[CMP_GTE_2:%.*]] = icmp sge i32 [[RET]], 9 138; IS__CGSCC____-NEXT: [[CMP_GTE_3:%.*]] = icmp sge i32 [[RET]], 8 139; IS__CGSCC____-NEXT: [[CMP_GTE_4:%.*]] = icmp sge i32 [[RET]], 1 140; IS__CGSCC____-NEXT: [[CMP_GTE_5:%.*]] = icmp sge i32 [[RET]], 0 141; IS__CGSCC____-NEXT: [[CMP_GTE_6:%.*]] = icmp sge i32 [[RET]], -1 142; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_GTE_1]], i1 [[CMP_GTE_2]], i1 [[CMP_GTE_3]]) 143; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_GTE_4]], i1 [[CMP_GTE_5]], i1 [[CMP_GTE_6]]) 144; IS__CGSCC____-NEXT: [[CMP_SLT_1:%.*]] = icmp slt i32 [[RET]], 10 145; IS__CGSCC____-NEXT: [[CMP_SLT_2:%.*]] = icmp slt i32 [[RET]], 9 146; IS__CGSCC____-NEXT: [[CMP_SLT_3:%.*]] = icmp slt i32 [[RET]], 8 147; IS__CGSCC____-NEXT: [[CMP_SLT_4:%.*]] = icmp slt i32 [[RET]], 1 148; IS__CGSCC____-NEXT: [[CMP_SLT_5:%.*]] = icmp slt i32 [[RET]], 0 149; IS__CGSCC____-NEXT: [[CMP_SLT_6:%.*]] = icmp slt i32 [[RET]], -1 150; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SLT_1]], i1 [[CMP_SLT_2]], i1 [[CMP_SLT_3]]) 151; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_SLT_4]], i1 [[CMP_SLT_5]], i1 [[CMP_SLT_6]]) 152; IS__CGSCC____-NEXT: [[CMP_LTE_1:%.*]] = icmp sle i32 [[RET]], 10 153; IS__CGSCC____-NEXT: [[CMP_LTE_2:%.*]] = icmp sle i32 [[RET]], 9 154; IS__CGSCC____-NEXT: [[CMP_LTE_3:%.*]] = icmp sle i32 [[RET]], 8 155; IS__CGSCC____-NEXT: [[CMP_LTE_4:%.*]] = icmp sle i32 [[RET]], 1 156; IS__CGSCC____-NEXT: [[CMP_LTE_5:%.*]] = icmp sle i32 [[RET]], 0 157; IS__CGSCC____-NEXT: [[CMP_LTE_6:%.*]] = icmp sle i32 [[RET]], -1 158; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_LTE_1]], i1 [[CMP_LTE_2]], i1 [[CMP_LTE_3]]) 159; IS__CGSCC____-NEXT: tail call void @use3(i1 [[CMP_LTE_4]], i1 [[CMP_LTE_5]], i1 [[CMP_LTE_6]]) 160; IS__CGSCC____-NEXT: ret void 161; 162 %ret = tail call i32 @test0(i32 *%p) 163 164 ; ret = [0, 10), eq 165 %cmp-eq-1 = icmp eq i32 %ret, 10 166 %cmp-eq-2 = icmp eq i32 %ret, 9 167 %cmp-eq-3 = icmp eq i32 %ret, 8 168 %cmp-eq-4 = icmp eq i32 %ret, 1 169 %cmp-eq-5 = icmp eq i32 %ret, 0 170 %cmp-eq-6 = icmp eq i32 %ret, -1 171 tail call void @use3(i1 %cmp-eq-1, i1 %cmp-eq-2, i1 %cmp-eq-3) 172 tail call void @use3(i1 %cmp-eq-4, i1 %cmp-eq-5, i1 %cmp-eq-6) 173 174 ; ret = [0, 10), ne 175 %cmp-ne-1 = icmp ne i32 %ret, 10 176 %cmp-ne-2 = icmp ne i32 %ret, 9 177 %cmp-ne-3 = icmp ne i32 %ret, 8 178 %cmp-ne-4 = icmp ne i32 %ret, 1 179 %cmp-ne-5 = icmp ne i32 %ret, 0 180 %cmp-ne-6 = icmp ne i32 %ret, -1 181 tail call void @use3(i1 %cmp-ne-1, i1 %cmp-ne-2, i1 %cmp-ne-3) 182 tail call void @use3(i1 %cmp-ne-4, i1 %cmp-ne-5, i1 %cmp-ne-6) 183 184 ; ret = [0, 10), ugt 185 %cmp-ugt-1 = icmp ugt i32 %ret, 10 186 %cmp-ugt-2 = icmp ugt i32 %ret, 9 187 %cmp-ugt-3 = icmp ugt i32 %ret, 8 188 %cmp-ugt-4 = icmp ugt i32 %ret, 1 189 %cmp-ugt-5 = icmp ugt i32 %ret, 0 190 %cmp-ugt-6 = icmp ugt i32 %ret, -1 191 tail call void @use3(i1 %cmp-ugt-1, i1 %cmp-ugt-2, i1 %cmp-ugt-3) 192 tail call void @use3(i1 %cmp-ugt-4, i1 %cmp-ugt-5, i1 %cmp-ugt-6) 193 194 ; ret = [0, 10), uge 195 %cmp-uge-1 = icmp uge i32 %ret, 10 196 %cmp-uge-2 = icmp uge i32 %ret, 9 197 %cmp-uge-3 = icmp uge i32 %ret, 8 198 %cmp-uge-4 = icmp uge i32 %ret, 1 199 %cmp-uge-5 = icmp uge i32 %ret, 0 200 %cmp-uge-6 = icmp uge i32 %ret, -1 201 tail call void @use3(i1 %cmp-uge-1, i1 %cmp-uge-2, i1 %cmp-uge-3) 202 tail call void @use3(i1 %cmp-uge-4, i1 %cmp-uge-5, i1 %cmp-uge-6) 203 204 ; ret = [0, 10), sgt 205 %cmp-sgt-1 = icmp sgt i32 %ret, 10 206 %cmp-sgt-2 = icmp sgt i32 %ret, 9 207 %cmp-sgt-3 = icmp sgt i32 %ret, 8 208 %cmp-sgt-4 = icmp sgt i32 %ret, 1 209 %cmp-sgt-5 = icmp sgt i32 %ret, 0 210 %cmp-sgt-6 = icmp sgt i32 %ret, -1 211 tail call void @use3(i1 %cmp-sgt-1, i1 %cmp-sgt-2, i1 %cmp-sgt-3) 212 tail call void @use3(i1 %cmp-sgt-4, i1 %cmp-sgt-5, i1 %cmp-sgt-6) 213 214 ; ret = [0, 10), sge 215 %cmp-gte-1 = icmp sge i32 %ret, 10 216 %cmp-gte-2 = icmp sge i32 %ret, 9 217 %cmp-gte-3 = icmp sge i32 %ret, 8 218 %cmp-gte-4 = icmp sge i32 %ret, 1 219 %cmp-gte-5 = icmp sge i32 %ret, 0 220 %cmp-gte-6 = icmp sge i32 %ret, -1 221 tail call void @use3(i1 %cmp-gte-1, i1 %cmp-gte-2, i1 %cmp-gte-3) 222 tail call void @use3(i1 %cmp-gte-4, i1 %cmp-gte-5, i1 %cmp-gte-6) 223 224 ; ret = [0, 10), slt 225 %cmp-slt-1 = icmp slt i32 %ret, 10 226 %cmp-slt-2 = icmp slt i32 %ret, 9 227 %cmp-slt-3 = icmp slt i32 %ret, 8 228 %cmp-slt-4 = icmp slt i32 %ret, 1 229 %cmp-slt-5 = icmp slt i32 %ret, 0 230 %cmp-slt-6 = icmp slt i32 %ret, -1 231 tail call void @use3(i1 %cmp-slt-1, i1 %cmp-slt-2, i1 %cmp-slt-3) 232 tail call void @use3(i1 %cmp-slt-4, i1 %cmp-slt-5, i1 %cmp-slt-6) 233 234 ; ret = [0, 10), sle 235 %cmp-lte-1 = icmp sle i32 %ret, 10 236 %cmp-lte-2 = icmp sle i32 %ret, 9 237 %cmp-lte-3 = icmp sle i32 %ret, 8 238 %cmp-lte-4 = icmp sle i32 %ret, 1 239 %cmp-lte-5 = icmp sle i32 %ret, 0 240 %cmp-lte-6 = icmp sle i32 %ret, -1 241 tail call void @use3(i1 %cmp-lte-1, i1 %cmp-lte-2, i1 %cmp-lte-3) 242 tail call void @use3(i1 %cmp-lte-4, i1 %cmp-lte-5, i1 %cmp-lte-6) 243 244 ret void 245} 246define i32 @test1(i32* %p) { 247; CHECK-LABEL: define {{[^@]+}}@test1 248; CHECK-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 249; CHECK-NEXT: [[LOAD_10_100:%.*]] = load i32, i32* [[P]], align 4, !range !1 250; CHECK-NEXT: [[ADD_10_THEN_20_110:%.*]] = add i32 [[LOAD_10_100]], 10 251; CHECK-NEXT: [[MUL_10_THEN_200_1091:%.*]] = mul i32 [[ADD_10_THEN_20_110]], 10 252; CHECK-NEXT: ret i32 [[MUL_10_THEN_200_1091]] 253; 254 %load-10-100 = load i32, i32* %p, !range !1 255 %add-10-then-20-110 = add i32 %load-10-100, 10 256 %mul-10-then-200-1091 = mul i32 %add-10-then-20-110, 10 257 ret i32 %mul-10-then-200-1091 258} 259 260define i1 @test1-check(i32* %p) { 261; 262; IS__TUNIT____-LABEL: define {{[^@]+}}@test1-check 263; IS__TUNIT____-SAME: (i32* nocapture nofree readonly align 4 [[P:%.*]]) 264; IS__TUNIT____-NEXT: [[RES:%.*]] = tail call i32 @test1(i32* nocapture nofree readonly align 4 [[P]]) #4, !range !2 265; IS__TUNIT____-NEXT: [[CMP:%.*]] = icmp eq i32 [[RES]], 500 266; IS__TUNIT____-NEXT: ret i1 [[CMP]] 267; 268; IS__CGSCC____-LABEL: define {{[^@]+}}@test1-check 269; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 270; IS__CGSCC____-NEXT: [[RES:%.*]] = tail call i32 @test1(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 271; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp eq i32 [[RES]], 500 272; IS__CGSCC____-NEXT: ret i1 [[CMP]] 273; 274 %res = tail call i32 @test1(i32* %p) 275 %cmp = icmp eq i32 %res, 500 276 ret i1 %cmp 277} 278 279; TEST2 280; int test2(int *p) { return *p == 0 ? 4 : 3; } 281; int test2_check(int *p) { 282; int call = test2(p); 283; if (call == 5) { 284; // dead block 285; return 2; 286; } else { 287; return 3; 288; } 289; } 290 291define i32 @test2(i32* %p) { 292; CHECK-LABEL: define {{[^@]+}}@test2 293; CHECK-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 294; CHECK-NEXT: entry: 295; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P]], align 4 296; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP0]], 0 297; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 4, i32 3 298; CHECK-NEXT: ret i32 [[COND]] 299; 300entry: 301 %0 = load i32, i32* %p, align 4 302 %tobool = icmp eq i32 %0, 0 303 %cond = select i1 %tobool, i32 4, i32 3 304 ret i32 %cond 305} 306 307define i32 @test2_check(i32* %p) { 308; IS__TUNIT____-LABEL: define {{[^@]+}}@test2_check 309; IS__TUNIT____-SAME: (i32* nocapture nofree readnone align 4 [[P:%.*]]) 310; IS__TUNIT____-NEXT: entry: 311; IS__TUNIT____-NEXT: br label [[IF_THEN:%.*]] 312; IS__TUNIT____: if.then: 313; IS__TUNIT____-NEXT: br label [[RETURN:%.*]] 314; IS__TUNIT____: if.end: 315; IS__TUNIT____-NEXT: unreachable 316; IS__TUNIT____: return: 317; IS__TUNIT____-NEXT: ret i32 2 318; 319; IS__CGSCC____-LABEL: define {{[^@]+}}@test2_check 320; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P:%.*]]) 321; IS__CGSCC____-NEXT: entry: 322; IS__CGSCC____-NEXT: [[CALL:%.*]] = tail call i32 @test2(i32* nocapture nofree nonnull readonly align 4 dereferenceable(4) [[P]]) 323; IS__CGSCC____-NEXT: [[CMP:%.*]] = icmp slt i32 [[CALL]], 5 324; IS__CGSCC____-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 325; IS__CGSCC____: if.then: 326; IS__CGSCC____-NEXT: br label [[RETURN:%.*]] 327; IS__CGSCC____: if.end: 328; IS__CGSCC____-NEXT: br label [[RETURN]] 329; IS__CGSCC____: return: 330; IS__CGSCC____-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 2, [[IF_THEN]] ], [ 3, [[IF_END]] ] 331; IS__CGSCC____-NEXT: ret i32 [[RETVAL_0]] 332; 333entry: 334 %call = tail call i32 @test2(i32* %p) 335 %cmp = icmp slt i32 %call, 5 336 br i1 %cmp, label %if.then, label %if.end 337 338if.then: ; preds = %entry 339 br label %return 340 341if.end: ; preds = %entry 342 br label %return 343 344return: ; preds = %if.end, %if.then 345 %retval.0 = phi i32 [ 2, %if.then ], [ 3, %if.end ] 346 ret i32 %retval.0 347} 348 349; TEST 3 SECV test 350 351; void unkown(); 352; int r1(unsigned int u){ 353; int sum = 0; 354; for(int i = 0; i<100;i++){ 355; sum += i; 356; } 357; // sum = 50 * 49 / 2 358; if(sum > 10000){ 359; // dead block 360; return 20; 361; }else { 362; return 10; 363; } 364; } 365; void f1(int u){ 366; if(r1(u) > 15){ 367; // deadblock 368; unkown(); 369; }else { 370; return; 371; } 372; } 373 374declare dso_local void @unkown() 375 376define internal i32 @r1(i32) local_unnamed_addr { 377; IS________OPM-LABEL: define {{[^@]+}}@r1() local_unnamed_addr 378; IS________OPM-NEXT: br label [[TMP4:%.*]] 379; IS________OPM: 1: 380; IS________OPM-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP7:%.*]], 10000 381; IS________OPM-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[F:%.*]] 382; IS________OPM: 3: 383; IS________OPM-NEXT: ret i32 20 384; IS________OPM: f: 385; IS________OPM-NEXT: ret i32 10 386; IS________OPM: 4: 387; IS________OPM-NEXT: [[TMP5:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP8:%.*]], [[TMP4]] ] 388; IS________OPM-NEXT: [[TMP6:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[TMP7]], [[TMP4]] ] 389; IS________OPM-NEXT: [[TMP7]] = add nuw nsw i32 [[TMP5]], [[TMP6]] 390; IS________OPM-NEXT: [[TMP8]] = add nuw nsw i32 [[TMP5]], 1 391; IS________OPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 100 392; IS________OPM-NEXT: br i1 [[TMP9]], label [[TMP1:%.*]], label [[TMP4]] 393; 394; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@r1() local_unnamed_addr 395; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] 396; IS__CGSCC_NPM: 1: 397; IS__CGSCC_NPM-NEXT: br label [[F:%.*]] 398; IS__CGSCC_NPM: 2: 399; IS__CGSCC_NPM-NEXT: unreachable 400; IS__CGSCC_NPM: f: 401; IS__CGSCC_NPM-NEXT: ret i32 10 402; IS__CGSCC_NPM: 3: 403; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[TMP3]] ] 404; IS__CGSCC_NPM-NEXT: [[TMP5:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[TMP6:%.*]], [[TMP3]] ] 405; IS__CGSCC_NPM-NEXT: [[TMP6]] = add nuw nsw i32 [[TMP4]], [[TMP5]] 406; IS__CGSCC_NPM-NEXT: [[TMP7]] = add nuw nsw i32 [[TMP4]], 1 407; IS__CGSCC_NPM-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 100 408; IS__CGSCC_NPM-NEXT: br i1 [[TMP8]], label [[TMP1:%.*]], label [[TMP3]] 409; 410 br label %5 411 4122: ; preds = %5 413 %3 = icmp sgt i32 %8, 10000 414 br i1 %3, label %4, label %f 4154: 416 ret i32 20 417f: 418 ret i32 10 4195: ; preds = %5, %1 420 %6 = phi i32 [ 0, %1 ], [ %9, %5 ] 421 %7 = phi i32 [ 0, %1 ], [ %8, %5 ] 422 %8 = add nuw nsw i32 %6, %7 423 %9 = add nuw nsw i32 %6, 1 424 %10 = icmp eq i32 %9, 100 425 br i1 %10, label %2, label %5 426} 427 428define void @f1(i32){ 429; IS________OPM-LABEL: define {{[^@]+}}@f1 430; IS________OPM-SAME: (i32 [[TMP0:%.*]]) 431; IS________OPM-NEXT: [[TMP2:%.*]] = tail call i32 @r1() 432; IS________OPM-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], 15 433; IS________OPM-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP5:%.*]] 434; IS________OPM: 4: 435; IS________OPM-NEXT: tail call void @unkown() 436; IS________OPM-NEXT: br label [[TMP5]] 437; IS________OPM: 5: 438; IS________OPM-NEXT: ret void 439; 440; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@f1 441; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]]) 442; IS__TUNIT_NPM-NEXT: br label [[TMP3:%.*]] 443; IS__TUNIT_NPM: 2: 444; IS__TUNIT_NPM-NEXT: tail call void @unkown() 445; IS__TUNIT_NPM-NEXT: br label [[TMP3]] 446; IS__TUNIT_NPM: 3: 447; IS__TUNIT_NPM-NEXT: ret void 448; 449; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@f1 450; IS__CGSCC_NPM-SAME: (i32 [[TMP0:%.*]]) 451; IS__CGSCC_NPM-NEXT: br label [[TMP3:%.*]] 452; IS__CGSCC_NPM: 2: 453; IS__CGSCC_NPM-NEXT: unreachable 454; IS__CGSCC_NPM: 3: 455; IS__CGSCC_NPM-NEXT: ret void 456; 457 %2 = tail call i32 @r1(i32 %0) 458 %3 = icmp sgt i32 %2, 15 459 br i1 %3, label %4, label %5 460 4614: ; preds = %1 462 tail call void @unkown() 463 br label %5 464 4655: ; preds = %1, %4 466 ret void 467} 468 469; TEST4 LVI test 470 471; f1 472; int test4-f1(int u){ 473; if(u>=0) { 474; return u; 475; }else{ 476; return 0; 477; } 478; } 479define dso_local i32 @test4-f1(i32 %u) { 480; CHECK-LABEL: define {{[^@]+}}@test4-f1 481; CHECK-SAME: (i32 [[U:%.*]]) 482; CHECK-NEXT: entry: 483; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[U]], -1 484; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[RETURN:%.*]] 485; CHECK: if.then: 486; CHECK-NEXT: br label [[RETURN]] 487; CHECK: return: 488; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[U]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ] 489; CHECK-NEXT: ret i32 [[RETVAL_0]] 490; 491; FIXME: RETVAL_0 >= 0 492entry: 493 %cmp = icmp sgt i32 %u, -1 494 br i1 %cmp, label %if.then, label %return 495 496if.then: ; preds = %entry 497 br label %return 498 499return: ; preds = %entry, %if.then 500 %retval.0 = phi i32 [ %u, %if.then ], [ 0, %entry ] 501 ret i32 %retval.0 502} 503 504 505define dso_local i32 @test4-g1(i32 %u) { 506; CHECK-LABEL: define {{[^@]+}}@test4-g1 507; CHECK-SAME: (i32 [[U:%.*]]) 508; CHECK-NEXT: entry: 509; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @test4-f1(i32 [[U]]) 510; CHECK-NEXT: ret i32 [[CALL]] 511; 512; FIXME: %call should have range [0, inf] 513 514entry: 515 %call = tail call i32 @test4-f1(i32 %u) 516 ret i32 %call 517} 518 519; f2 520; int test4-f1(int u){ 521; if(u>-1) { 522; return u+1; 523; }else{ 524; return 1; 525; } 526; } 527define dso_local i32 @test4-f2(i32 %u) { 528; CHECK-LABEL: define {{[^@]+}}@test4-f2 529; CHECK-SAME: (i32 [[U:%.*]]) 530; CHECK-NEXT: entry: 531; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[U]], -1 532; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] 533; CHECK: if.then: 534; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[U]], 1 535; CHECK-NEXT: br label [[RETURN:%.*]] 536; CHECK: if.else: 537; CHECK-NEXT: br label [[RETURN]] 538; CHECK: return: 539; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[ADD]], [[IF_THEN]] ], [ 1, [[IF_ELSE]] ] 540; CHECK-NEXT: ret i32 [[RETVAL_0]] 541; 542entry: 543 %cmp = icmp sgt i32 %u, -1 544 br i1 %cmp, label %if.then, label %if.else 545 546if.then: ; preds = %entry 547 %add = add nuw nsw i32 %u, 1 548 br label %return 549 550if.else: ; preds = %entry 551 br label %return 552 553return: ; preds = %if.else, %if.then 554 %retval.0 = phi i32 [ %add, %if.then ], [ 1, %if.else ] 555 ret i32 %retval.0 556} 557 558 559define dso_local i32 @test4-g2(i32 %u) { 560; NOT_TUNIT_NPM-LABEL: define {{[^@]+}}@test4-g2 561; NOT_TUNIT_NPM-SAME: (i32 [[U:%.*]]) 562; NOT_TUNIT_NPM-NEXT: entry: 563; NOT_TUNIT_NPM-NEXT: [[CALL:%.*]] = tail call i32 @test4-f2(i32 [[U]]) 564; NOT_TUNIT_NPM-NEXT: ret i32 [[CALL]] 565; 566; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@test4-g2 567; IS__TUNIT_NPM-SAME: (i32 [[U:%.*]]) 568; IS__TUNIT_NPM-NEXT: entry: 569; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = tail call i32 @test4-f2(i32 [[U]]) #2, !range !3 570; IS__TUNIT_NPM-NEXT: ret i32 [[CALL]] 571; 572entry: 573 %call = tail call i32 @test4-f2(i32 %u) 574 ret i32 %call 575} 576 577define dso_local i32 @test-5() { 578; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@test-5() 579; IS__TUNIT_OPM-NEXT: entry: 580; IS__TUNIT_OPM-NEXT: [[CALL:%.*]] = call i32 @rec(i32 0), !range !3 581; IS__TUNIT_OPM-NEXT: ret i32 [[CALL]] 582; 583; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@test-5() 584; IS__TUNIT_NPM-NEXT: entry: 585; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = call i32 @rec(i32 0), !range !4 586; IS__TUNIT_NPM-NEXT: ret i32 [[CALL]] 587; 588; IS__CGSCC____-LABEL: define {{[^@]+}}@test-5() 589; IS__CGSCC____-NEXT: entry: 590; IS__CGSCC____-NEXT: [[CALL:%.*]] = call i32 @rec(i32 0) 591; IS__CGSCC____-NEXT: ret i32 [[CALL]] 592; 593entry: 594 %call = call i32 @rec(i32 0) 595 ret i32 %call 596} 597define internal i32 @rec(i32 %depth) { 598; CHECK-LABEL: define {{[^@]+}}@rec 599; CHECK-SAME: (i32 [[DEPTH:%.*]]) 600; CHECK-NEXT: entry: 601; CHECK-NEXT: [[CALL:%.*]] = call i32 @foo(i32 [[DEPTH]]) 602; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[CALL]], 0 603; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] 604; CHECK: if.then: 605; CHECK-NEXT: br label [[RETURN:%.*]] 606; CHECK: if.end: 607; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[DEPTH]], 10 608; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN1:%.*]], label [[IF_END3:%.*]] 609; CHECK: if.then1: 610; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[DEPTH]], 1 611; CHECK-NEXT: [[CALL2:%.*]] = call i32 @rec(i32 [[ADD]]) 612; CHECK-NEXT: br label [[IF_END3]] 613; CHECK: if.end3: 614; CHECK-NEXT: br label [[RETURN]] 615; CHECK: return: 616; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 0, [[IF_THEN]] ], [ 1, [[IF_END3]] ] 617; CHECK-NEXT: ret i32 [[RETVAL_0]] 618; 619entry: 620 %call = call i32 @foo(i32 %depth) 621 %tobool = icmp ne i32 %call, 0 622 br i1 %tobool, label %if.then, label %if.end 623 624if.then: ; preds = %entry 625 br label %return 626 627if.end: ; preds = %entry 628 %cmp = icmp slt i32 %depth, 10 629 br i1 %cmp, label %if.then1, label %if.end3 630 631if.then1: ; preds = %if.end 632 %add = add nsw i32 %depth, 1 633 %call2 = call i32 @rec(i32 %add) 634 br label %if.end3 635 636if.end3: ; preds = %if.then1, %if.end 637 br label %return 638 639return: ; preds = %if.end3, %if.then 640 %retval.0 = phi i32 [ 0, %if.then ], [ 1, %if.end3 ] 641 ret i32 %retval.0 642} 643declare dso_local i32 @foo(i32) 644 645 646; Examples taken from https://llvm.discourse.group/t/impossible-condition-optimization/461/1 647; 648; The important part is that we return a constant (false) 649; 650; { 651 652; FIXME: All but the return is not needed anymore 653define dso_local zeroext i1 @phi(i32 %arg) { 654; CHECK-LABEL: define {{[^@]+}}@phi 655; CHECK-SAME: (i32 [[ARG:%.*]]) 656; CHECK-NEXT: bb: 657; CHECK-NEXT: [[TMP:%.*]] = icmp sgt i32 [[ARG]], 5 658; CHECK-NEXT: br i1 [[TMP]], label [[BB1:%.*]], label [[BB2:%.*]] 659; CHECK: bb1: 660; CHECK-NEXT: br label [[BB3:%.*]] 661; CHECK: bb2: 662; CHECK-NEXT: br label [[BB3]] 663; CHECK: bb3: 664; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[ARG]], 10 665; CHECK-NEXT: br i1 [[TMP4]], label [[BB5:%.*]], label [[BB7:%.*]] 666; CHECK: bb5: 667; CHECK-NEXT: br label [[BB9:%.*]] 668; CHECK: bb7: 669; CHECK-NEXT: br label [[BB9]] 670; CHECK: bb9: 671; CHECK-NEXT: br label [[BB12:%.*]] 672; CHECK: bb11: 673; CHECK-NEXT: unreachable 674; CHECK: bb12: 675; CHECK-NEXT: br label [[BB13:%.*]] 676; CHECK: bb13: 677; CHECK-NEXT: ret i1 false 678; 679bb: 680 %tmp = icmp sgt i32 %arg, 5 681 br i1 %tmp, label %bb1, label %bb2 682 683bb1: ; preds = %bb 684 br label %bb3 685 686bb2: ; preds = %bb 687 br label %bb3 688 689bb3: ; preds = %bb2, %bb1 690 %.02 = phi i32 [ 1, %bb1 ], [ 2, %bb2 ] 691 %tmp4 = icmp sgt i32 %arg, 10 692 br i1 %tmp4, label %bb5, label %bb7 693 694bb5: ; preds = %bb3 695 %tmp6 = add nsw i32 %.02, 1 696 br label %bb9 697 698bb7: ; preds = %bb3 699 %tmp8 = add nsw i32 %.02, 2 700 br label %bb9 701 702bb9: ; preds = %bb7, %bb5 703 %.01 = phi i32 [ %tmp6, %bb5 ], [ %tmp8, %bb7 ] 704 %tmp10 = icmp eq i32 %.01, 5 705 br i1 %tmp10, label %bb11, label %bb12 706 707bb11: ; preds = %bb9 708 br label %bb13 709 710bb12: ; preds = %bb9 711 br label %bb13 712 713bb13: ; preds = %bb12, %bb11 714 %.0 = phi i1 [ true, %bb11 ], [ false, %bb12 ] 715 ret i1 %.0 716} 717 718define dso_local i1 @select(i32 %a) local_unnamed_addr #0 { 719; CHECK-LABEL: define {{[^@]+}}@select 720; CHECK-SAME: (i32 [[A:%.*]]) local_unnamed_addr 721; CHECK-NEXT: entry: 722; CHECK-NEXT: ret i1 false 723; 724entry: 725 %cmp = icmp sgt i32 %a, 5 726 %. = select i1 %cmp, i32 1, i32 2 727 %cmp1 = icmp sgt i32 %a, 10 728 %y.0.v = select i1 %cmp1, i32 1, i32 2 729 %y.0 = add nuw nsw i32 %., %y.0.v 730 %cmp6 = icmp eq i32 %y.0, 5 731 ret i1 %cmp6 732} 733 734define dso_local i32 @select_zext(i32 %a) local_unnamed_addr #0 { 735; CHECK-LABEL: define {{[^@]+}}@select_zext 736; CHECK-SAME: (i32 [[A:%.*]]) local_unnamed_addr 737; CHECK-NEXT: entry: 738; CHECK-NEXT: ret i32 0 739; 740entry: 741 %cmp = icmp sgt i32 %a, 5 742 %. = select i1 %cmp, i32 1, i32 2 743 %cmp1 = icmp sgt i32 %a, 10 744 %y.0.v = select i1 %cmp1, i32 1, i32 2 745 %y.0 = add nuw nsw i32 %., %y.0.v 746 %cmp6 = icmp eq i32 %y.0, 5 747 %.13 = zext i1 %cmp6 to i32 748 ret i32 %.13 749} 750 751; FIXME: We do not look through the ptr casts here. 752define dso_local i64 @select_int2ptr_bitcast_ptr2int(i32 %a) local_unnamed_addr #0 { 753; CHECK-LABEL: define {{[^@]+}}@select_int2ptr_bitcast_ptr2int 754; CHECK-SAME: (i32 [[A:%.*]]) local_unnamed_addr 755; CHECK-NEXT: entry: 756; CHECK-NEXT: [[I2P:%.*]] = inttoptr i1 false to i1* 757; CHECK-NEXT: [[BC:%.*]] = bitcast i1* [[I2P]] to i32* 758; CHECK-NEXT: [[P2I:%.*]] = ptrtoint i32* [[BC]] to i64 759; CHECK-NEXT: ret i64 [[P2I]] 760; 761entry: 762 %cmp = icmp sgt i32 %a, 5 763 %. = select i1 %cmp, i32 1, i32 2 764 %cmp1 = icmp sgt i32 %a, 10 765 %y.0.v = select i1 %cmp1, i32 1, i32 2 766 %y.0 = add nuw nsw i32 %., %y.0.v 767 %cmp6 = icmp eq i32 %y.0, 5 768 %i2p = inttoptr i1 %cmp6 to i1* 769 %bc = bitcast i1* %i2p to i32* 770 %p2i = ptrtoint i32* %bc to i64 771 ret i64 %p2i 772} 773 774; } 775 776define i1 @f_fcmp(float %a, float %b) { 777; CHECK-LABEL: define {{[^@]+}}@f_fcmp 778; CHECK-SAME: (float [[A:%.*]], float [[B:%.*]]) 779; CHECK-NEXT: [[R:%.*]] = fcmp uge float [[A]], [[B]] 780; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 781; CHECK-NEXT: ret i1 [[S]] 782; 783 %r = fcmp uge float %a, %b 784 %s = select i1 %r, i1 %r, i1 0 785 ret i1 %s 786} 787define i1 @d_fcmp(double %a, double %b) { 788; CHECK-LABEL: define {{[^@]+}}@d_fcmp 789; CHECK-SAME: (double [[A:%.*]], double [[B:%.*]]) 790; CHECK-NEXT: [[R:%.*]] = fcmp oeq double [[A]], [[B]] 791; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 792; CHECK-NEXT: ret i1 [[S]] 793; 794 %r = fcmp oeq double %a, %b 795 %s = select i1 %r, i1 %r, i1 0 796 ret i1 %s 797} 798define i1 @dp_icmp(double* %a, double* %b) { 799; CHECK-LABEL: define {{[^@]+}}@dp_icmp 800; CHECK-SAME: (double* nofree readnone [[A:%.*]], double* nofree readnone [[B:%.*]]) 801; CHECK-NEXT: [[R:%.*]] = icmp sge double* [[A]], [[B]] 802; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 803; CHECK-NEXT: ret i1 [[S]] 804; 805 %r = icmp sge double* %a, %b 806 %s = select i1 %r, i1 %r, i1 0 807 ret i1 %s 808} 809define i1 @ip_icmp(i8* %a, i8* %b) { 810; CHECK-LABEL: define {{[^@]+}}@ip_icmp 811; CHECK-SAME: (i8* nofree readnone [[A:%.*]], i8* nofree readnone [[B:%.*]]) 812; CHECK-NEXT: [[R:%.*]] = icmp ult i8* [[A]], [[B]] 813; CHECK-NEXT: [[S:%.*]] = select i1 [[R]], i1 [[R]], i1 false 814; CHECK-NEXT: ret i1 [[S]] 815; 816 %r = icmp ult i8* %a, %b 817 %s = select i1 %r, i1 %r, i1 0 818 ret i1 %s 819} 820define i1 @fcmp_caller(float %fa, float %fb, double %da, double %db, double* %dpa, double* %dpb, i8* %ipa, i8* %ipb) { 821; CHECK-LABEL: define {{[^@]+}}@fcmp_caller 822; CHECK-SAME: (float [[FA:%.*]], float [[FB:%.*]], double [[DA:%.*]], double [[DB:%.*]], double* nofree readnone [[DPA:%.*]], double* nofree readnone [[DPB:%.*]], i8* nofree readnone [[IPA:%.*]], i8* nofree readnone [[IPB:%.*]]) 823; CHECK-NEXT: [[R1:%.*]] = call i1 @f_fcmp(float [[FA]], float [[FB]]) 824; CHECK-NEXT: [[R2:%.*]] = call i1 @d_fcmp(double [[DA]], double [[DB]]) 825; CHECK-NEXT: [[R3:%.*]] = call i1 @dp_icmp(double* noalias nofree readnone [[DPA]], double* noalias nofree readnone [[DPB]]) 826; CHECK-NEXT: [[R4:%.*]] = call i1 @ip_icmp(i8* noalias nofree readnone [[IPA]], i8* noalias nofree readnone [[IPB]]) 827; CHECK-NEXT: [[O1:%.*]] = or i1 [[R1]], [[R2]] 828; CHECK-NEXT: [[O2:%.*]] = or i1 [[R3]], [[R4]] 829; CHECK-NEXT: [[O3:%.*]] = or i1 [[O1]], [[O2]] 830; CHECK-NEXT: ret i1 [[O3]] 831; 832 %r1 = call i1 @f_fcmp(float %fa, float %fb) 833 %r2 = call i1 @d_fcmp(double %da, double %db) 834 %r3 = call i1 @dp_icmp(double* %dpa, double* %dpb) 835 %r4 = call i1 @ip_icmp(i8* %ipa, i8* %ipb) 836 %o1 = or i1 %r1, %r2 837 %o2 = or i1 %r3, %r4 838 %o3 = or i1 %o1, %o2 839 ret i1 %o3 840} 841 842define i8 @ret_two() { 843; CHECK-LABEL: define {{[^@]+}}@ret_two() 844; CHECK-NEXT: ret i8 2 845; 846 ret i8 2 847} 848define i8 @ret_undef() { 849; CHECK-LABEL: define {{[^@]+}}@ret_undef() 850; CHECK-NEXT: ret i8 undef 851; 852 ret i8 undef 853} 854 855; Verify we collapse undef to a value and return something non-undef here. 856define i8 @undef_collapse_1() { 857; CHECK-LABEL: define {{[^@]+}}@undef_collapse_1() 858; CHECK-NEXT: ret i8 0 859; 860 %c = call i8 @ret_undef() 861 %s = shl i8 %c, 2 862 ret i8 %s 863} 864 865; Verify we collapse undef to a value and return something non-undef here. 866define i8 @undef_collapse_2() { 867; CHECK-LABEL: define {{[^@]+}}@undef_collapse_2() 868; CHECK-NEXT: ret i8 0 869; 870 %c = call i8 @ret_two() 871 %s = shl i8 undef, %c 872 ret i8 %s 873} 874 875define i8 @undef_collapse_caller() { 876; 877; IS__TUNIT____-LABEL: define {{[^@]+}}@undef_collapse_caller() 878; IS__TUNIT____-NEXT: ret i8 0 879; 880; IS__CGSCC____-LABEL: define {{[^@]+}}@undef_collapse_caller() 881; IS__CGSCC____-NEXT: [[C1:%.*]] = call i8 @undef_collapse_1() 882; IS__CGSCC____-NEXT: [[C2:%.*]] = call i8 @undef_collapse_2() 883; IS__CGSCC____-NEXT: [[A:%.*]] = add i8 [[C1]], [[C2]] 884; IS__CGSCC____-NEXT: ret i8 [[A]] 885; 886 %c1 = call i8 @undef_collapse_1() 887 %c2 = call i8 @undef_collapse_2() 888 %a = add i8 %c1, %c2 889 ret i8 %a 890} 891 892define i32 @ret1or2(i1 %c) { 893; CHECK-LABEL: define {{[^@]+}}@ret1or2 894; CHECK-SAME: (i1 [[C:%.*]]) 895; CHECK-NEXT: [[S:%.*]] = select i1 [[C]], i32 1, i32 2 896; CHECK-NEXT: ret i32 [[S]] 897; 898 %s = select i1 %c, i32 1, i32 2 899 ret i32 %s 900} 901define i1 @callee_range_1(i1 %c1, i1 %c2, i1 %c3) { 902; 903; IS__TUNIT____-LABEL: define {{[^@]+}}@callee_range_1 904; IS__TUNIT____-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]], i1 [[C3:%.*]]) 905; IS__TUNIT____-NEXT: ret i1 true 906; 907; IS__CGSCC____-LABEL: define {{[^@]+}}@callee_range_1 908; IS__CGSCC____-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]], i1 [[C3:%.*]]) 909; IS__CGSCC____-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) 910; IS__CGSCC____-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) 911; IS__CGSCC____-NEXT: [[INDIRECTION:%.*]] = select i1 [[C3]], i32 [[R1]], i32 [[R2]] 912; IS__CGSCC____-NEXT: [[A:%.*]] = add i32 [[R1]], [[INDIRECTION]] 913; IS__CGSCC____-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 4 914; IS__CGSCC____-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 915; IS__CGSCC____-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 916; IS__CGSCC____-NEXT: ret i1 [[F]] 917; 918 %r1 = call i32 @ret1or2(i1 %c1) 919 %r2 = call i32 @ret1or2(i1 %c2) 920 %indirection = select i1 %c3, i32 %r1, i32 %r2 921 %a = add i32 %r1, %indirection 922 %i1 = icmp sle i32 %a, 4 923 %i2 = icmp sge i32 %a, 2 924 %f = and i1 %i1, %i2 925 ret i1 %f 926} 927 928define i1 @callee_range_2(i1 %c1, i1 %c2) { 929; 930; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@callee_range_2 931; IS__TUNIT_OPM-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]]) 932; IS__TUNIT_OPM-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) #2, !range !4 933; IS__TUNIT_OPM-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) #3, !range !4 934; IS__TUNIT_OPM-NEXT: [[A:%.*]] = add i32 [[R1]], [[R2]] 935; IS__TUNIT_OPM-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 3 936; IS__TUNIT_OPM-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 937; IS__TUNIT_OPM-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 938; IS__TUNIT_OPM-NEXT: ret i1 [[F]] 939; 940; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@callee_range_2 941; IS__TUNIT_NPM-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]]) 942; IS__TUNIT_NPM-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) #2, !range !5 943; IS__TUNIT_NPM-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) #3, !range !5 944; IS__TUNIT_NPM-NEXT: [[A:%.*]] = add i32 [[R1]], [[R2]] 945; IS__TUNIT_NPM-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 3 946; IS__TUNIT_NPM-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 947; IS__TUNIT_NPM-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 948; IS__TUNIT_NPM-NEXT: ret i1 [[F]] 949; 950; IS__CGSCC____-LABEL: define {{[^@]+}}@callee_range_2 951; IS__CGSCC____-SAME: (i1 [[C1:%.*]], i1 [[C2:%.*]]) 952; IS__CGSCC____-NEXT: [[R1:%.*]] = call i32 @ret1or2(i1 [[C1]]) 953; IS__CGSCC____-NEXT: [[R2:%.*]] = call i32 @ret1or2(i1 [[C2]]) 954; IS__CGSCC____-NEXT: [[A:%.*]] = add i32 [[R1]], [[R2]] 955; IS__CGSCC____-NEXT: [[I1:%.*]] = icmp sle i32 [[A]], 3 956; IS__CGSCC____-NEXT: [[I2:%.*]] = icmp sge i32 [[A]], 2 957; IS__CGSCC____-NEXT: [[F:%.*]] = and i1 [[I1]], [[I2]] 958; IS__CGSCC____-NEXT: ret i1 [[F]] 959; 960 %r1 = call i32 @ret1or2(i1 %c1) 961 %r2 = call i32 @ret1or2(i1 %c2) 962 %a = add i32 %r1, %r2 963 %i1 = icmp sle i32 %a, 3 964 %i2 = icmp sge i32 %a, 2 965 %f = and i1 %i1, %i2 966 ret i1 %f 967} 968 969 970define i32 @ret100() { 971; CHECK-LABEL: define {{[^@]+}}@ret100() 972; CHECK-NEXT: ret i32 100 973; 974 ret i32 100 975} 976 977define i1 @ctx_adjustment(i32 %V) { 978; 979; IS________OPM-LABEL: define {{[^@]+}}@ctx_adjustment 980; IS________OPM-SAME: (i32 [[V:%.*]]) 981; IS________OPM-NEXT: [[C1:%.*]] = icmp sge i32 [[V]], 100 982; IS________OPM-NEXT: br i1 [[C1]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] 983; IS________OPM: if.true: 984; IS________OPM-NEXT: br label [[END:%.*]] 985; IS________OPM: if.false: 986; IS________OPM-NEXT: br label [[END]] 987; IS________OPM: end: 988; IS________OPM-NEXT: [[PHI:%.*]] = phi i32 [ [[V]], [[IF_TRUE]] ], [ 100, [[IF_FALSE]] ] 989; IS________OPM-NEXT: [[C2:%.*]] = icmp sge i32 [[PHI]], 100 990; IS________OPM-NEXT: ret i1 [[C2]] 991; 992; IS________NPM-LABEL: define {{[^@]+}}@ctx_adjustment 993; IS________NPM-SAME: (i32 [[V:%.*]]) 994; IS________NPM-NEXT: [[C1:%.*]] = icmp sge i32 [[V]], 100 995; IS________NPM-NEXT: br i1 [[C1]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] 996; IS________NPM: if.true: 997; IS________NPM-NEXT: br label [[END:%.*]] 998; IS________NPM: if.false: 999; IS________NPM-NEXT: br label [[END]] 1000; IS________NPM: end: 1001; IS________NPM-NEXT: ret i1 true 1002; 1003 %c1 = icmp sge i32 %V, 100 1004 br i1 %c1, label %if.true, label %if.false 1005if.true: 1006 br label %end 1007if.false: 1008 %call = call i32 @ret100() 1009 br label %end 1010end: 1011 %phi = phi i32 [ %V, %if.true ], [ %call, %if.false ] 1012 %c2 = icmp sge i32 %phi, 100 1013 ret i1 %c2 1014} 1015 1016 1017!0 = !{i32 0, i32 10} 1018!1 = !{i32 10, i32 100} 1019 1020; NOT_TUNIT____: !0 = !{i32 0, i32 10} 1021; NOT_TUNIT____: !1 = !{i32 10, i32 100} 1022; NOT_TUNIT____-NOT: !2 1023 1024; IS__TUNIT_OPM: !0 = !{i32 0, i32 10} 1025; IS__TUNIT_OPM: !1 = !{i32 10, i32 100} 1026; IS__TUNIT_OPM: !2 = !{i32 200, i32 1091} 1027; IS__TUNIT_OPM: !3 = !{i32 0, i32 2} 1028; IS__TUNIT_OPM: !4 = !{i32 1, i32 3} 1029; IS__TUNIT_OPM-NOT: !5 1030 1031; IS__TUNIT_NPM: !0 = !{i32 0, i32 10} 1032; IS__TUNIT_NPM: !1 = !{i32 10, i32 100} 1033; IS__TUNIT_NPM: !2 = !{i32 200, i32 1091} 1034; IS__TUNIT_NPM: !3 = !{i32 1, i32 -2147483648} 1035; IS__TUNIT_NPM: !4 = !{i32 0, i32 2} 1036; IS__TUNIT_NPM: !5 = !{i32 1, i32 3} 1037; IS__TUNIT_NPM-NOT: !6 1038