1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes --check-globals 2; call site specific analysis is disabled 3 4; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM 5 6; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM 7 8; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM 9 10; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM 11 12define i32 @test_range(i32 %unknown) { 13; CHECK-LABEL: define {{[^@]+}}@test_range 14; CHECK-SAME: (i32 [[UNKNOWN:%.*]]) #[[ATTR0:[0-9]+]] { 15; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[UNKNOWN]], 100 16; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 100, i32 0 17; CHECK-NEXT: ret i32 [[TMP2]] 18; 19 %1 = icmp sgt i32 %unknown, 100 20 %2 = select i1 %1, i32 100, i32 0 21 ret i32 %2 22} 23 24define i32 @test1(i32 %unknown, i32 %b) { 25; IS__TUNIT____-LABEL: define {{[^@]+}}@test1 26; IS__TUNIT____-SAME: (i32 [[UNKNOWN:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 27; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i32 @test_range(i32 [[UNKNOWN]]) #[[ATTR0]], !range [[RNG0:![0-9]+]] 28; IS__TUNIT____-NEXT: [[TMP2:%.*]] = sub nsw i32 [[TMP1]], [[B]] 29; IS__TUNIT____-NEXT: ret i32 [[TMP2]] 30; 31; IS__CGSCC____-LABEL: define {{[^@]+}}@test1 32; IS__CGSCC____-SAME: (i32 [[UNKNOWN:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 33; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i32 @test_range(i32 [[UNKNOWN]]) #[[ATTR1:[0-9]+]], !range [[RNG0:![0-9]+]] 34; IS__CGSCC____-NEXT: [[TMP2:%.*]] = sub nsw i32 [[TMP1]], [[B]] 35; IS__CGSCC____-NEXT: ret i32 [[TMP2]] 36; 37 %1 = call i32 @test_range(i32 %unknown) 38 %2 = sub nsw i32 %1, %b 39 ret i32 %2 40} 41 42define i32 @test2(i32 %unknown, i32 %b) { 43; IS__TUNIT____-LABEL: define {{[^@]+}}@test2 44; IS__TUNIT____-SAME: (i32 [[UNKNOWN:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 45; IS__TUNIT____-NEXT: [[TMP1:%.*]] = call i32 @test_range(i32 [[UNKNOWN]]) #[[ATTR0]], !range [[RNG0]] 46; IS__TUNIT____-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], [[B]] 47; IS__TUNIT____-NEXT: ret i32 [[TMP2]] 48; 49; IS__CGSCC____-LABEL: define {{[^@]+}}@test2 50; IS__CGSCC____-SAME: (i32 [[UNKNOWN:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 51; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i32 @test_range(i32 [[UNKNOWN]]) #[[ATTR1]], !range [[RNG0]] 52; IS__CGSCC____-NEXT: [[TMP2:%.*]] = add nsw i32 [[TMP1]], [[B]] 53; IS__CGSCC____-NEXT: ret i32 [[TMP2]] 54; 55 %1 = call i32 @test_range(i32 %unknown) 56 %2 = add nsw i32 %1, %b 57 ret i32 %2 58} 59 60; Positive checks 61 62define i32 @test1_pcheck(i32 %unknown) { 63; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test1_pcheck 64; NOT_CGSCC_NPM-SAME: (i32 [[UNKNOWN:%.*]]) #[[ATTR0]] { 65; NOT_CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i32 @test1(i32 [[UNKNOWN]], i32 noundef 20) 66; NOT_CGSCC_NPM-NEXT: [[TMP2:%.*]] = icmp sle i32 [[TMP1]], 90 67; NOT_CGSCC_NPM-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 68; NOT_CGSCC_NPM-NEXT: ret i32 [[TMP3]] 69; 70; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test1_pcheck 71; IS__CGSCC_NPM-SAME: (i32 [[UNKNOWN:%.*]]) #[[ATTR0]] { 72; IS__CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i32 @test1(i32 [[UNKNOWN]], i32 noundef 20) #[[ATTR1]], !range [[RNG1:![0-9]+]] 73; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = icmp sle i32 [[TMP1]], 90 74; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 75; IS__CGSCC_NPM-NEXT: ret i32 [[TMP3]] 76; 77 %1 = call i32 @test1(i32 %unknown, i32 20) 78 %2 = icmp sle i32 %1, 90 79 %3 = zext i1 %2 to i32 80 ret i32 %3 81} 82 83define i32 @test2_pcheck(i32 %unknown) { 84; CHECK-LABEL: define {{[^@]+}}@test2_pcheck 85; CHECK-SAME: (i32 [[UNKNOWN:%.*]]) #[[ATTR0]] { 86; CHECK-NEXT: [[TMP1:%.*]] = call i32 @test2(i32 [[UNKNOWN]], i32 noundef 20) 87; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[TMP1]], 20 88; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 89; CHECK-NEXT: ret i32 [[TMP3]] 90; 91 %1 = call i32 @test2(i32 %unknown, i32 20) 92 %2 = icmp sge i32 %1, 20 93 %3 = zext i1 %2 to i32 94 ret i32 %3 95} 96 97; Negative checks 98 99define i32 @test1_ncheck(i32 %unknown) { 100; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test1_ncheck 101; NOT_CGSCC_NPM-SAME: (i32 [[UNKNOWN:%.*]]) #[[ATTR0]] { 102; NOT_CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i32 @test1(i32 [[UNKNOWN]], i32 noundef 20) 103; NOT_CGSCC_NPM-NEXT: [[TMP2:%.*]] = icmp sle i32 [[TMP1]], 10 104; NOT_CGSCC_NPM-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 105; NOT_CGSCC_NPM-NEXT: ret i32 [[TMP3]] 106; 107; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@test1_ncheck 108; IS__CGSCC_NPM-SAME: (i32 [[UNKNOWN:%.*]]) #[[ATTR0]] { 109; IS__CGSCC_NPM-NEXT: [[TMP1:%.*]] = call i32 @test1(i32 [[UNKNOWN]], i32 noundef 20) #[[ATTR1]], !range [[RNG1]] 110; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = icmp sle i32 [[TMP1]], 10 111; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 112; IS__CGSCC_NPM-NEXT: ret i32 [[TMP3]] 113; 114 %1 = call i32 @test1(i32 %unknown, i32 20) 115 %2 = icmp sle i32 %1, 10 116 %3 = zext i1 %2 to i32 117 ret i32 %3 118} 119 120define i32 @test2_ncheck(i32 %unknown) { 121; CHECK-LABEL: define {{[^@]+}}@test2_ncheck 122; CHECK-SAME: (i32 [[UNKNOWN:%.*]]) #[[ATTR0]] { 123; CHECK-NEXT: [[TMP1:%.*]] = call i32 @test2(i32 [[UNKNOWN]], i32 noundef 20) 124; CHECK-NEXT: [[TMP2:%.*]] = icmp sge i32 [[TMP1]], 30 125; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 126; CHECK-NEXT: ret i32 [[TMP3]] 127; 128 %1 = call i32 @test2(i32 %unknown, i32 20) 129 %2 = icmp sge i32 %1, 30 130 %3 = zext i1 %2 to i32 131 ret i32 %3 132} 133;. 134; IS__TUNIT____: attributes #[[ATTR0]] = { nofree nosync nounwind readnone willreturn } 135;. 136; IS__CGSCC____: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind readnone willreturn } 137; IS__CGSCC____: attributes #[[ATTR1]] = { readnone willreturn } 138;. 139; NOT_CGSCC_NPM: [[META0:![0-9]+]] = !{i32 0, i32 101} 140;. 141; IS__CGSCC_NPM: [[RNG0]] = !{i32 0, i32 101} 142; IS__CGSCC_NPM: [[RNG1]] = !{i32 -2147483647, i32 -2147483648} 143;. 144