1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
6
7; Verify that we don't emit packed vector shifts instructions if the
8; condition used by the vector select is a vector of constants.
9
10define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
11; SSE2-LABEL: test1:
12; SSE2:       # BB#0:
13; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
14; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
15; SSE2-NEXT:    retq
16;
17; SSE41-LABEL: test1:
18; SSE41:       # BB#0:
19; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
20; SSE41-NEXT:    retq
21;
22; AVX-LABEL: test1:
23; AVX:       # BB#0:
24; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
25; AVX-NEXT:    retq
26  %1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
27  ret <4 x float> %1
28}
29
30define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
31; SSE2-LABEL: test2:
32; SSE2:       # BB#0:
33; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
34; SSE2-NEXT:    movapd %xmm1, %xmm0
35; SSE2-NEXT:    retq
36;
37; SSE41-LABEL: test2:
38; SSE41:       # BB#0:
39; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
40; SSE41-NEXT:    retq
41;
42; AVX-LABEL: test2:
43; AVX:       # BB#0:
44; AVX-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
45; AVX-NEXT:    retq
46  %1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
47  ret <4 x float> %1
48}
49
50define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
51; SSE2-LABEL: test3:
52; SSE2:       # BB#0:
53; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
54; SSE2-NEXT:    retq
55;
56; SSE41-LABEL: test3:
57; SSE41:       # BB#0:
58; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
59; SSE41-NEXT:    retq
60;
61; AVX-LABEL: test3:
62; AVX:       # BB#0:
63; AVX-NEXT:    vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
64; AVX-NEXT:    retq
65  %1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
66  ret <4 x float> %1
67}
68
69define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
70; SSE-LABEL: test4:
71; SSE:       # BB#0:
72; SSE-NEXT:    movaps %xmm1, %xmm0
73; SSE-NEXT:    retq
74;
75; AVX-LABEL: test4:
76; AVX:       # BB#0:
77; AVX-NEXT:    vmovaps %xmm1, %xmm0
78; AVX-NEXT:    retq
79  %1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
80  ret <4 x float> %1
81}
82
83define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
84; SSE-LABEL: test5:
85; SSE:       # BB#0:
86; SSE-NEXT:    retq
87;
88; AVX-LABEL: test5:
89; AVX:       # BB#0:
90; AVX-NEXT:    retq
91  %1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
92  ret <4 x float> %1
93}
94
95define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
96; SSE-LABEL: test6:
97; SSE:       # BB#0:
98; SSE-NEXT:    retq
99;
100; AVX-LABEL: test6:
101; AVX:       # BB#0:
102; AVX-NEXT:    retq
103  %1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
104  ret <8 x i16> %1
105}
106
107define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
108; SSE2-LABEL: test7:
109; SSE2:       # BB#0:
110; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
111; SSE2-NEXT:    movapd %xmm1, %xmm0
112; SSE2-NEXT:    retq
113;
114; SSE41-LABEL: test7:
115; SSE41:       # BB#0:
116; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
117; SSE41-NEXT:    retq
118;
119; AVX1-LABEL: test7:
120; AVX1:       # BB#0:
121; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
122; AVX1-NEXT:    retq
123;
124; AVX2-LABEL: test7:
125; AVX2:       # BB#0:
126; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
127; AVX2-NEXT:    retq
128  %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
129  ret <8 x i16> %1
130}
131
132define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
133; SSE2-LABEL: test8:
134; SSE2:       # BB#0:
135; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
136; SSE2-NEXT:    retq
137;
138; SSE41-LABEL: test8:
139; SSE41:       # BB#0:
140; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
141; SSE41-NEXT:    retq
142;
143; AVX1-LABEL: test8:
144; AVX1:       # BB#0:
145; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
146; AVX1-NEXT:    retq
147;
148; AVX2-LABEL: test8:
149; AVX2:       # BB#0:
150; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
151; AVX2-NEXT:    retq
152  %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
153  ret <8 x i16> %1
154}
155
156define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
157; SSE-LABEL: test9:
158; SSE:       # BB#0:
159; SSE-NEXT:    movaps %xmm1, %xmm0
160; SSE-NEXT:    retq
161;
162; AVX-LABEL: test9:
163; AVX:       # BB#0:
164; AVX-NEXT:    vmovaps %xmm1, %xmm0
165; AVX-NEXT:    retq
166  %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
167  ret <8 x i16> %1
168}
169
170define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
171; SSE-LABEL: test10:
172; SSE:       # BB#0:
173; SSE-NEXT:    retq
174;
175; AVX-LABEL: test10:
176; AVX:       # BB#0:
177; AVX-NEXT:    retq
178  %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
179  ret <8 x i16> %1
180}
181
182define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
183; SSE2-LABEL: test11:
184; SSE2:       # BB#0:
185; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [0,65535,65535,0,65535,65535,65535,65535]
186; SSE2-NEXT:    andps %xmm2, %xmm0
187; SSE2-NEXT:    andnps %xmm1, %xmm2
188; SSE2-NEXT:    orps %xmm2, %xmm0
189; SSE2-NEXT:    retq
190;
191; SSE41-LABEL: test11:
192; SSE41:       # BB#0:
193; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3],xmm0[4,5,6,7]
194; SSE41-NEXT:    retq
195;
196; AVX-LABEL: test11:
197; AVX:       # BB#0:
198; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3],xmm0[4,5,6,7]
199; AVX-NEXT:    retq
200  %1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
201  ret <8 x i16> %1
202}
203
204define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
205; SSE-LABEL: test12:
206; SSE:       # BB#0:
207; SSE-NEXT:    movaps %xmm1, %xmm0
208; SSE-NEXT:    retq
209;
210; AVX-LABEL: test12:
211; AVX:       # BB#0:
212; AVX-NEXT:    vmovaps %xmm1, %xmm0
213; AVX-NEXT:    retq
214  %1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
215  ret <8 x i16> %1
216}
217
218define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
219; SSE-LABEL: test13:
220; SSE:       # BB#0:
221; SSE-NEXT:    movaps %xmm1, %xmm0
222; SSE-NEXT:    retq
223;
224; AVX-LABEL: test13:
225; AVX:       # BB#0:
226; AVX-NEXT:    vmovaps %xmm1, %xmm0
227; AVX-NEXT:    retq
228  %1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
229  ret <8 x i16> %1
230}
231
232; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
233define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
234; SSE-LABEL: test14:
235; SSE:       # BB#0:
236; SSE-NEXT:    retq
237;
238; AVX-LABEL: test14:
239; AVX:       # BB#0:
240; AVX-NEXT:    retq
241  %1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
242  ret <4 x float> %1
243}
244
245define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
246; SSE-LABEL: test15:
247; SSE:       # BB#0:
248; SSE-NEXT:    retq
249;
250; AVX-LABEL: test15:
251; AVX:       # BB#0:
252; AVX-NEXT:    retq
253  %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
254  ret <8 x i16> %1
255}
256
257; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
258define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
259; SSE-LABEL: test16:
260; SSE:       # BB#0:
261; SSE-NEXT:    movaps %xmm1, %xmm0
262; SSE-NEXT:    retq
263;
264; AVX-LABEL: test16:
265; AVX:       # BB#0:
266; AVX-NEXT:    vmovaps %xmm1, %xmm0
267; AVX-NEXT:    retq
268  %1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
269  ret <4 x float> %1
270}
271
272define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
273; SSE-LABEL: test17:
274; SSE:       # BB#0:
275; SSE-NEXT:    movaps %xmm1, %xmm0
276; SSE-NEXT:    retq
277;
278; AVX-LABEL: test17:
279; AVX:       # BB#0:
280; AVX-NEXT:    vmovaps %xmm1, %xmm0
281; AVX-NEXT:    retq
282  %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
283  ret <8 x i16> %1
284}
285
286define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
287; SSE2-LABEL: test18:
288; SSE2:       # BB#0:
289; SSE2-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
290; SSE2-NEXT:    retq
291;
292; SSE41-LABEL: test18:
293; SSE41:       # BB#0:
294; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
295; SSE41-NEXT:    retq
296;
297; AVX-LABEL: test18:
298; AVX:       # BB#0:
299; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
300; AVX-NEXT:    retq
301  %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
302  ret <4 x float> %1
303}
304
305define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
306; SSE2-LABEL: test19:
307; SSE2:       # BB#0:
308; SSE2-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
309; SSE2-NEXT:    retq
310;
311; SSE41-LABEL: test19:
312; SSE41:       # BB#0:
313; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
314; SSE41-NEXT:    retq
315;
316; AVX1-LABEL: test19:
317; AVX1:       # BB#0:
318; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
319; AVX1-NEXT:    retq
320;
321; AVX2-LABEL: test19:
322; AVX2:       # BB#0:
323; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
324; AVX2-NEXT:    retq
325  %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
326  ret <4 x i32> %1
327}
328
329define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
330; SSE2-LABEL: test20:
331; SSE2:       # BB#0:
332; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
333; SSE2-NEXT:    retq
334;
335; SSE41-LABEL: test20:
336; SSE41:       # BB#0:
337; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
338; SSE41-NEXT:    retq
339;
340; AVX-LABEL: test20:
341; AVX:       # BB#0:
342; AVX-NEXT:    vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
343; AVX-NEXT:    retq
344  %1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
345  ret <2 x double> %1
346}
347
348define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
349; SSE2-LABEL: test21:
350; SSE2:       # BB#0:
351; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
352; SSE2-NEXT:    retq
353;
354; SSE41-LABEL: test21:
355; SSE41:       # BB#0:
356; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
357; SSE41-NEXT:    retq
358;
359; AVX1-LABEL: test21:
360; AVX1:       # BB#0:
361; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
362; AVX1-NEXT:    retq
363;
364; AVX2-LABEL: test21:
365; AVX2:       # BB#0:
366; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
367; AVX2-NEXT:    retq
368  %1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
369  ret <2 x i64> %1
370}
371
372define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
373; SSE2-LABEL: test22:
374; SSE2:       # BB#0:
375; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
376; SSE2-NEXT:    movaps %xmm1, %xmm0
377; SSE2-NEXT:    retq
378;
379; SSE41-LABEL: test22:
380; SSE41:       # BB#0:
381; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
382; SSE41-NEXT:    retq
383;
384; AVX-LABEL: test22:
385; AVX:       # BB#0:
386; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
387; AVX-NEXT:    retq
388  %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
389  ret <4 x float> %1
390}
391
392define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
393; SSE2-LABEL: test23:
394; SSE2:       # BB#0:
395; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
396; SSE2-NEXT:    movaps %xmm1, %xmm0
397; SSE2-NEXT:    retq
398;
399; SSE41-LABEL: test23:
400; SSE41:       # BB#0:
401; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
402; SSE41-NEXT:    retq
403;
404; AVX1-LABEL: test23:
405; AVX1:       # BB#0:
406; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
407; AVX1-NEXT:    retq
408;
409; AVX2-LABEL: test23:
410; AVX2:       # BB#0:
411; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
412; AVX2-NEXT:    retq
413  %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
414  ret <4 x i32> %1
415}
416
417define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
418; SSE2-LABEL: test24:
419; SSE2:       # BB#0:
420; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
421; SSE2-NEXT:    movapd %xmm1, %xmm0
422; SSE2-NEXT:    retq
423;
424; SSE41-LABEL: test24:
425; SSE41:       # BB#0:
426; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
427; SSE41-NEXT:    retq
428;
429; AVX-LABEL: test24:
430; AVX:       # BB#0:
431; AVX-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
432; AVX-NEXT:    retq
433  %1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
434  ret <2 x double> %1
435}
436
437define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
438; SSE2-LABEL: test25:
439; SSE2:       # BB#0:
440; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
441; SSE2-NEXT:    movapd %xmm1, %xmm0
442; SSE2-NEXT:    retq
443;
444; SSE41-LABEL: test25:
445; SSE41:       # BB#0:
446; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
447; SSE41-NEXT:    retq
448;
449; AVX1-LABEL: test25:
450; AVX1:       # BB#0:
451; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
452; AVX1-NEXT:    retq
453;
454; AVX2-LABEL: test25:
455; AVX2:       # BB#0:
456; AVX2-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
457; AVX2-NEXT:    retq
458  %1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
459  ret <2 x i64> %1
460}
461
462define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) {
463; SSE-LABEL: select_of_shuffles_0:
464; SSE:       # BB#0:
465; SSE-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
466; SSE-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
467; SSE-NEXT:    subps %xmm1, %xmm0
468; SSE-NEXT:    retq
469;
470; AVX-LABEL: select_of_shuffles_0:
471; AVX:       # BB#0:
472; AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
473; AVX-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
474; AVX-NEXT:    vsubps %xmm1, %xmm0, %xmm0
475; AVX-NEXT:    retq
476  %1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
477  %2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
478  %3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1
479  %4 = shufflevector <2 x float> %b0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
480  %5 = shufflevector <2 x float> %b1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
481  %6 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %5, <4 x float> %4
482  %7 = fsub <4 x float> %3, %6
483  ret <4 x float> %7
484}
485
486; PR20677
487define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) {
488; SSE-LABEL: select_illegal:
489; SSE:       # BB#0:
490; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm4
491; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm5
492; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm6
493; SSE-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm7
494; SSE-NEXT:    movaps %xmm7, 112(%rdi)
495; SSE-NEXT:    movaps %xmm6, 96(%rdi)
496; SSE-NEXT:    movaps %xmm5, 80(%rdi)
497; SSE-NEXT:    movaps %xmm4, 64(%rdi)
498; SSE-NEXT:    movaps %xmm3, 48(%rdi)
499; SSE-NEXT:    movaps %xmm2, 32(%rdi)
500; SSE-NEXT:    movaps %xmm1, 16(%rdi)
501; SSE-NEXT:    movaps %xmm0, (%rdi)
502; SSE-NEXT:    movq %rdi, %rax
503; SSE-NEXT:    retq
504;
505; AVX-LABEL: select_illegal:
506; AVX:       # BB#0:
507; AVX-NEXT:    vmovaps %ymm6, %ymm2
508; AVX-NEXT:    vmovaps %ymm7, %ymm3
509; AVX-NEXT:    retq
510  %sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
511  ret <16 x double> %sel
512}
513