1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
6; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512F
7;
8; Combine tests involving SSE3/SSSE3 target shuffles (MOVDDUP, MOVSHDUP, MOVSLDUP, PSHUFB)
9
10declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
11
12define <16 x i8> @combine_vpshufb_as_zero(<16 x i8> %a0) {
13; SSE-LABEL: combine_vpshufb_as_zero:
14; SSE:       # BB#0:
15; SSE-NEXT:    xorps %xmm0, %xmm0
16; SSE-NEXT:    retq
17;
18; AVX-LABEL: combine_vpshufb_as_zero:
19; AVX:       # BB#0:
20; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
21; AVX-NEXT:    retq
22  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>)
23  %res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 128, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>)
24  %res2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res1, <16 x i8> <i8 0, i8 1, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
25  ret <16 x i8> %res2
26}
27
28define <16 x i8> @combine_vpshufb_as_movq(<16 x i8> %a0) {
29; SSE-LABEL: combine_vpshufb_as_movq:
30; SSE:       # BB#0:
31; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
32; SSE-NEXT:    retq
33;
34; AVX-LABEL: combine_vpshufb_as_movq:
35; AVX:       # BB#0:
36; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
37; AVX-NEXT:    retq
38  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 128, i8 1, i8 128, i8 2, i8 128, i8 3, i8 128, i8 4, i8 128, i8 5, i8 128, i8 6, i8 128, i8 7, i8 128>)
39  %res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i8 12, i8 14, i8 1, i8 3, i8 5, i8 7, i8 9, i8 11, i8 13, i8 15>)
40  ret <16 x i8> %res1
41}
42
43define <2 x double> @combine_pshufb_as_movsd(<2 x double> %a0, <2 x double> %a1) {
44; SSSE3-LABEL: combine_pshufb_as_movsd:
45; SSSE3:       # BB#0:
46; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
47; SSSE3-NEXT:    movapd %xmm1, %xmm0
48; SSSE3-NEXT:    retq
49;
50; SSE41-LABEL: combine_pshufb_as_movsd:
51; SSE41:       # BB#0:
52; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
53; SSE41-NEXT:    retq
54;
55; AVX1-LABEL: combine_pshufb_as_movsd:
56; AVX1:       # BB#0:
57; AVX1-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
58; AVX1-NEXT:    retq
59;
60; AVX2-LABEL: combine_pshufb_as_movsd:
61; AVX2:       # BB#0:
62; AVX2-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
63; AVX2-NEXT:    retq
64;
65; AVX512F-LABEL: combine_pshufb_as_movsd:
66; AVX512F:       # BB#0:
67; AVX512F-NEXT:    vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
68; AVX512F-NEXT:    retq
69  %1 = shufflevector <2 x double> %a0, <2 x double> %a1, <2 x i32> <i32 3, i32 0>
70  %2 = bitcast <2 x double> %1 to <16 x i8>
71  %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
72  %4 = bitcast <16 x i8> %3 to <2 x double>
73  ret <2 x double> %4
74}
75
76define <4 x float> @combine_pshufb_as_movss(<4 x float> %a0, <4 x float> %a1) {
77; SSSE3-LABEL: combine_pshufb_as_movss:
78; SSSE3:       # BB#0:
79; SSSE3-NEXT:    movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
80; SSSE3-NEXT:    retq
81;
82; SSE41-LABEL: combine_pshufb_as_movss:
83; SSE41:       # BB#0:
84; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
85; SSE41-NEXT:    retq
86;
87; AVX1-LABEL: combine_pshufb_as_movss:
88; AVX1:       # BB#0:
89; AVX1-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
90; AVX1-NEXT:    retq
91;
92; AVX2-LABEL: combine_pshufb_as_movss:
93; AVX2:       # BB#0:
94; AVX2-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
95; AVX2-NEXT:    retq
96;
97; AVX512F-LABEL: combine_pshufb_as_movss:
98; AVX512F:       # BB#0:
99; AVX512F-NEXT:    vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
100; AVX512F-NEXT:    retq
101  %1 = shufflevector <4 x float> %a0, <4 x float> %a1, <4 x i32> <i32 4, i32 3, i32 2, i32 1>
102  %2 = bitcast <4 x float> %1 to <16 x i8>
103  %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 12, i8 13, i8 14, i8 15, i8 8, i8 9, i8 10, i8 11, i8 4, i8 5, i8 6, i8 7>)
104  %4 = bitcast <16 x i8> %3 to <4 x float>
105  ret <4 x float> %4
106}
107
108define <4 x i32> @combine_pshufb_as_zext(<16 x i8> %a0) {
109; SSSE3-LABEL: combine_pshufb_as_zext:
110; SSSE3:       # BB#0:
111; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
112; SSSE3-NEXT:    retq
113;
114; SSE41-LABEL: combine_pshufb_as_zext:
115; SSE41:       # BB#0:
116; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
117; SSE41-NEXT:    retq
118;
119; AVX-LABEL: combine_pshufb_as_zext:
120; AVX:       # BB#0:
121; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
122; AVX-NEXT:    retq
123  %1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1, i8 2, i8 -1, i8 -1, i8 -1, i8 3, i8 -1, i8 -1, i8 -1>)
124  %2 = bitcast <16 x i8> %1 to <4 x i32>
125  ret <4 x i32> %2
126}
127
128define <2 x double> @combine_pshufb_as_vzmovl_64(<2 x double> %a0) {
129; SSE-LABEL: combine_pshufb_as_vzmovl_64:
130; SSE:       # BB#0:
131; SSE-NEXT:    movq {{.*#+}} xmm0 = xmm0[0],zero
132; SSE-NEXT:    retq
133;
134; AVX-LABEL: combine_pshufb_as_vzmovl_64:
135; AVX:       # BB#0:
136; AVX-NEXT:    vmovq {{.*#+}} xmm0 = xmm0[0],zero
137; AVX-NEXT:    retq
138  %1 = bitcast <2 x double> %a0 to <16 x i8>
139  %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
140  %3 = bitcast <16 x i8> %2 to <2 x double>
141  ret <2 x double> %3
142}
143
144define <4 x float> @combine_pshufb_as_vzmovl_32(<4 x float> %a0) {
145; SSSE3-LABEL: combine_pshufb_as_vzmovl_32:
146; SSSE3:       # BB#0:
147; SSSE3-NEXT:    xorps %xmm1, %xmm1
148; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
149; SSSE3-NEXT:    movaps %xmm1, %xmm0
150; SSSE3-NEXT:    retq
151;
152; SSE41-LABEL: combine_pshufb_as_vzmovl_32:
153; SSE41:       # BB#0:
154; SSE41-NEXT:    xorps %xmm1, %xmm1
155; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
156; SSE41-NEXT:    retq
157;
158; AVX1-LABEL: combine_pshufb_as_vzmovl_32:
159; AVX1:       # BB#0:
160; AVX1-NEXT:    vxorps %xmm1, %xmm1, %xmm1
161; AVX1-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
162; AVX1-NEXT:    retq
163;
164; AVX2-LABEL: combine_pshufb_as_vzmovl_32:
165; AVX2:       # BB#0:
166; AVX2-NEXT:    vxorps %xmm1, %xmm1, %xmm1
167; AVX2-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
168; AVX2-NEXT:    retq
169;
170; AVX512F-LABEL: combine_pshufb_as_vzmovl_32:
171; AVX512F:       # BB#0:
172; AVX512F-NEXT:    vxorps %xmm1, %xmm1, %xmm1
173; AVX512F-NEXT:    vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
174; AVX512F-NEXT:    retq
175  %1 = bitcast <4 x float> %a0 to <16 x i8>
176  %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
177  %3 = bitcast <16 x i8> %2 to <4 x float>
178  ret <4 x float> %3
179}
180
181define <4 x float> @combine_pshufb_movddup(<4 x float> %a0) {
182; SSE-LABEL: combine_pshufb_movddup:
183; SSE:       # BB#0:
184; SSE-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,7,7,7,7,5,5,5,5,7,7,7,7]
185; SSE-NEXT:    retq
186;
187; AVX-LABEL: combine_pshufb_movddup:
188; AVX:       # BB#0:
189; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,7,7,7,7,5,5,5,5,7,7,7,7]
190; AVX-NEXT:    retq
191  %1 = bitcast <4 x float> %a0 to <16 x i8>
192  %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 1, i8 1, i8 1, i8 1, i8 3, i8 3, i8 3, i8 3>)
193  %3 = bitcast <16 x i8> %2 to <4 x float>
194  %4 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
195  ret <4 x float> %4
196}
197
198define <4 x float> @combine_pshufb_movshdup(<4 x float> %a0) {
199; SSE-LABEL: combine_pshufb_movshdup:
200; SSE:       # BB#0:
201; SSE-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[7,7,7,7,7,7,7,7,3,3,3,3,3,3,3,3]
202; SSE-NEXT:    retq
203;
204; AVX-LABEL: combine_pshufb_movshdup:
205; AVX:       # BB#0:
206; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[7,7,7,7,7,7,7,7,3,3,3,3,3,3,3,3]
207; AVX-NEXT:    retq
208  %1 = bitcast <4 x float> %a0 to <16 x i8>
209  %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 1, i8 1, i8 1, i8 1, i8 3, i8 3, i8 3, i8 3>)
210  %3 = bitcast <16 x i8> %2 to <4 x float>
211  %4 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
212  ret <4 x float> %4
213}
214
215define <4 x float> @combine_pshufb_movsldup(<4 x float> %a0) {
216; SSE-LABEL: combine_pshufb_movsldup:
217; SSE:       # BB#0:
218; SSE-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1]
219; SSE-NEXT:    retq
220;
221; AVX-LABEL: combine_pshufb_movsldup:
222; AVX:       # BB#0:
223; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[5,5,5,5,5,5,5,5,1,1,1,1,1,1,1,1]
224; AVX-NEXT:    retq
225  %1 = bitcast <4 x float> %a0 to <16 x i8>
226  %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 1, i8 1, i8 1, i8 1, i8 3, i8 3, i8 3, i8 3>)
227  %3 = bitcast <16 x i8> %2 to <4 x float>
228  %4 = shufflevector <4 x float> %3, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
229  ret <4 x float> %4
230}
231
232define <16 x i8> @combine_pshufb_palignr(<16 x i8> %a0, <16 x i8> %a1) {
233; SSE-LABEL: combine_pshufb_palignr:
234; SSE:       # BB#0:
235; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
236; SSE-NEXT:    retq
237;
238; AVX-LABEL: combine_pshufb_palignr:
239; AVX:       # BB#0:
240; AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
241; AVX-NEXT:    retq
242  %1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
243  %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
244  ret <16 x i8> %2
245}
246
247define <16 x i8> @combine_pshufb_pslldq(<16 x i8> %a0) {
248; SSE-LABEL: combine_pshufb_pslldq:
249; SSE:       # BB#0:
250; SSE-NEXT:    xorps %xmm0, %xmm0
251; SSE-NEXT:    retq
252;
253; AVX-LABEL: combine_pshufb_pslldq:
254; AVX:       # BB#0:
255; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
256; AVX-NEXT:    retq
257  %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
258  %2 = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
259  ret <16 x i8> %2
260}
261
262define <16 x i8> @combine_pshufb_psrldq(<16 x i8> %a0) {
263; SSE-LABEL: combine_pshufb_psrldq:
264; SSE:       # BB#0:
265; SSE-NEXT:    xorps %xmm0, %xmm0
266; SSE-NEXT:    retq
267;
268; AVX-LABEL: combine_pshufb_psrldq:
269; AVX:       # BB#0:
270; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
271; AVX-NEXT:    retq
272  %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
273  %2 = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
274  ret <16 x i8> %2
275}
276
277define <16 x i8> @combine_and_pshufb(<16 x i8> %a0) {
278; SSSE3-LABEL: combine_and_pshufb:
279; SSSE3:       # BB#0:
280; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
281; SSSE3-NEXT:    retq
282;
283; SSE41-LABEL: combine_and_pshufb:
284; SSE41:       # BB#0:
285; SSE41-NEXT:    pxor %xmm1, %xmm1
286; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
287; SSE41-NEXT:    retq
288;
289; AVX-LABEL: combine_and_pshufb:
290; AVX:       # BB#0:
291; AVX-NEXT:    vpxor %xmm1, %xmm1, %xmm1
292; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
293; AVX-NEXT:    retq
294  %1 = shufflevector <16 x i8> %a0, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
295  %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
296  ret <16 x i8> %2
297}
298
299define <16 x i8> @combine_pshufb_and(<16 x i8> %a0) {
300; SSSE3-LABEL: combine_pshufb_and:
301; SSSE3:       # BB#0:
302; SSSE3-NEXT:    andps {{.*}}(%rip), %xmm0
303; SSSE3-NEXT:    retq
304;
305; SSE41-LABEL: combine_pshufb_and:
306; SSE41:       # BB#0:
307; SSE41-NEXT:    pxor %xmm1, %xmm1
308; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
309; SSE41-NEXT:    retq
310;
311; AVX-LABEL: combine_pshufb_and:
312; AVX:       # BB#0:
313; AVX-NEXT:    vpxor %xmm1, %xmm1, %xmm1
314; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
315; AVX-NEXT:    retq
316  %1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 8, i8 9, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
317  %2 = shufflevector <16 x i8> %1, <16 x i8> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
318  ret <16 x i8> %2
319}
320
321define <16 x i8> @combine_pshufb_as_palignr(<16 x i8> %a0) {
322; SSE-LABEL: combine_pshufb_as_palignr:
323; SSE:       # BB#0:
324; SSE-NEXT:    palignr {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0]
325; SSE-NEXT:    retq
326;
327; AVX-LABEL: combine_pshufb_as_palignr:
328; AVX:       # BB#0:
329; AVX-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0]
330; AVX-NEXT:    retq
331  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 undef, i8 undef, i8 0>)
332  ret <16 x i8> %res0
333}
334
335define <16 x i8> @combine_pshufb_as_pslldq(<16 x i8> %a0) {
336; SSE-LABEL: combine_pshufb_as_pslldq:
337; SSE:       # BB#0:
338; SSE-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
339; SSE-NEXT:    retq
340;
341; AVX-LABEL: combine_pshufb_as_pslldq:
342; AVX:       # BB#0:
343; AVX-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
344; AVX-NEXT:    retq
345  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>)
346  ret <16 x i8> %res0
347}
348
349define <16 x i8> @combine_pshufb_as_psrldq(<16 x i8> %a0) {
350; SSE-LABEL: combine_pshufb_as_psrldq:
351; SSE:       # BB#0:
352; SSE-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
353; SSE-NEXT:    retq
354;
355; AVX-LABEL: combine_pshufb_as_psrldq:
356; AVX:       # BB#0:
357; AVX-NEXT:    vpsrldq {{.*#+}} xmm0 = xmm0[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
358; AVX-NEXT:    retq
359  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 15, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
360  ret <16 x i8> %res0
361}
362
363define <16 x i8> @combine_pshufb_as_psrlw(<16 x i8> %a0) {
364; SSE-LABEL: combine_pshufb_as_psrlw:
365; SSE:       # BB#0:
366; SSE-NEXT:    psrlw $8, %xmm0
367; SSE-NEXT:    retq
368;
369; AVX-LABEL: combine_pshufb_as_psrlw:
370; AVX:       # BB#0:
371; AVX-NEXT:    vpsrlw $8, %xmm0, %xmm0
372; AVX-NEXT:    retq
373  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 1, i8 128, i8 3, i8 128, i8 5, i8 128, i8 7, i8 128, i8 9, i8 128, i8 11, i8 128, i8 13, i8 128, i8 15, i8 128>)
374  ret <16 x i8> %res0
375}
376
377define <16 x i8> @combine_pshufb_as_pslld(<16 x i8> %a0) {
378; SSE-LABEL: combine_pshufb_as_pslld:
379; SSE:       # BB#0:
380; SSE-NEXT:    pslld $24, %xmm0
381; SSE-NEXT:    retq
382;
383; AVX-LABEL: combine_pshufb_as_pslld:
384; AVX:       # BB#0:
385; AVX-NEXT:    vpslld $24, %xmm0, %xmm0
386; AVX-NEXT:    retq
387  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 128, i8 128, i8 128, i8 0, i8 128, i8 128, i8 128, i8 4, i8 128, i8 128, i8 128, i8 8, i8 128, i8 128, i8 128, i8 12>)
388  ret <16 x i8> %res0
389}
390
391define <16 x i8> @combine_pshufb_as_psrlq(<16 x i8> %a0) {
392; SSE-LABEL: combine_pshufb_as_psrlq:
393; SSE:       # BB#0:
394; SSE-NEXT:    psrlq $40, %xmm0
395; SSE-NEXT:    retq
396;
397; AVX-LABEL: combine_pshufb_as_psrlq:
398; AVX:       # BB#0:
399; AVX-NEXT:    vpsrlq $40, %xmm0, %xmm0
400; AVX-NEXT:    retq
401  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 5, i8 6, i8 7, i8 128, i8 128, i8 128, i8 128, i8 128, i8 13, i8 14, i8 15, i8 128, i8 128, i8 128, i8 128, i8 128>)
402  ret <16 x i8> %res0
403}
404
405define <16 x i8> @combine_pshufb_as_pshuflw(<16 x i8> %a0) {
406; SSE-LABEL: combine_pshufb_as_pshuflw:
407; SSE:       # BB#0:
408; SSE-NEXT:    pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
409; SSE-NEXT:    retq
410;
411; AVX-LABEL: combine_pshufb_as_pshuflw:
412; AVX:       # BB#0:
413; AVX-NEXT:    vpshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
414; AVX-NEXT:    retq
415  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 2, i8 3, i8 0, i8 1, i8 6, i8 7, i8 4, i8 5, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
416  ret <16 x i8> %res0
417}
418
419define <16 x i8> @combine_pshufb_as_pshufhw(<16 x i8> %a0) {
420; SSE-LABEL: combine_pshufb_as_pshufhw:
421; SSE:       # BB#0:
422; SSE-NEXT:    pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
423; SSE-NEXT:    retq
424;
425; AVX-LABEL: combine_pshufb_as_pshufhw:
426; AVX:       # BB#0:
427; AVX-NEXT:    vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6]
428; AVX-NEXT:    retq
429  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 10, i8 11, i8 8, i8 9, i8 14, i8 15, i8 12, i8 13>)
430  ret <16 x i8> %res0
431}
432
433define <16 x i8> @combine_pshufb_not_as_pshufw(<16 x i8> %a0) {
434; SSE-LABEL: combine_pshufb_not_as_pshufw:
435; SSE:       # BB#0:
436; SSE-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
437; SSE-NEXT:    retq
438;
439; AVX-LABEL: combine_pshufb_not_as_pshufw:
440; AVX:       # BB#0:
441; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
442; AVX-NEXT:    retq
443  %res0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 2, i8 3, i8 0, i8 1, i8 6, i8 7, i8 4, i8 5, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
444  %res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 10, i8 11, i8 8, i8 9, i8 14, i8 15, i8 12, i8 13>)
445  ret <16 x i8> %res1
446}
447
448define <16 x i8> @combine_pshufb_as_unary_unpcklbw(<16 x i8> %a0) {
449; SSE-LABEL: combine_pshufb_as_unary_unpcklbw:
450; SSE:       # BB#0:
451; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
452; SSE-NEXT:    retq
453;
454; AVX-LABEL: combine_pshufb_as_unary_unpcklbw:
455; AVX:       # BB#0:
456; AVX-NEXT:    vpunpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
457; AVX-NEXT:    retq
458  %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 undef, i8 undef, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7>)
459  ret <16 x i8> %1
460}
461
462define <16 x i8> @combine_pshufb_as_unary_unpckhwd(<16 x i8> %a0) {
463; SSE-LABEL: combine_pshufb_as_unary_unpckhwd:
464; SSE:       # BB#0:
465; SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
466; SSE-NEXT:    retq
467;
468; AVX-LABEL: combine_pshufb_as_unary_unpckhwd:
469; AVX:       # BB#0:
470; AVX-NEXT:    vpunpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
471; AVX-NEXT:    retq
472  %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 8, i8 9, i8 8, i8 9, i8 10, i8 11, i8 10, i8 11, i8 12, i8 13, i8 12, i8 13, i8 14, i8 15, i8 undef, i8 undef>)
473  ret <16 x i8> %1
474}
475
476define <16 x i8> @combine_psrlw_pshufb(<8 x i16> %a0) {
477; SSE-LABEL: combine_psrlw_pshufb:
478; SSE:       # BB#0:
479; SSE-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero
480; SSE-NEXT:    retq
481;
482; AVX-LABEL: combine_psrlw_pshufb:
483; AVX:       # BB#0:
484; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[1],zero,zero,zero
485; AVX-NEXT:    retq
486  %1 = lshr <8 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
487  %2 = bitcast <8 x i16> %1 to <16 x i8>
488  %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1>)
489  ret <16 x i8> %3
490}
491
492define <16 x i8> @combine_pslld_pshufb(<4 x i32> %a0) {
493; SSE-LABEL: combine_pslld_pshufb:
494; SSE:       # BB#0:
495; SSE-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[2,1,0],zero,xmm0[6,5,4],zero,xmm0[10,9,8],zero,xmm0[14,13,12],zero
496; SSE-NEXT:    retq
497;
498; AVX-LABEL: combine_pslld_pshufb:
499; AVX:       # BB#0:
500; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[2,1,0],zero,xmm0[6,5,4],zero,xmm0[10,9,8],zero,xmm0[14,13,12],zero
501; AVX-NEXT:    retq
502  %1 = shl <4 x i32> %a0, <i32 8, i32 8, i32 8, i32 8>
503  %2 = bitcast <4 x i32> %1 to <16 x i8>
504  %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 3, i8 2, i8 1, i8 0, i8 7, i8 6, i8 5, i8 4, i8 11, i8 10, i8 9, i8 8, i8 15, i8 14, i8 13, i8 12>)
505  ret <16 x i8> %3
506}
507
508define <16 x i8> @combine_psrlq_pshufb(<2 x i64> %a0) {
509; SSE-LABEL: combine_psrlq_pshufb:
510; SSE:       # BB#0:
511; SSE-NEXT:    pshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[7,6],zero,zero,zero,zero,zero,zero,xmm0[15,14]
512; SSE-NEXT:    retq
513;
514; AVX-LABEL: combine_psrlq_pshufb:
515; AVX:       # BB#0:
516; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[7,6],zero,zero,zero,zero,zero,zero,xmm0[15,14]
517; AVX-NEXT:    retq
518  %1 = lshr <2 x i64> %a0, <i64 48, i64 48>
519  %2 = bitcast <2 x i64> %1 to <16 x i8>
520  %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %2, <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>)
521  ret <16 x i8> %3
522}
523
524define <16 x i8> @combine_unpckl_arg0_pshufb(<16 x i8> %a0, <16 x i8> %a1) {
525; SSE-LABEL: combine_unpckl_arg0_pshufb:
526; SSE:       # BB#0:
527; SSE-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
528; SSE-NEXT:    retq
529;
530; AVX-LABEL: combine_unpckl_arg0_pshufb:
531; AVX:       # BB#0:
532; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
533; AVX-NEXT:    retq
534  %1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
535  %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1>)
536  ret <16 x i8> %2
537}
538
539define <16 x i8> @combine_unpckl_arg1_pshufb(<16 x i8> %a0, <16 x i8> %a1) {
540; SSE-LABEL: combine_unpckl_arg1_pshufb:
541; SSE:       # BB#0:
542; SSE-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
543; SSE-NEXT:    movdqa %xmm1, %xmm0
544; SSE-NEXT:    retq
545;
546; AVX-LABEL: combine_unpckl_arg1_pshufb:
547; AVX:       # BB#0:
548; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
549; AVX-NEXT:    retq
550  %1 = shufflevector <16 x i8> %a0, <16 x i8> %a1, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
551  %2 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 1, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1, i8 1, i8 -1, i8 -1, i8 -1>)
552  ret <16 x i8> %2
553}
554
555define <16 x i8> @constant_fold_pshufb() {
556; SSE-LABEL: constant_fold_pshufb:
557; SSE:       # BB#0:
558; SSE-NEXT:    movaps {{.*#+}} xmm0 = <14,0,0,0,u,u,0,0,0,0,0,0,0,0,8,9>
559; SSE-NEXT:    retq
560;
561; AVX-LABEL: constant_fold_pshufb:
562; AVX:       # BB#0:
563; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = <14,0,0,0,u,u,0,0,0,0,0,0,0,0,8,9>
564; AVX-NEXT:    retq
565  %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8> <i8 1, i8 -1, i8 -1, i8 -1, i8 undef, i8 undef, i8 -1, i8 -1, i8 15, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 7, i8 6>)
566  ret <16 x i8> %1
567}
568