1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX1
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX2
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512DQ
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512DQVL
9; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512BWVL
10
11;
12; Variable Shifts
13;
14
15define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
16; AVX1-LABEL: var_shift_v4i64:
17; AVX1:       # BB#0:
18; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
19; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
20; AVX1-NEXT:    vpsllq %xmm2, %xmm3, %xmm4
21; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
22; AVX1-NEXT:    vpsllq %xmm2, %xmm3, %xmm2
23; AVX1-NEXT:    vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7]
24; AVX1-NEXT:    vpsllq %xmm1, %xmm0, %xmm3
25; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
26; AVX1-NEXT:    vpsllq %xmm1, %xmm0, %xmm0
27; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
28; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
29; AVX1-NEXT:    retq
30;
31; AVX2-LABEL: var_shift_v4i64:
32; AVX2:       # BB#0:
33; AVX2-NEXT:    vpsllvq %ymm1, %ymm0, %ymm0
34; AVX2-NEXT:    retq
35;
36; XOPAVX1-LABEL: var_shift_v4i64:
37; XOPAVX1:       # BB#0:
38; XOPAVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
39; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
40; XOPAVX1-NEXT:    vpshlq %xmm2, %xmm3, %xmm2
41; XOPAVX1-NEXT:    vpshlq %xmm1, %xmm0, %xmm0
42; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
43; XOPAVX1-NEXT:    retq
44;
45; XOPAVX2-LABEL: var_shift_v4i64:
46; XOPAVX2:       # BB#0:
47; XOPAVX2-NEXT:    vpsllvq %ymm1, %ymm0, %ymm0
48; XOPAVX2-NEXT:    retq
49;
50; AVX512-LABEL: var_shift_v4i64:
51; AVX512:       # BB#0:
52; AVX512-NEXT:    vpsllvq %ymm1, %ymm0, %ymm0
53; AVX512-NEXT:    retq
54;
55; AVX512VL-LABEL: var_shift_v4i64:
56; AVX512VL:       # BB#0:
57; AVX512VL-NEXT:    vpsllvq %ymm1, %ymm0, %ymm0
58; AVX512VL-NEXT:    retq
59  %shift = shl <4 x i64> %a, %b
60  ret <4 x i64> %shift
61}
62
63define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
64; AVX1-LABEL: var_shift_v8i32:
65; AVX1:       # BB#0:
66; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
67; AVX1-NEXT:    vpslld $23, %xmm2, %xmm2
68; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
69; AVX1-NEXT:    vpaddd %xmm3, %xmm2, %xmm2
70; AVX1-NEXT:    vcvttps2dq %xmm2, %xmm2
71; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
72; AVX1-NEXT:    vpmulld %xmm4, %xmm2, %xmm2
73; AVX1-NEXT:    vpslld $23, %xmm1, %xmm1
74; AVX1-NEXT:    vpaddd %xmm3, %xmm1, %xmm1
75; AVX1-NEXT:    vcvttps2dq %xmm1, %xmm1
76; AVX1-NEXT:    vpmulld %xmm0, %xmm1, %xmm0
77; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
78; AVX1-NEXT:    retq
79;
80; AVX2-LABEL: var_shift_v8i32:
81; AVX2:       # BB#0:
82; AVX2-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0
83; AVX2-NEXT:    retq
84;
85; XOPAVX1-LABEL: var_shift_v8i32:
86; XOPAVX1:       # BB#0:
87; XOPAVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
88; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
89; XOPAVX1-NEXT:    vpshld %xmm2, %xmm3, %xmm2
90; XOPAVX1-NEXT:    vpshld %xmm1, %xmm0, %xmm0
91; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
92; XOPAVX1-NEXT:    retq
93;
94; XOPAVX2-LABEL: var_shift_v8i32:
95; XOPAVX2:       # BB#0:
96; XOPAVX2-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0
97; XOPAVX2-NEXT:    retq
98;
99; AVX512-LABEL: var_shift_v8i32:
100; AVX512:       # BB#0:
101; AVX512-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0
102; AVX512-NEXT:    retq
103;
104; AVX512VL-LABEL: var_shift_v8i32:
105; AVX512VL:       # BB#0:
106; AVX512VL-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0
107; AVX512VL-NEXT:    retq
108  %shift = shl <8 x i32> %a, %b
109  ret <8 x i32> %shift
110}
111
112define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
113; AVX1-LABEL: var_shift_v16i16:
114; AVX1:       # BB#0:
115; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
116; AVX1-NEXT:    vpsllw $12, %xmm2, %xmm3
117; AVX1-NEXT:    vpsllw $4, %xmm2, %xmm2
118; AVX1-NEXT:    vpor %xmm3, %xmm2, %xmm2
119; AVX1-NEXT:    vpaddw %xmm2, %xmm2, %xmm3
120; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
121; AVX1-NEXT:    vpsllw $8, %xmm4, %xmm5
122; AVX1-NEXT:    vpblendvb %xmm2, %xmm5, %xmm4, %xmm2
123; AVX1-NEXT:    vpsllw $4, %xmm2, %xmm4
124; AVX1-NEXT:    vpblendvb %xmm3, %xmm4, %xmm2, %xmm2
125; AVX1-NEXT:    vpsllw $2, %xmm2, %xmm4
126; AVX1-NEXT:    vpaddw %xmm3, %xmm3, %xmm3
127; AVX1-NEXT:    vpblendvb %xmm3, %xmm4, %xmm2, %xmm2
128; AVX1-NEXT:    vpsllw $1, %xmm2, %xmm4
129; AVX1-NEXT:    vpaddw %xmm3, %xmm3, %xmm3
130; AVX1-NEXT:    vpblendvb %xmm3, %xmm4, %xmm2, %xmm2
131; AVX1-NEXT:    vpsllw $12, %xmm1, %xmm3
132; AVX1-NEXT:    vpsllw $4, %xmm1, %xmm1
133; AVX1-NEXT:    vpor %xmm3, %xmm1, %xmm1
134; AVX1-NEXT:    vpaddw %xmm1, %xmm1, %xmm3
135; AVX1-NEXT:    vpsllw $8, %xmm0, %xmm4
136; AVX1-NEXT:    vpblendvb %xmm1, %xmm4, %xmm0, %xmm0
137; AVX1-NEXT:    vpsllw $4, %xmm0, %xmm1
138; AVX1-NEXT:    vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
139; AVX1-NEXT:    vpsllw $2, %xmm0, %xmm1
140; AVX1-NEXT:    vpaddw %xmm3, %xmm3, %xmm3
141; AVX1-NEXT:    vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
142; AVX1-NEXT:    vpsllw $1, %xmm0, %xmm1
143; AVX1-NEXT:    vpaddw %xmm3, %xmm3, %xmm3
144; AVX1-NEXT:    vpblendvb %xmm3, %xmm1, %xmm0, %xmm0
145; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
146; AVX1-NEXT:    retq
147;
148; AVX2-LABEL: var_shift_v16i16:
149; AVX2:       # BB#0:
150; AVX2-NEXT:    vpxor %ymm2, %ymm2, %ymm2
151; AVX2-NEXT:    vpunpckhwd {{.*#+}} ymm3 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
152; AVX2-NEXT:    vpunpckhwd {{.*#+}} ymm4 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
153; AVX2-NEXT:    vpsllvd %ymm3, %ymm4, %ymm3
154; AVX2-NEXT:    vpsrld $16, %ymm3, %ymm3
155; AVX2-NEXT:    vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
156; AVX2-NEXT:    vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
157; AVX2-NEXT:    vpsllvd %ymm1, %ymm0, %ymm0
158; AVX2-NEXT:    vpsrld $16, %ymm0, %ymm0
159; AVX2-NEXT:    vpackusdw %ymm3, %ymm0, %ymm0
160; AVX2-NEXT:    retq
161;
162; XOPAVX1-LABEL: var_shift_v16i16:
163; XOPAVX1:       # BB#0:
164; XOPAVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
165; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
166; XOPAVX1-NEXT:    vpshlw %xmm2, %xmm3, %xmm2
167; XOPAVX1-NEXT:    vpshlw %xmm1, %xmm0, %xmm0
168; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
169; XOPAVX1-NEXT:    retq
170;
171; XOPAVX2-LABEL: var_shift_v16i16:
172; XOPAVX2:       # BB#0:
173; XOPAVX2-NEXT:    vextracti128 $1, %ymm1, %xmm2
174; XOPAVX2-NEXT:    vextracti128 $1, %ymm0, %xmm3
175; XOPAVX2-NEXT:    vpshlw %xmm2, %xmm3, %xmm2
176; XOPAVX2-NEXT:    vpshlw %xmm1, %xmm0, %xmm0
177; XOPAVX2-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
178; XOPAVX2-NEXT:    retq
179;
180; AVX512DQ-LABEL: var_shift_v16i16:
181; AVX512DQ:       # BB#0:
182; AVX512DQ-NEXT:    vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
183; AVX512DQ-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
184; AVX512DQ-NEXT:    vpsllvd %zmm1, %zmm0, %zmm0
185; AVX512DQ-NEXT:    vpmovdw %zmm0, %ymm0
186; AVX512DQ-NEXT:    retq
187;
188; AVX512BW-LABEL: var_shift_v16i16:
189; AVX512BW:       # BB#0:
190; AVX512BW-NEXT:    # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
191; AVX512BW-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
192; AVX512BW-NEXT:    vpsllvw %zmm1, %zmm0, %zmm0
193; AVX512BW-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
194; AVX512BW-NEXT:    retq
195;
196; AVX512DQVL-LABEL: var_shift_v16i16:
197; AVX512DQVL:       # BB#0:
198; AVX512DQVL-NEXT:    vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
199; AVX512DQVL-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
200; AVX512DQVL-NEXT:    vpsllvd %zmm1, %zmm0, %zmm0
201; AVX512DQVL-NEXT:    vpmovdw %zmm0, %ymm0
202; AVX512DQVL-NEXT:    retq
203;
204; AVX512BWVL-LABEL: var_shift_v16i16:
205; AVX512BWVL:       # BB#0:
206; AVX512BWVL-NEXT:    vpsllvw %ymm1, %ymm0, %ymm0
207; AVX512BWVL-NEXT:    retq
208  %shift = shl <16 x i16> %a, %b
209  ret <16 x i16> %shift
210}
211
212define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
213; AVX1-LABEL: var_shift_v32i8:
214; AVX1:       # BB#0:
215; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
216; AVX1-NEXT:    vpsllw $4, %xmm2, %xmm3
217; AVX1-NEXT:    vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
218; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
219; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm5
220; AVX1-NEXT:    vpsllw $5, %xmm5, %xmm5
221; AVX1-NEXT:    vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
222; AVX1-NEXT:    vpsllw $2, %xmm2, %xmm3
223; AVX1-NEXT:    vmovdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
224; AVX1-NEXT:    vpand %xmm6, %xmm3, %xmm3
225; AVX1-NEXT:    vpaddb %xmm5, %xmm5, %xmm5
226; AVX1-NEXT:    vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
227; AVX1-NEXT:    vpaddb %xmm2, %xmm2, %xmm3
228; AVX1-NEXT:    vpaddb %xmm5, %xmm5, %xmm5
229; AVX1-NEXT:    vpblendvb %xmm5, %xmm3, %xmm2, %xmm2
230; AVX1-NEXT:    vpsllw $4, %xmm0, %xmm3
231; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
232; AVX1-NEXT:    vpsllw $5, %xmm1, %xmm1
233; AVX1-NEXT:    vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
234; AVX1-NEXT:    vpsllw $2, %xmm0, %xmm3
235; AVX1-NEXT:    vpand %xmm6, %xmm3, %xmm3
236; AVX1-NEXT:    vpaddb %xmm1, %xmm1, %xmm1
237; AVX1-NEXT:    vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
238; AVX1-NEXT:    vpaddb %xmm0, %xmm0, %xmm3
239; AVX1-NEXT:    vpaddb %xmm1, %xmm1, %xmm1
240; AVX1-NEXT:    vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
241; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
242; AVX1-NEXT:    retq
243;
244; AVX2-LABEL: var_shift_v32i8:
245; AVX2:       # BB#0:
246; AVX2-NEXT:    vpsllw $5, %ymm1, %ymm1
247; AVX2-NEXT:    vpsllw $4, %ymm0, %ymm2
248; AVX2-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
249; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
250; AVX2-NEXT:    vpsllw $2, %ymm0, %ymm2
251; AVX2-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
252; AVX2-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
253; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
254; AVX2-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
255; AVX2-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
256; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
257; AVX2-NEXT:    retq
258;
259; XOPAVX1-LABEL: var_shift_v32i8:
260; XOPAVX1:       # BB#0:
261; XOPAVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
262; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
263; XOPAVX1-NEXT:    vpshlb %xmm2, %xmm3, %xmm2
264; XOPAVX1-NEXT:    vpshlb %xmm1, %xmm0, %xmm0
265; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
266; XOPAVX1-NEXT:    retq
267;
268; XOPAVX2-LABEL: var_shift_v32i8:
269; XOPAVX2:       # BB#0:
270; XOPAVX2-NEXT:    vextracti128 $1, %ymm1, %xmm2
271; XOPAVX2-NEXT:    vextracti128 $1, %ymm0, %xmm3
272; XOPAVX2-NEXT:    vpshlb %xmm2, %xmm3, %xmm2
273; XOPAVX2-NEXT:    vpshlb %xmm1, %xmm0, %xmm0
274; XOPAVX2-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
275; XOPAVX2-NEXT:    retq
276;
277; AVX512DQ-LABEL: var_shift_v32i8:
278; AVX512DQ:       # BB#0:
279; AVX512DQ-NEXT:    vpsllw $5, %ymm1, %ymm1
280; AVX512DQ-NEXT:    vpsllw $4, %ymm0, %ymm2
281; AVX512DQ-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
282; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
283; AVX512DQ-NEXT:    vpsllw $2, %ymm0, %ymm2
284; AVX512DQ-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
285; AVX512DQ-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
286; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
287; AVX512DQ-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
288; AVX512DQ-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
289; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
290; AVX512DQ-NEXT:    retq
291;
292; AVX512BW-LABEL: var_shift_v32i8:
293; AVX512BW:       # BB#0:
294; AVX512BW-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
295; AVX512BW-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
296; AVX512BW-NEXT:    vpsllvw %zmm1, %zmm0, %zmm0
297; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm0
298; AVX512BW-NEXT:    retq
299;
300; AVX512DQVL-LABEL: var_shift_v32i8:
301; AVX512DQVL:       # BB#0:
302; AVX512DQVL-NEXT:    vpsllw $5, %ymm1, %ymm1
303; AVX512DQVL-NEXT:    vpsllw $4, %ymm0, %ymm2
304; AVX512DQVL-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
305; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
306; AVX512DQVL-NEXT:    vpsllw $2, %ymm0, %ymm2
307; AVX512DQVL-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
308; AVX512DQVL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
309; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
310; AVX512DQVL-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
311; AVX512DQVL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
312; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
313; AVX512DQVL-NEXT:    retq
314;
315; AVX512BWVL-LABEL: var_shift_v32i8:
316; AVX512BWVL:       # BB#0:
317; AVX512BWVL-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
318; AVX512BWVL-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
319; AVX512BWVL-NEXT:    vpsllvw %zmm1, %zmm0, %zmm0
320; AVX512BWVL-NEXT:    vpmovwb %zmm0, %ymm0
321; AVX512BWVL-NEXT:    retq
322  %shift = shl <32 x i8> %a, %b
323  ret <32 x i8> %shift
324}
325
326;
327; Uniform Variable Shifts
328;
329
330define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind {
331; AVX1-LABEL: splatvar_shift_v4i64:
332; AVX1:       # BB#0:
333; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
334; AVX1-NEXT:    vpsllq %xmm1, %xmm2, %xmm2
335; AVX1-NEXT:    vpsllq %xmm1, %xmm0, %xmm0
336; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
337; AVX1-NEXT:    retq
338;
339; AVX2-LABEL: splatvar_shift_v4i64:
340; AVX2:       # BB#0:
341; AVX2-NEXT:    vpsllq %xmm1, %ymm0, %ymm0
342; AVX2-NEXT:    retq
343;
344; XOPAVX1-LABEL: splatvar_shift_v4i64:
345; XOPAVX1:       # BB#0:
346; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
347; XOPAVX1-NEXT:    vpsllq %xmm1, %xmm2, %xmm2
348; XOPAVX1-NEXT:    vpsllq %xmm1, %xmm0, %xmm0
349; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
350; XOPAVX1-NEXT:    retq
351;
352; XOPAVX2-LABEL: splatvar_shift_v4i64:
353; XOPAVX2:       # BB#0:
354; XOPAVX2-NEXT:    vpsllq %xmm1, %ymm0, %ymm0
355; XOPAVX2-NEXT:    retq
356;
357; AVX512-LABEL: splatvar_shift_v4i64:
358; AVX512:       # BB#0:
359; AVX512-NEXT:    vpsllq %xmm1, %ymm0, %ymm0
360; AVX512-NEXT:    retq
361;
362; AVX512VL-LABEL: splatvar_shift_v4i64:
363; AVX512VL:       # BB#0:
364; AVX512VL-NEXT:    vpsllq %xmm1, %ymm0, %ymm0
365; AVX512VL-NEXT:    retq
366  %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
367  %shift = shl <4 x i64> %a, %splat
368  ret <4 x i64> %shift
369}
370
371define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
372; AVX1-LABEL: splatvar_shift_v8i32:
373; AVX1:       # BB#0:
374; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
375; AVX1-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
376; AVX1-NEXT:    vpslld %xmm1, %xmm2, %xmm2
377; AVX1-NEXT:    vpslld %xmm1, %xmm0, %xmm0
378; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
379; AVX1-NEXT:    retq
380;
381; AVX2-LABEL: splatvar_shift_v8i32:
382; AVX2:       # BB#0:
383; AVX2-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
384; AVX2-NEXT:    vpslld %xmm1, %ymm0, %ymm0
385; AVX2-NEXT:    retq
386;
387; XOPAVX1-LABEL: splatvar_shift_v8i32:
388; XOPAVX1:       # BB#0:
389; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
390; XOPAVX1-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
391; XOPAVX1-NEXT:    vpslld %xmm1, %xmm2, %xmm2
392; XOPAVX1-NEXT:    vpslld %xmm1, %xmm0, %xmm0
393; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
394; XOPAVX1-NEXT:    retq
395;
396; XOPAVX2-LABEL: splatvar_shift_v8i32:
397; XOPAVX2:       # BB#0:
398; XOPAVX2-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
399; XOPAVX2-NEXT:    vpslld %xmm1, %ymm0, %ymm0
400; XOPAVX2-NEXT:    retq
401;
402; AVX512-LABEL: splatvar_shift_v8i32:
403; AVX512:       # BB#0:
404; AVX512-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
405; AVX512-NEXT:    vpslld %xmm1, %ymm0, %ymm0
406; AVX512-NEXT:    retq
407;
408; AVX512VL-LABEL: splatvar_shift_v8i32:
409; AVX512VL:       # BB#0:
410; AVX512VL-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
411; AVX512VL-NEXT:    vpslld %xmm1, %ymm0, %ymm0
412; AVX512VL-NEXT:    retq
413  %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer
414  %shift = shl <8 x i32> %a, %splat
415  ret <8 x i32> %shift
416}
417
418define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind {
419; AVX1-LABEL: splatvar_shift_v16i16:
420; AVX1:       # BB#0:
421; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
422; AVX1-NEXT:    vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
423; AVX1-NEXT:    vpsllw %xmm1, %xmm2, %xmm2
424; AVX1-NEXT:    vpsllw %xmm1, %xmm0, %xmm0
425; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
426; AVX1-NEXT:    retq
427;
428; AVX2-LABEL: splatvar_shift_v16i16:
429; AVX2:       # BB#0:
430; AVX2-NEXT:    vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
431; AVX2-NEXT:    vpsllw %xmm1, %ymm0, %ymm0
432; AVX2-NEXT:    retq
433;
434; XOPAVX1-LABEL: splatvar_shift_v16i16:
435; XOPAVX1:       # BB#0:
436; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
437; XOPAVX1-NEXT:    vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
438; XOPAVX1-NEXT:    vpsllw %xmm1, %xmm2, %xmm2
439; XOPAVX1-NEXT:    vpsllw %xmm1, %xmm0, %xmm0
440; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
441; XOPAVX1-NEXT:    retq
442;
443; XOPAVX2-LABEL: splatvar_shift_v16i16:
444; XOPAVX2:       # BB#0:
445; XOPAVX2-NEXT:    vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
446; XOPAVX2-NEXT:    vpsllw %xmm1, %ymm0, %ymm0
447; XOPAVX2-NEXT:    retq
448;
449; AVX512-LABEL: splatvar_shift_v16i16:
450; AVX512:       # BB#0:
451; AVX512-NEXT:    vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
452; AVX512-NEXT:    vpsllw %xmm1, %ymm0, %ymm0
453; AVX512-NEXT:    retq
454;
455; AVX512VL-LABEL: splatvar_shift_v16i16:
456; AVX512VL:       # BB#0:
457; AVX512VL-NEXT:    vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
458; AVX512VL-NEXT:    vpsllw %xmm1, %ymm0, %ymm0
459; AVX512VL-NEXT:    retq
460  %splat = shufflevector <16 x i16> %b, <16 x i16> undef, <16 x i32> zeroinitializer
461  %shift = shl <16 x i16> %a, %splat
462  ret <16 x i16> %shift
463}
464
465define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
466; AVX1-LABEL: splatvar_shift_v32i8:
467; AVX1:       # BB#0:
468; AVX1-NEXT:    vpxor %xmm2, %xmm2, %xmm2
469; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
470; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
471; AVX1-NEXT:    vpsllw $4, %xmm2, %xmm3
472; AVX1-NEXT:    vmovdqa {{.*#+}} xmm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
473; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
474; AVX1-NEXT:    vpsllw $5, %xmm1, %xmm1
475; AVX1-NEXT:    vpblendvb %xmm1, %xmm3, %xmm2, %xmm2
476; AVX1-NEXT:    vpsllw $2, %xmm2, %xmm3
477; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
478; AVX1-NEXT:    vpand %xmm5, %xmm3, %xmm3
479; AVX1-NEXT:    vpaddb %xmm1, %xmm1, %xmm6
480; AVX1-NEXT:    vpblendvb %xmm6, %xmm3, %xmm2, %xmm2
481; AVX1-NEXT:    vpaddb %xmm2, %xmm2, %xmm3
482; AVX1-NEXT:    vpaddb %xmm6, %xmm6, %xmm7
483; AVX1-NEXT:    vpblendvb %xmm7, %xmm3, %xmm2, %xmm2
484; AVX1-NEXT:    vpsllw $4, %xmm0, %xmm3
485; AVX1-NEXT:    vpand %xmm4, %xmm3, %xmm3
486; AVX1-NEXT:    vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
487; AVX1-NEXT:    vpsllw $2, %xmm0, %xmm1
488; AVX1-NEXT:    vpand %xmm5, %xmm1, %xmm1
489; AVX1-NEXT:    vpblendvb %xmm6, %xmm1, %xmm0, %xmm0
490; AVX1-NEXT:    vpaddb %xmm0, %xmm0, %xmm1
491; AVX1-NEXT:    vpblendvb %xmm7, %xmm1, %xmm0, %xmm0
492; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
493; AVX1-NEXT:    retq
494;
495; AVX2-LABEL: splatvar_shift_v32i8:
496; AVX2:       # BB#0:
497; AVX2-NEXT:    vpbroadcastb %xmm1, %ymm1
498; AVX2-NEXT:    vpsllw $4, %ymm0, %ymm2
499; AVX2-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
500; AVX2-NEXT:    vpsllw $5, %ymm1, %ymm1
501; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
502; AVX2-NEXT:    vpsllw $2, %ymm0, %ymm2
503; AVX2-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
504; AVX2-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
505; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
506; AVX2-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
507; AVX2-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
508; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
509; AVX2-NEXT:    retq
510;
511; XOPAVX1-LABEL: splatvar_shift_v32i8:
512; XOPAVX1:       # BB#0:
513; XOPAVX1-NEXT:    vpxor %xmm2, %xmm2, %xmm2
514; XOPAVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
515; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
516; XOPAVX1-NEXT:    vpshlb %xmm1, %xmm2, %xmm2
517; XOPAVX1-NEXT:    vpshlb %xmm1, %xmm0, %xmm0
518; XOPAVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
519; XOPAVX1-NEXT:    retq
520;
521; XOPAVX2-LABEL: splatvar_shift_v32i8:
522; XOPAVX2:       # BB#0:
523; XOPAVX2-NEXT:    vpbroadcastb %xmm1, %ymm1
524; XOPAVX2-NEXT:    vextracti128 $1, %ymm0, %xmm2
525; XOPAVX2-NEXT:    vextracti128 $1, %ymm1, %xmm3
526; XOPAVX2-NEXT:    vpshlb %xmm3, %xmm2, %xmm2
527; XOPAVX2-NEXT:    vpshlb %xmm1, %xmm0, %xmm0
528; XOPAVX2-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
529; XOPAVX2-NEXT:    retq
530;
531; AVX512DQ-LABEL: splatvar_shift_v32i8:
532; AVX512DQ:       # BB#0:
533; AVX512DQ-NEXT:    vpbroadcastb %xmm1, %ymm1
534; AVX512DQ-NEXT:    vpsllw $4, %ymm0, %ymm2
535; AVX512DQ-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
536; AVX512DQ-NEXT:    vpsllw $5, %ymm1, %ymm1
537; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
538; AVX512DQ-NEXT:    vpsllw $2, %ymm0, %ymm2
539; AVX512DQ-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
540; AVX512DQ-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
541; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
542; AVX512DQ-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
543; AVX512DQ-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
544; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
545; AVX512DQ-NEXT:    retq
546;
547; AVX512BW-LABEL: splatvar_shift_v32i8:
548; AVX512BW:       # BB#0:
549; AVX512BW-NEXT:    vpbroadcastb %xmm1, %ymm1
550; AVX512BW-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
551; AVX512BW-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
552; AVX512BW-NEXT:    vpsllvw %zmm1, %zmm0, %zmm0
553; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm0
554; AVX512BW-NEXT:    retq
555;
556; AVX512DQVL-LABEL: splatvar_shift_v32i8:
557; AVX512DQVL:       # BB#0:
558; AVX512DQVL-NEXT:    vpbroadcastb %xmm1, %ymm1
559; AVX512DQVL-NEXT:    vpsllw $4, %ymm0, %ymm2
560; AVX512DQVL-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
561; AVX512DQVL-NEXT:    vpsllw $5, %ymm1, %ymm1
562; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
563; AVX512DQVL-NEXT:    vpsllw $2, %ymm0, %ymm2
564; AVX512DQVL-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
565; AVX512DQVL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
566; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
567; AVX512DQVL-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
568; AVX512DQVL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
569; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
570; AVX512DQVL-NEXT:    retq
571;
572; AVX512BWVL-LABEL: splatvar_shift_v32i8:
573; AVX512BWVL:       # BB#0:
574; AVX512BWVL-NEXT:    vpbroadcastb %xmm1, %ymm1
575; AVX512BWVL-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
576; AVX512BWVL-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
577; AVX512BWVL-NEXT:    vpsllvw %zmm1, %zmm0, %zmm0
578; AVX512BWVL-NEXT:    vpmovwb %zmm0, %ymm0
579; AVX512BWVL-NEXT:    retq
580  %splat = shufflevector <32 x i8> %b, <32 x i8> undef, <32 x i32> zeroinitializer
581  %shift = shl <32 x i8> %a, %splat
582  ret <32 x i8> %shift
583}
584
585;
586; Constant Shifts
587;
588
589define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind {
590; AVX1-LABEL: constant_shift_v4i64:
591; AVX1:       # BB#0:
592; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
593; AVX1-NEXT:    vpsllq $62, %xmm1, %xmm2
594; AVX1-NEXT:    vpsllq $31, %xmm1, %xmm1
595; AVX1-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
596; AVX1-NEXT:    vpsllq $7, %xmm0, %xmm2
597; AVX1-NEXT:    vpsllq $1, %xmm0, %xmm0
598; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
599; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
600; AVX1-NEXT:    retq
601;
602; AVX2-LABEL: constant_shift_v4i64:
603; AVX2:       # BB#0:
604; AVX2-NEXT:    vpsllvq {{.*}}(%rip), %ymm0, %ymm0
605; AVX2-NEXT:    retq
606;
607; XOPAVX1-LABEL: constant_shift_v4i64:
608; XOPAVX1:       # BB#0:
609; XOPAVX1-NEXT:    vpshlq {{.*}}(%rip), %xmm0, %xmm1
610; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
611; XOPAVX1-NEXT:    vpshlq {{.*}}(%rip), %xmm0, %xmm0
612; XOPAVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
613; XOPAVX1-NEXT:    retq
614;
615; XOPAVX2-LABEL: constant_shift_v4i64:
616; XOPAVX2:       # BB#0:
617; XOPAVX2-NEXT:    vpsllvq {{.*}}(%rip), %ymm0, %ymm0
618; XOPAVX2-NEXT:    retq
619;
620; AVX512-LABEL: constant_shift_v4i64:
621; AVX512:       # BB#0:
622; AVX512-NEXT:    vpsllvq {{.*}}(%rip), %ymm0, %ymm0
623; AVX512-NEXT:    retq
624;
625; AVX512VL-LABEL: constant_shift_v4i64:
626; AVX512VL:       # BB#0:
627; AVX512VL-NEXT:    vpsllvq {{.*}}(%rip), %ymm0, %ymm0
628; AVX512VL-NEXT:    retq
629  %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62>
630  ret <4 x i64> %shift
631}
632
633define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind {
634; AVX1-LABEL: constant_shift_v8i32:
635; AVX1:       # BB#0:
636; AVX1-NEXT:    vpmulld {{.*}}(%rip), %xmm0, %xmm1
637; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
638; AVX1-NEXT:    vpmulld {{.*}}(%rip), %xmm0, %xmm0
639; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
640; AVX1-NEXT:    retq
641;
642; AVX2-LABEL: constant_shift_v8i32:
643; AVX2:       # BB#0:
644; AVX2-NEXT:    vpsllvd {{.*}}(%rip), %ymm0, %ymm0
645; AVX2-NEXT:    retq
646;
647; XOPAVX1-LABEL: constant_shift_v8i32:
648; XOPAVX1:       # BB#0:
649; XOPAVX1-NEXT:    vpshld {{.*}}(%rip), %xmm0, %xmm1
650; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
651; XOPAVX1-NEXT:    vpshld {{.*}}(%rip), %xmm0, %xmm0
652; XOPAVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
653; XOPAVX1-NEXT:    retq
654;
655; XOPAVX2-LABEL: constant_shift_v8i32:
656; XOPAVX2:       # BB#0:
657; XOPAVX2-NEXT:    vpsllvd {{.*}}(%rip), %ymm0, %ymm0
658; XOPAVX2-NEXT:    retq
659;
660; AVX512-LABEL: constant_shift_v8i32:
661; AVX512:       # BB#0:
662; AVX512-NEXT:    vpsllvd {{.*}}(%rip), %ymm0, %ymm0
663; AVX512-NEXT:    retq
664;
665; AVX512VL-LABEL: constant_shift_v8i32:
666; AVX512VL:       # BB#0:
667; AVX512VL-NEXT:    vpsllvd {{.*}}(%rip), %ymm0, %ymm0
668; AVX512VL-NEXT:    retq
669  %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>
670  ret <8 x i32> %shift
671}
672
673define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
674; AVX1-LABEL: constant_shift_v16i16:
675; AVX1:       # BB#0:
676; AVX1-NEXT:    vpmullw {{.*}}(%rip), %xmm0, %xmm1
677; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
678; AVX1-NEXT:    vpmullw {{.*}}(%rip), %xmm0, %xmm0
679; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
680; AVX1-NEXT:    retq
681;
682; AVX2-LABEL: constant_shift_v16i16:
683; AVX2:       # BB#0:
684; AVX2-NEXT:    vpmullw {{.*}}(%rip), %ymm0, %ymm0
685; AVX2-NEXT:    retq
686;
687; XOPAVX1-LABEL: constant_shift_v16i16:
688; XOPAVX1:       # BB#0:
689; XOPAVX1-NEXT:    vpshlw {{.*}}(%rip), %xmm0, %xmm1
690; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
691; XOPAVX1-NEXT:    vpshlw {{.*}}(%rip), %xmm0, %xmm0
692; XOPAVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
693; XOPAVX1-NEXT:    retq
694;
695; XOPAVX2-LABEL: constant_shift_v16i16:
696; XOPAVX2:       # BB#0:
697; XOPAVX2-NEXT:    vpmullw {{.*}}(%rip), %ymm0, %ymm0
698; XOPAVX2-NEXT:    retq
699;
700; AVX512DQ-LABEL: constant_shift_v16i16:
701; AVX512DQ:       # BB#0:
702; AVX512DQ-NEXT:    vpmullw {{.*}}(%rip), %ymm0, %ymm0
703; AVX512DQ-NEXT:    retq
704;
705; AVX512BW-LABEL: constant_shift_v16i16:
706; AVX512BW:       # BB#0:
707; AVX512BW-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
708; AVX512BW-NEXT:    vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
709; AVX512BW-NEXT:    vpsllvw %zmm1, %zmm0, %zmm0
710; AVX512BW-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
711; AVX512BW-NEXT:    retq
712;
713; AVX512DQVL-LABEL: constant_shift_v16i16:
714; AVX512DQVL:       # BB#0:
715; AVX512DQVL-NEXT:    vpmullw {{.*}}(%rip), %ymm0, %ymm0
716; AVX512DQVL-NEXT:    retq
717;
718; AVX512BWVL-LABEL: constant_shift_v16i16:
719; AVX512BWVL:       # BB#0:
720; AVX512BWVL-NEXT:    vpsllvw {{.*}}(%rip), %ymm0, %ymm0
721; AVX512BWVL-NEXT:    retq
722  %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
723  ret <16 x i16> %shift
724}
725
726define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
727; AVX1-LABEL: constant_shift_v32i8:
728; AVX1:       # BB#0:
729; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
730; AVX1-NEXT:    vpsllw $4, %xmm1, %xmm2
731; AVX1-NEXT:    vmovdqa {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
732; AVX1-NEXT:    vpand %xmm3, %xmm2, %xmm2
733; AVX1-NEXT:    vmovdqa {{.*#+}} xmm4 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
734; AVX1-NEXT:    vpsllw $5, %xmm4, %xmm4
735; AVX1-NEXT:    vpblendvb %xmm4, %xmm2, %xmm1, %xmm1
736; AVX1-NEXT:    vpsllw $2, %xmm1, %xmm2
737; AVX1-NEXT:    vmovdqa {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
738; AVX1-NEXT:    vpand %xmm5, %xmm2, %xmm2
739; AVX1-NEXT:    vpaddb %xmm4, %xmm4, %xmm6
740; AVX1-NEXT:    vpblendvb %xmm6, %xmm2, %xmm1, %xmm1
741; AVX1-NEXT:    vpaddb %xmm1, %xmm1, %xmm2
742; AVX1-NEXT:    vpaddb %xmm6, %xmm6, %xmm7
743; AVX1-NEXT:    vpblendvb %xmm7, %xmm2, %xmm1, %xmm1
744; AVX1-NEXT:    vpsllw $4, %xmm0, %xmm2
745; AVX1-NEXT:    vpand %xmm3, %xmm2, %xmm2
746; AVX1-NEXT:    vpblendvb %xmm4, %xmm2, %xmm0, %xmm0
747; AVX1-NEXT:    vpsllw $2, %xmm0, %xmm2
748; AVX1-NEXT:    vpand %xmm5, %xmm2, %xmm2
749; AVX1-NEXT:    vpblendvb %xmm6, %xmm2, %xmm0, %xmm0
750; AVX1-NEXT:    vpaddb %xmm0, %xmm0, %xmm2
751; AVX1-NEXT:    vpblendvb %xmm7, %xmm2, %xmm0, %xmm0
752; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
753; AVX1-NEXT:    retq
754;
755; AVX2-LABEL: constant_shift_v32i8:
756; AVX2:       # BB#0:
757; AVX2-NEXT:    vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
758; AVX2-NEXT:    vpsllw $5, %ymm1, %ymm1
759; AVX2-NEXT:    vpsllw $4, %ymm0, %ymm2
760; AVX2-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
761; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
762; AVX2-NEXT:    vpsllw $2, %ymm0, %ymm2
763; AVX2-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
764; AVX2-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
765; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
766; AVX2-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
767; AVX2-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
768; AVX2-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
769; AVX2-NEXT:    retq
770;
771; XOPAVX1-LABEL: constant_shift_v32i8:
772; XOPAVX1:       # BB#0:
773; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
774; XOPAVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
775; XOPAVX1-NEXT:    vpshlb %xmm2, %xmm1, %xmm1
776; XOPAVX1-NEXT:    vpshlb %xmm2, %xmm0, %xmm0
777; XOPAVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
778; XOPAVX1-NEXT:    retq
779;
780; XOPAVX2-LABEL: constant_shift_v32i8:
781; XOPAVX2:       # BB#0:
782; XOPAVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
783; XOPAVX2-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
784; XOPAVX2-NEXT:    vpshlb %xmm2, %xmm1, %xmm1
785; XOPAVX2-NEXT:    vpshlb %xmm2, %xmm0, %xmm0
786; XOPAVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
787; XOPAVX2-NEXT:    retq
788;
789; AVX512DQ-LABEL: constant_shift_v32i8:
790; AVX512DQ:       # BB#0:
791; AVX512DQ-NEXT:    vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
792; AVX512DQ-NEXT:    vpsllw $5, %ymm1, %ymm1
793; AVX512DQ-NEXT:    vpsllw $4, %ymm0, %ymm2
794; AVX512DQ-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
795; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
796; AVX512DQ-NEXT:    vpsllw $2, %ymm0, %ymm2
797; AVX512DQ-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
798; AVX512DQ-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
799; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
800; AVX512DQ-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
801; AVX512DQ-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
802; AVX512DQ-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
803; AVX512DQ-NEXT:    retq
804;
805; AVX512BW-LABEL: constant_shift_v32i8:
806; AVX512BW:       # BB#0:
807; AVX512BW-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
808; AVX512BW-NEXT:    vpsllvw {{.*}}(%rip), %zmm0, %zmm0
809; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm0
810; AVX512BW-NEXT:    retq
811;
812; AVX512DQVL-LABEL: constant_shift_v32i8:
813; AVX512DQVL:       # BB#0:
814; AVX512DQVL-NEXT:    vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0,0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
815; AVX512DQVL-NEXT:    vpsllw $5, %ymm1, %ymm1
816; AVX512DQVL-NEXT:    vpsllw $4, %ymm0, %ymm2
817; AVX512DQVL-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
818; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
819; AVX512DQVL-NEXT:    vpsllw $2, %ymm0, %ymm2
820; AVX512DQVL-NEXT:    vpand {{.*}}(%rip), %ymm2, %ymm2
821; AVX512DQVL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
822; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
823; AVX512DQVL-NEXT:    vpaddb %ymm0, %ymm0, %ymm2
824; AVX512DQVL-NEXT:    vpaddb %ymm1, %ymm1, %ymm1
825; AVX512DQVL-NEXT:    vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
826; AVX512DQVL-NEXT:    retq
827;
828; AVX512BWVL-LABEL: constant_shift_v32i8:
829; AVX512BWVL:       # BB#0:
830; AVX512BWVL-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
831; AVX512BWVL-NEXT:    vpsllvw {{.*}}(%rip), %zmm0, %zmm0
832; AVX512BWVL-NEXT:    vpmovwb %zmm0, %ymm0
833; AVX512BWVL-NEXT:    retq
834  %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
835  ret <32 x i8> %shift
836}
837
838;
839; Uniform Constant Shifts
840;
841
842define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind {
843; AVX1-LABEL: splatconstant_shift_v4i64:
844; AVX1:       # BB#0:
845; AVX1-NEXT:    vpsllq $7, %xmm0, %xmm1
846; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
847; AVX1-NEXT:    vpsllq $7, %xmm0, %xmm0
848; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
849; AVX1-NEXT:    retq
850;
851; AVX2-LABEL: splatconstant_shift_v4i64:
852; AVX2:       # BB#0:
853; AVX2-NEXT:    vpsllq $7, %ymm0, %ymm0
854; AVX2-NEXT:    retq
855;
856; XOPAVX1-LABEL: splatconstant_shift_v4i64:
857; XOPAVX1:       # BB#0:
858; XOPAVX1-NEXT:    vpsllq $7, %xmm0, %xmm1
859; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
860; XOPAVX1-NEXT:    vpsllq $7, %xmm0, %xmm0
861; XOPAVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
862; XOPAVX1-NEXT:    retq
863;
864; XOPAVX2-LABEL: splatconstant_shift_v4i64:
865; XOPAVX2:       # BB#0:
866; XOPAVX2-NEXT:    vpsllq $7, %ymm0, %ymm0
867; XOPAVX2-NEXT:    retq
868;
869; AVX512-LABEL: splatconstant_shift_v4i64:
870; AVX512:       # BB#0:
871; AVX512-NEXT:    vpsllq $7, %ymm0, %ymm0
872; AVX512-NEXT:    retq
873;
874; AVX512VL-LABEL: splatconstant_shift_v4i64:
875; AVX512VL:       # BB#0:
876; AVX512VL-NEXT:    vpsllq $7, %ymm0, %ymm0
877; AVX512VL-NEXT:    retq
878  %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
879  ret <4 x i64> %shift
880}
881
882define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) nounwind {
883; AVX1-LABEL: splatconstant_shift_v8i32:
884; AVX1:       # BB#0:
885; AVX1-NEXT:    vpslld $5, %xmm0, %xmm1
886; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
887; AVX1-NEXT:    vpslld $5, %xmm0, %xmm0
888; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
889; AVX1-NEXT:    retq
890;
891; AVX2-LABEL: splatconstant_shift_v8i32:
892; AVX2:       # BB#0:
893; AVX2-NEXT:    vpslld $5, %ymm0, %ymm0
894; AVX2-NEXT:    retq
895;
896; XOPAVX1-LABEL: splatconstant_shift_v8i32:
897; XOPAVX1:       # BB#0:
898; XOPAVX1-NEXT:    vpslld $5, %xmm0, %xmm1
899; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
900; XOPAVX1-NEXT:    vpslld $5, %xmm0, %xmm0
901; XOPAVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
902; XOPAVX1-NEXT:    retq
903;
904; XOPAVX2-LABEL: splatconstant_shift_v8i32:
905; XOPAVX2:       # BB#0:
906; XOPAVX2-NEXT:    vpslld $5, %ymm0, %ymm0
907; XOPAVX2-NEXT:    retq
908;
909; AVX512-LABEL: splatconstant_shift_v8i32:
910; AVX512:       # BB#0:
911; AVX512-NEXT:    vpslld $5, %ymm0, %ymm0
912; AVX512-NEXT:    retq
913;
914; AVX512VL-LABEL: splatconstant_shift_v8i32:
915; AVX512VL:       # BB#0:
916; AVX512VL-NEXT:    vpslld $5, %ymm0, %ymm0
917; AVX512VL-NEXT:    retq
918  %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
919  ret <8 x i32> %shift
920}
921
922define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) nounwind {
923; AVX1-LABEL: splatconstant_shift_v16i16:
924; AVX1:       # BB#0:
925; AVX1-NEXT:    vpsllw $3, %xmm0, %xmm1
926; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
927; AVX1-NEXT:    vpsllw $3, %xmm0, %xmm0
928; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
929; AVX1-NEXT:    retq
930;
931; AVX2-LABEL: splatconstant_shift_v16i16:
932; AVX2:       # BB#0:
933; AVX2-NEXT:    vpsllw $3, %ymm0, %ymm0
934; AVX2-NEXT:    retq
935;
936; XOPAVX1-LABEL: splatconstant_shift_v16i16:
937; XOPAVX1:       # BB#0:
938; XOPAVX1-NEXT:    vpsllw $3, %xmm0, %xmm1
939; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
940; XOPAVX1-NEXT:    vpsllw $3, %xmm0, %xmm0
941; XOPAVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
942; XOPAVX1-NEXT:    retq
943;
944; XOPAVX2-LABEL: splatconstant_shift_v16i16:
945; XOPAVX2:       # BB#0:
946; XOPAVX2-NEXT:    vpsllw $3, %ymm0, %ymm0
947; XOPAVX2-NEXT:    retq
948;
949; AVX512-LABEL: splatconstant_shift_v16i16:
950; AVX512:       # BB#0:
951; AVX512-NEXT:    vpsllw $3, %ymm0, %ymm0
952; AVX512-NEXT:    retq
953;
954; AVX512VL-LABEL: splatconstant_shift_v16i16:
955; AVX512VL:       # BB#0:
956; AVX512VL-NEXT:    vpsllw $3, %ymm0, %ymm0
957; AVX512VL-NEXT:    retq
958  %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
959  ret <16 x i16> %shift
960}
961
962define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind {
963; AVX1-LABEL: splatconstant_shift_v32i8:
964; AVX1:       # BB#0:
965; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
966; AVX1-NEXT:    vpsllw $3, %xmm1, %xmm1
967; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [248,248,248,248,248,248,248,248,248,248,248,248,248,248,248,248]
968; AVX1-NEXT:    vpand %xmm2, %xmm1, %xmm1
969; AVX1-NEXT:    vpsllw $3, %xmm0, %xmm0
970; AVX1-NEXT:    vpand %xmm2, %xmm0, %xmm0
971; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
972; AVX1-NEXT:    retq
973;
974; AVX2-LABEL: splatconstant_shift_v32i8:
975; AVX2:       # BB#0:
976; AVX2-NEXT:    vpsllw $3, %ymm0, %ymm0
977; AVX2-NEXT:    vpand {{.*}}(%rip), %ymm0, %ymm0
978; AVX2-NEXT:    retq
979;
980; XOPAVX1-LABEL: splatconstant_shift_v32i8:
981; XOPAVX1:       # BB#0:
982; XOPAVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
983; XOPAVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3]
984; XOPAVX1-NEXT:    vpshlb %xmm2, %xmm1, %xmm1
985; XOPAVX1-NEXT:    vpshlb %xmm2, %xmm0, %xmm0
986; XOPAVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
987; XOPAVX1-NEXT:    retq
988;
989; XOPAVX2-LABEL: splatconstant_shift_v32i8:
990; XOPAVX2:       # BB#0:
991; XOPAVX2-NEXT:    vpsllw $3, %ymm0, %ymm0
992; XOPAVX2-NEXT:    vpand {{.*}}(%rip), %ymm0, %ymm0
993; XOPAVX2-NEXT:    retq
994;
995; AVX512-LABEL: splatconstant_shift_v32i8:
996; AVX512:       # BB#0:
997; AVX512-NEXT:    vpsllw $3, %ymm0, %ymm0
998; AVX512-NEXT:    vpand {{.*}}(%rip), %ymm0, %ymm0
999; AVX512-NEXT:    retq
1000;
1001; AVX512VL-LABEL: splatconstant_shift_v32i8:
1002; AVX512VL:       # BB#0:
1003; AVX512VL-NEXT:    vpsllw $3, %ymm0, %ymm0
1004; AVX512VL-NEXT:    vpand {{.*}}(%rip), %ymm0, %ymm0
1005; AVX512VL-NEXT:    retq
1006  %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
1007  ret <32 x i8> %shift
1008}
1009