1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
4
5define <8 x i32> @zext_and_v8i32(<8 x i16> %x, <8 x i16> %y) {
6; SSE2-LABEL: zext_and_v8i32:
7; SSE2:       # %bb.0:
8; SSE2-NEXT:    pand %xmm0, %xmm1
9; SSE2-NEXT:    pxor %xmm2, %xmm2
10; SSE2-NEXT:    movdqa %xmm1, %xmm0
11; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
12; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
13; SSE2-NEXT:    retq
14;
15; AVX2-LABEL: zext_and_v8i32:
16; AVX2:       # %bb.0:
17; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
18; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
19; AVX2-NEXT:    retq
20  %xz = zext <8 x i16> %x to <8 x i32>
21  %yz = zext <8 x i16> %y to <8 x i32>
22  %r = and <8 x i32> %xz, %yz
23  ret <8 x i32> %r
24}
25
26define <8 x i32> @zext_or_v8i32(<8 x i16> %x, <8 x i16> %y) {
27; SSE2-LABEL: zext_or_v8i32:
28; SSE2:       # %bb.0:
29; SSE2-NEXT:    por %xmm0, %xmm1
30; SSE2-NEXT:    pxor %xmm2, %xmm2
31; SSE2-NEXT:    movdqa %xmm1, %xmm0
32; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
33; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
34; SSE2-NEXT:    retq
35;
36; AVX2-LABEL: zext_or_v8i32:
37; AVX2:       # %bb.0:
38; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
39; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
40; AVX2-NEXT:    retq
41  %xz = zext <8 x i16> %x to <8 x i32>
42  %yz = zext <8 x i16> %y to <8 x i32>
43  %r = or <8 x i32> %xz, %yz
44  ret <8 x i32> %r
45}
46
47define <8 x i32> @zext_xor_v8i32(<8 x i16> %x, <8 x i16> %y) {
48; SSE2-LABEL: zext_xor_v8i32:
49; SSE2:       # %bb.0:
50; SSE2-NEXT:    pxor %xmm0, %xmm1
51; SSE2-NEXT:    pxor %xmm2, %xmm2
52; SSE2-NEXT:    movdqa %xmm1, %xmm0
53; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
54; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
55; SSE2-NEXT:    retq
56;
57; AVX2-LABEL: zext_xor_v8i32:
58; AVX2:       # %bb.0:
59; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
60; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
61; AVX2-NEXT:    retq
62  %xz = zext <8 x i16> %x to <8 x i32>
63  %yz = zext <8 x i16> %y to <8 x i32>
64  %r = xor <8 x i32> %xz, %yz
65  ret <8 x i32> %r
66}
67
68define <8 x i32> @sext_and_v8i32(<8 x i16> %x, <8 x i16> %y) {
69; SSE2-LABEL: sext_and_v8i32:
70; SSE2:       # %bb.0:
71; SSE2-NEXT:    pand %xmm1, %xmm0
72; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
73; SSE2-NEXT:    psrad $16, %xmm2
74; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
75; SSE2-NEXT:    psrad $16, %xmm1
76; SSE2-NEXT:    movdqa %xmm2, %xmm0
77; SSE2-NEXT:    retq
78;
79; AVX2-LABEL: sext_and_v8i32:
80; AVX2:       # %bb.0:
81; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
82; AVX2-NEXT:    vpmovsxwd %xmm0, %ymm0
83; AVX2-NEXT:    retq
84  %xs = sext <8 x i16> %x to <8 x i32>
85  %ys = sext <8 x i16> %y to <8 x i32>
86  %r = and <8 x i32> %xs, %ys
87  ret <8 x i32> %r
88}
89
90define <8 x i32> @sext_or_v8i32(<8 x i16> %x, <8 x i16> %y) {
91; SSE2-LABEL: sext_or_v8i32:
92; SSE2:       # %bb.0:
93; SSE2-NEXT:    por %xmm1, %xmm0
94; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
95; SSE2-NEXT:    psrad $16, %xmm2
96; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
97; SSE2-NEXT:    psrad $16, %xmm1
98; SSE2-NEXT:    movdqa %xmm2, %xmm0
99; SSE2-NEXT:    retq
100;
101; AVX2-LABEL: sext_or_v8i32:
102; AVX2:       # %bb.0:
103; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
104; AVX2-NEXT:    vpmovsxwd %xmm0, %ymm0
105; AVX2-NEXT:    retq
106  %xs = sext <8 x i16> %x to <8 x i32>
107  %ys = sext <8 x i16> %y to <8 x i32>
108  %r = or <8 x i32> %xs, %ys
109  ret <8 x i32> %r
110}
111
112define <8 x i32> @sext_xor_v8i32(<8 x i16> %x, <8 x i16> %y) {
113; SSE2-LABEL: sext_xor_v8i32:
114; SSE2:       # %bb.0:
115; SSE2-NEXT:    pxor %xmm1, %xmm0
116; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
117; SSE2-NEXT:    psrad $16, %xmm2
118; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
119; SSE2-NEXT:    psrad $16, %xmm1
120; SSE2-NEXT:    movdqa %xmm2, %xmm0
121; SSE2-NEXT:    retq
122;
123; AVX2-LABEL: sext_xor_v8i32:
124; AVX2:       # %bb.0:
125; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
126; AVX2-NEXT:    vpmovsxwd %xmm0, %ymm0
127; AVX2-NEXT:    retq
128  %xs = sext <8 x i16> %x to <8 x i32>
129  %ys = sext <8 x i16> %y to <8 x i32>
130  %r = xor <8 x i32> %xs, %ys
131  ret <8 x i32> %r
132}
133
134define <8 x i16> @zext_and_v8i16(<8 x i8> %x, <8 x i8> %y) {
135; SSE2-LABEL: zext_and_v8i16:
136; SSE2:       # %bb.0:
137; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
138; SSE2-NEXT:    pxor %xmm2, %xmm2
139; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
140; SSE2-NEXT:    pand %xmm1, %xmm0
141; SSE2-NEXT:    retq
142;
143; AVX2-LABEL: zext_and_v8i16:
144; AVX2:       # %bb.0:
145; AVX2-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
146; AVX2-NEXT:    vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
147; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
148; AVX2-NEXT:    retq
149  %xz = zext <8 x i8> %x to <8 x i16>
150  %yz = zext <8 x i8> %y to <8 x i16>
151  %r = and <8 x i16> %xz, %yz
152  ret <8 x i16> %r
153}
154
155define <8 x i16> @zext_or_v8i16(<8 x i8> %x, <8 x i8> %y) {
156; SSE2-LABEL: zext_or_v8i16:
157; SSE2:       # %bb.0:
158; SSE2-NEXT:    pxor %xmm2, %xmm2
159; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
160; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
161; SSE2-NEXT:    por %xmm1, %xmm0
162; SSE2-NEXT:    retq
163;
164; AVX2-LABEL: zext_or_v8i16:
165; AVX2:       # %bb.0:
166; AVX2-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
167; AVX2-NEXT:    vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
168; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
169; AVX2-NEXT:    retq
170  %xz = zext <8 x i8> %x to <8 x i16>
171  %yz = zext <8 x i8> %y to <8 x i16>
172  %r = or <8 x i16> %xz, %yz
173  ret <8 x i16> %r
174}
175
176define <8 x i16> @zext_xor_v8i16(<8 x i8> %x, <8 x i8> %y) {
177; SSE2-LABEL: zext_xor_v8i16:
178; SSE2:       # %bb.0:
179; SSE2-NEXT:    pxor %xmm2, %xmm2
180; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
181; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
182; SSE2-NEXT:    pxor %xmm1, %xmm0
183; SSE2-NEXT:    retq
184;
185; AVX2-LABEL: zext_xor_v8i16:
186; AVX2:       # %bb.0:
187; AVX2-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
188; AVX2-NEXT:    vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
189; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
190; AVX2-NEXT:    retq
191  %xz = zext <8 x i8> %x to <8 x i16>
192  %yz = zext <8 x i8> %y to <8 x i16>
193  %r = xor <8 x i16> %xz, %yz
194  ret <8 x i16> %r
195}
196
197define <8 x i16> @sext_and_v8i16(<8 x i8> %x, <8 x i8> %y) {
198; SSE2-LABEL: sext_and_v8i16:
199; SSE2:       # %bb.0:
200; SSE2-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
201; SSE2-NEXT:    psraw $8, %xmm2
202; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
203; SSE2-NEXT:    psraw $8, %xmm0
204; SSE2-NEXT:    pand %xmm2, %xmm0
205; SSE2-NEXT:    retq
206;
207; AVX2-LABEL: sext_and_v8i16:
208; AVX2:       # %bb.0:
209; AVX2-NEXT:    vpmovsxbw %xmm0, %xmm0
210; AVX2-NEXT:    vpmovsxbw %xmm1, %xmm1
211; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
212; AVX2-NEXT:    retq
213  %xs = sext <8 x i8> %x to <8 x i16>
214  %ys = sext <8 x i8> %y to <8 x i16>
215  %r = and <8 x i16> %xs, %ys
216  ret <8 x i16> %r
217}
218
219define <8 x i16> @sext_or_v8i16(<8 x i8> %x, <8 x i8> %y) {
220; SSE2-LABEL: sext_or_v8i16:
221; SSE2:       # %bb.0:
222; SSE2-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
223; SSE2-NEXT:    psraw $8, %xmm2
224; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
225; SSE2-NEXT:    psraw $8, %xmm0
226; SSE2-NEXT:    por %xmm2, %xmm0
227; SSE2-NEXT:    retq
228;
229; AVX2-LABEL: sext_or_v8i16:
230; AVX2:       # %bb.0:
231; AVX2-NEXT:    vpmovsxbw %xmm0, %xmm0
232; AVX2-NEXT:    vpmovsxbw %xmm1, %xmm1
233; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
234; AVX2-NEXT:    retq
235  %xs = sext <8 x i8> %x to <8 x i16>
236  %ys = sext <8 x i8> %y to <8 x i16>
237  %r = or <8 x i16> %xs, %ys
238  ret <8 x i16> %r
239}
240
241define <8 x i16> @sext_xor_v8i16(<8 x i8> %x, <8 x i8> %y) {
242; SSE2-LABEL: sext_xor_v8i16:
243; SSE2:       # %bb.0:
244; SSE2-NEXT:    punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
245; SSE2-NEXT:    psraw $8, %xmm2
246; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
247; SSE2-NEXT:    psraw $8, %xmm0
248; SSE2-NEXT:    pxor %xmm2, %xmm0
249; SSE2-NEXT:    retq
250;
251; AVX2-LABEL: sext_xor_v8i16:
252; AVX2:       # %bb.0:
253; AVX2-NEXT:    vpmovsxbw %xmm0, %xmm0
254; AVX2-NEXT:    vpmovsxbw %xmm1, %xmm1
255; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
256; AVX2-NEXT:    retq
257  %xs = sext <8 x i8> %x to <8 x i16>
258  %ys = sext <8 x i8> %y to <8 x i16>
259  %r = xor <8 x i16> %xs, %ys
260  ret <8 x i16> %r
261}
262
263define <8 x i32> @bool_zext_and(<8 x i1> %x, <8 x i1> %y) {
264; SSE2-LABEL: bool_zext_and:
265; SSE2:       # %bb.0:
266; SSE2-NEXT:    movdqa %xmm0, %xmm3
267; SSE2-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4,4,5,5,6,6,7,7]
268; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
269; SSE2-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
270; SSE2-NEXT:    pxor %xmm4, %xmm4
271; SSE2-NEXT:    movdqa %xmm1, %xmm2
272; SSE2-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
273; SSE2-NEXT:    pand %xmm3, %xmm2
274; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
275; SSE2-NEXT:    pand %xmm1, %xmm0
276; SSE2-NEXT:    movdqa %xmm2, %xmm1
277; SSE2-NEXT:    retq
278;
279; AVX2-LABEL: bool_zext_and:
280; AVX2:       # %bb.0:
281; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
282; AVX2-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
283; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
284; AVX2-NEXT:    vpand %ymm1, %ymm0, %ymm0
285; AVX2-NEXT:    retq
286  %xz = zext <8 x i1> %x to <8 x i32>
287  %yz = zext <8 x i1> %y to <8 x i32>
288  %r = and <8 x i32> %xz, %yz
289  ret <8 x i32> %r
290}
291
292define <8 x i32> @bool_zext_or(<8 x i1> %x, <8 x i1> %y) {
293; SSE2-LABEL: bool_zext_or:
294; SSE2:       # %bb.0:
295; SSE2-NEXT:    por %xmm0, %xmm1
296; SSE2-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
297; SSE2-NEXT:    pxor %xmm2, %xmm2
298; SSE2-NEXT:    movdqa %xmm1, %xmm0
299; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
300; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
301; SSE2-NEXT:    retq
302;
303; AVX2-LABEL: bool_zext_or:
304; AVX2:       # %bb.0:
305; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
306; AVX2-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
307; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
308; AVX2-NEXT:    retq
309  %xz = zext <8 x i1> %x to <8 x i32>
310  %yz = zext <8 x i1> %y to <8 x i32>
311  %r = or <8 x i32> %xz, %yz
312  ret <8 x i32> %r
313}
314
315define <8 x i32> @bool_zext_xor(<8 x i1> %x, <8 x i1> %y) {
316; SSE2-LABEL: bool_zext_xor:
317; SSE2:       # %bb.0:
318; SSE2-NEXT:    pxor %xmm0, %xmm1
319; SSE2-NEXT:    pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
320; SSE2-NEXT:    pxor %xmm2, %xmm2
321; SSE2-NEXT:    movdqa %xmm1, %xmm0
322; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
323; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
324; SSE2-NEXT:    retq
325;
326; AVX2-LABEL: bool_zext_xor:
327; AVX2:       # %bb.0:
328; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
329; AVX2-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
330; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
331; AVX2-NEXT:    retq
332  %xz = zext <8 x i1> %x to <8 x i32>
333  %yz = zext <8 x i1> %y to <8 x i32>
334  %r = xor <8 x i32> %xz, %yz
335  ret <8 x i32> %r
336}
337
338define <8 x i32> @bool_sext_and(<8 x i1> %x, <8 x i1> %y) {
339; SSE2-LABEL: bool_sext_and:
340; SSE2:       # %bb.0:
341; SSE2-NEXT:    movdqa %xmm1, %xmm2
342; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
343; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
344; SSE2-NEXT:    movdqa %xmm0, %xmm3
345; SSE2-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3]
346; SSE2-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
347; SSE2-NEXT:    pslld $31, %xmm0
348; SSE2-NEXT:    psrad $31, %xmm0
349; SSE2-NEXT:    pslld $31, %xmm3
350; SSE2-NEXT:    psrad $31, %xmm3
351; SSE2-NEXT:    pslld $31, %xmm1
352; SSE2-NEXT:    psrad $31, %xmm1
353; SSE2-NEXT:    pand %xmm0, %xmm1
354; SSE2-NEXT:    pslld $31, %xmm2
355; SSE2-NEXT:    psrad $31, %xmm2
356; SSE2-NEXT:    pand %xmm3, %xmm2
357; SSE2-NEXT:    movdqa %xmm2, %xmm0
358; SSE2-NEXT:    retq
359;
360; AVX2-LABEL: bool_sext_and:
361; AVX2:       # %bb.0:
362; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
363; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
364; AVX2-NEXT:    vpslld $31, %ymm0, %ymm0
365; AVX2-NEXT:    vpsrad $31, %ymm0, %ymm0
366; AVX2-NEXT:    vpslld $31, %ymm1, %ymm1
367; AVX2-NEXT:    vpsrad $31, %ymm1, %ymm1
368; AVX2-NEXT:    vpand %ymm1, %ymm0, %ymm0
369; AVX2-NEXT:    retq
370  %xs = sext <8 x i1> %x to <8 x i32>
371  %ys = sext <8 x i1> %y to <8 x i32>
372  %r = and <8 x i32> %xs, %ys
373  ret <8 x i32> %r
374}
375
376define <8 x i32> @bool_sext_or(<8 x i1> %x, <8 x i1> %y) {
377; SSE2-LABEL: bool_sext_or:
378; SSE2:       # %bb.0:
379; SSE2-NEXT:    movdqa %xmm1, %xmm2
380; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
381; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
382; SSE2-NEXT:    movdqa %xmm0, %xmm3
383; SSE2-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3]
384; SSE2-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
385; SSE2-NEXT:    pslld $31, %xmm0
386; SSE2-NEXT:    psrad $31, %xmm0
387; SSE2-NEXT:    pslld $31, %xmm3
388; SSE2-NEXT:    psrad $31, %xmm3
389; SSE2-NEXT:    pslld $31, %xmm1
390; SSE2-NEXT:    psrad $31, %xmm1
391; SSE2-NEXT:    por %xmm0, %xmm1
392; SSE2-NEXT:    pslld $31, %xmm2
393; SSE2-NEXT:    psrad $31, %xmm2
394; SSE2-NEXT:    por %xmm3, %xmm2
395; SSE2-NEXT:    movdqa %xmm2, %xmm0
396; SSE2-NEXT:    retq
397;
398; AVX2-LABEL: bool_sext_or:
399; AVX2:       # %bb.0:
400; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
401; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
402; AVX2-NEXT:    vpslld $31, %ymm0, %ymm0
403; AVX2-NEXT:    vpsrad $31, %ymm0, %ymm0
404; AVX2-NEXT:    vpslld $31, %ymm1, %ymm1
405; AVX2-NEXT:    vpsrad $31, %ymm1, %ymm1
406; AVX2-NEXT:    vpor %ymm1, %ymm0, %ymm0
407; AVX2-NEXT:    retq
408  %xs = sext <8 x i1> %x to <8 x i32>
409  %ys = sext <8 x i1> %y to <8 x i32>
410  %r = or <8 x i32> %xs, %ys
411  ret <8 x i32> %r
412}
413
414define <8 x i32> @bool_sext_xor(<8 x i1> %x, <8 x i1> %y) {
415; SSE2-LABEL: bool_sext_xor:
416; SSE2:       # %bb.0:
417; SSE2-NEXT:    movdqa %xmm1, %xmm2
418; SSE2-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3]
419; SSE2-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
420; SSE2-NEXT:    movdqa %xmm0, %xmm3
421; SSE2-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0,0,1,1,2,2,3,3]
422; SSE2-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
423; SSE2-NEXT:    pslld $31, %xmm0
424; SSE2-NEXT:    psrad $31, %xmm0
425; SSE2-NEXT:    pslld $31, %xmm3
426; SSE2-NEXT:    psrad $31, %xmm3
427; SSE2-NEXT:    pslld $31, %xmm1
428; SSE2-NEXT:    psrad $31, %xmm1
429; SSE2-NEXT:    pxor %xmm0, %xmm1
430; SSE2-NEXT:    pslld $31, %xmm2
431; SSE2-NEXT:    psrad $31, %xmm2
432; SSE2-NEXT:    pxor %xmm3, %xmm2
433; SSE2-NEXT:    movdqa %xmm2, %xmm0
434; SSE2-NEXT:    retq
435;
436; AVX2-LABEL: bool_sext_xor:
437; AVX2:       # %bb.0:
438; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
439; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
440; AVX2-NEXT:    vpslld $31, %ymm0, %ymm0
441; AVX2-NEXT:    vpsrad $31, %ymm0, %ymm0
442; AVX2-NEXT:    vpslld $31, %ymm1, %ymm1
443; AVX2-NEXT:    vpsrad $31, %ymm1, %ymm1
444; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm0
445; AVX2-NEXT:    retq
446  %xs = sext <8 x i1> %x to <8 x i32>
447  %ys = sext <8 x i1> %y to <8 x i32>
448  %r = xor <8 x i32> %xs, %ys
449  ret <8 x i32> %r
450}
451
452