1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
7
8; AVX128 tests:
9
10define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
11; SSE2-LABEL: vsel_float:
12; SSE2:       # BB#0: # %entry
13; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
14; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
15; SSE2-NEXT:    retq
16;
17; SSSE3-LABEL: vsel_float:
18; SSSE3:       # BB#0: # %entry
19; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
20; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
21; SSSE3-NEXT:    retq
22;
23; SSE41-LABEL: vsel_float:
24; SSE41:       # BB#0: # %entry
25; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
26; SSE41-NEXT:    retq
27;
28; AVX-LABEL: vsel_float:
29; AVX:       # BB#0: # %entry
30; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
31; AVX-NEXT:    retq
32entry:
33  %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v2
34  ret <4 x float> %vsel
35}
36
37define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {
38; SSE2-LABEL: vsel_float2:
39; SSE2:       # BB#0: # %entry
40; SSE2-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
41; SSE2-NEXT:    movaps %xmm1, %xmm0
42; SSE2-NEXT:    retq
43;
44; SSSE3-LABEL: vsel_float2:
45; SSSE3:       # BB#0: # %entry
46; SSSE3-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
47; SSSE3-NEXT:    movaps %xmm1, %xmm0
48; SSSE3-NEXT:    retq
49;
50; SSE41-LABEL: vsel_float2:
51; SSE41:       # BB#0: # %entry
52; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
53; SSE41-NEXT:    retq
54;
55; AVX-LABEL: vsel_float2:
56; AVX:       # BB#0: # %entry
57; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
58; AVX-NEXT:    retq
59entry:
60  %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
61  ret <4 x float> %vsel
62}
63
64define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
65; SSE2-LABEL: vsel_4xi8:
66; SSE2:       # BB#0: # %entry
67; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
68; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
69; SSE2-NEXT:    retq
70;
71; SSSE3-LABEL: vsel_4xi8:
72; SSSE3:       # BB#0: # %entry
73; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[3,0]
74; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
75; SSSE3-NEXT:    retq
76;
77; SSE41-LABEL: vsel_4xi8:
78; SSE41:       # BB#0: # %entry
79; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
80; SSE41-NEXT:    retq
81;
82; AVX1-LABEL: vsel_4xi8:
83; AVX1:       # BB#0: # %entry
84; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
85; AVX1-NEXT:    retq
86;
87; AVX2-LABEL: vsel_4xi8:
88; AVX2:       # BB#0: # %entry
89; AVX2-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
90; AVX2-NEXT:    retq
91entry:
92  %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i8> %v1, <4 x i8> %v2
93  ret <4 x i8> %vsel
94}
95
96define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
97; SSE2-LABEL: vsel_4xi16:
98; SSE2:       # BB#0: # %entry
99; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
100; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
101; SSE2-NEXT:    movaps %xmm1, %xmm0
102; SSE2-NEXT:    retq
103;
104; SSSE3-LABEL: vsel_4xi16:
105; SSSE3:       # BB#0: # %entry
106; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
107; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
108; SSSE3-NEXT:    movaps %xmm1, %xmm0
109; SSSE3-NEXT:    retq
110;
111; SSE41-LABEL: vsel_4xi16:
112; SSE41:       # BB#0: # %entry
113; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
114; SSE41-NEXT:    retq
115;
116; AVX1-LABEL: vsel_4xi16:
117; AVX1:       # BB#0: # %entry
118; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
119; AVX1-NEXT:    retq
120;
121; AVX2-LABEL: vsel_4xi16:
122; AVX2:       # BB#0: # %entry
123; AVX2-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
124; AVX2-NEXT:    retq
125entry:
126  %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i16> %v1, <4 x i16> %v2
127  ret <4 x i16> %vsel
128}
129
130define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
131; SSE2-LABEL: vsel_i32:
132; SSE2:       # BB#0: # %entry
133; SSE2-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
134; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
135; SSE2-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
136; SSE2-NEXT:    retq
137;
138; SSSE3-LABEL: vsel_i32:
139; SSSE3:       # BB#0: # %entry
140; SSSE3-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
141; SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
142; SSSE3-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
143; SSSE3-NEXT:    retq
144;
145; SSE41-LABEL: vsel_i32:
146; SSE41:       # BB#0: # %entry
147; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
148; SSE41-NEXT:    retq
149;
150; AVX1-LABEL: vsel_i32:
151; AVX1:       # BB#0: # %entry
152; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
153; AVX1-NEXT:    retq
154;
155; AVX2-LABEL: vsel_i32:
156; AVX2:       # BB#0: # %entry
157; AVX2-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
158; AVX2-NEXT:    retq
159entry:
160  %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2
161  ret <4 x i32> %vsel
162}
163
164define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
165; SSE2-LABEL: vsel_double:
166; SSE2:       # BB#0: # %entry
167; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
168; SSE2-NEXT:    movapd %xmm1, %xmm0
169; SSE2-NEXT:    retq
170;
171; SSSE3-LABEL: vsel_double:
172; SSSE3:       # BB#0: # %entry
173; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
174; SSSE3-NEXT:    movapd %xmm1, %xmm0
175; SSSE3-NEXT:    retq
176;
177; SSE41-LABEL: vsel_double:
178; SSE41:       # BB#0: # %entry
179; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
180; SSE41-NEXT:    retq
181;
182; AVX-LABEL: vsel_double:
183; AVX:       # BB#0: # %entry
184; AVX-NEXT:    vblendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
185; AVX-NEXT:    retq
186entry:
187  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
188  ret <2 x double> %vsel
189}
190
191define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
192; SSE2-LABEL: vsel_i64:
193; SSE2:       # BB#0: # %entry
194; SSE2-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
195; SSE2-NEXT:    movapd %xmm1, %xmm0
196; SSE2-NEXT:    retq
197;
198; SSSE3-LABEL: vsel_i64:
199; SSSE3:       # BB#0: # %entry
200; SSSE3-NEXT:    movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
201; SSSE3-NEXT:    movapd %xmm1, %xmm0
202; SSSE3-NEXT:    retq
203;
204; SSE41-LABEL: vsel_i64:
205; SSE41:       # BB#0: # %entry
206; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
207; SSE41-NEXT:    retq
208;
209; AVX1-LABEL: vsel_i64:
210; AVX1:       # BB#0: # %entry
211; AVX1-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
212; AVX1-NEXT:    retq
213;
214; AVX2-LABEL: vsel_i64:
215; AVX2:       # BB#0: # %entry
216; AVX2-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
217; AVX2-NEXT:    retq
218entry:
219  %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
220  ret <2 x i64> %vsel
221}
222
223define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
224; SSE2-LABEL: vsel_8xi16:
225; SSE2:       # BB#0: # %entry
226; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [0,65535,65535,65535,0,65535,65535,65535]
227; SSE2-NEXT:    andps %xmm2, %xmm1
228; SSE2-NEXT:    andnps %xmm0, %xmm2
229; SSE2-NEXT:    orps %xmm1, %xmm2
230; SSE2-NEXT:    movaps %xmm2, %xmm0
231; SSE2-NEXT:    retq
232;
233; SSSE3-LABEL: vsel_8xi16:
234; SSSE3:       # BB#0: # %entry
235; SSSE3-NEXT:    movaps {{.*#+}} xmm2 = [0,65535,65535,65535,0,65535,65535,65535]
236; SSSE3-NEXT:    andps %xmm2, %xmm1
237; SSSE3-NEXT:    andnps %xmm0, %xmm2
238; SSSE3-NEXT:    orps %xmm1, %xmm2
239; SSSE3-NEXT:    movaps %xmm2, %xmm0
240; SSSE3-NEXT:    retq
241;
242; SSE41-LABEL: vsel_8xi16:
243; SSE41:       # BB#0: # %entry
244; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]
245; SSE41-NEXT:    retq
246;
247; AVX-LABEL: vsel_8xi16:
248; AVX:       # BB#0: # %entry
249; AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]
250; AVX-NEXT:    retq
251entry:
252  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
253  ret <8 x i16> %vsel
254}
255
256define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
257; SSE2-LABEL: vsel_i8:
258; SSE2:       # BB#0: # %entry
259; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [0,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]
260; SSE2-NEXT:    andps %xmm2, %xmm1
261; SSE2-NEXT:    andnps %xmm0, %xmm2
262; SSE2-NEXT:    orps %xmm1, %xmm2
263; SSE2-NEXT:    movaps %xmm2, %xmm0
264; SSE2-NEXT:    retq
265;
266; SSSE3-LABEL: vsel_i8:
267; SSSE3:       # BB#0: # %entry
268; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[12],zero,zero,zero
269; SSSE3-NEXT:    pshufb {{.*#+}} xmm1 = zero,xmm1[1,2,3],zero,xmm1[5,6,7],zero,xmm1[9,10,11],zero,xmm1[13,14,15]
270; SSSE3-NEXT:    por %xmm1, %xmm0
271; SSSE3-NEXT:    retq
272;
273; SSE41-LABEL: vsel_i8:
274; SSE41:       # BB#0: # %entry
275; SSE41-NEXT:    movdqa %xmm0, %xmm2
276; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
277; SSE41-NEXT:    pblendvb %xmm0, %xmm2, %xmm1
278; SSE41-NEXT:    movdqa %xmm1, %xmm0
279; SSE41-NEXT:    retq
280;
281; AVX-LABEL: vsel_i8:
282; AVX:       # BB#0: # %entry
283; AVX-NEXT:    vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
284; AVX-NEXT:    vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
285; AVX-NEXT:    retq
286entry:
287  %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
288  ret <16 x i8> %vsel
289}
290
291
292; AVX256 tests:
293
294define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
295; SSE2-LABEL: vsel_float8:
296; SSE2:       # BB#0: # %entry
297; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
298; SSE2-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
299; SSE2-NEXT:    movaps %xmm2, %xmm0
300; SSE2-NEXT:    movaps %xmm3, %xmm1
301; SSE2-NEXT:    retq
302;
303; SSSE3-LABEL: vsel_float8:
304; SSSE3:       # BB#0: # %entry
305; SSSE3-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
306; SSSE3-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
307; SSSE3-NEXT:    movaps %xmm2, %xmm0
308; SSSE3-NEXT:    movaps %xmm3, %xmm1
309; SSSE3-NEXT:    retq
310;
311; SSE41-LABEL: vsel_float8:
312; SSE41:       # BB#0: # %entry
313; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
314; SSE41-NEXT:    blendps {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3]
315; SSE41-NEXT:    retq
316;
317; AVX-LABEL: vsel_float8:
318; AVX:       # BB#0: # %entry
319; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
320; AVX-NEXT:    retq
321entry:
322  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
323  ret <8 x float> %vsel
324}
325
326define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
327; SSE2-LABEL: vsel_i328:
328; SSE2:       # BB#0: # %entry
329; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
330; SSE2-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
331; SSE2-NEXT:    movaps %xmm2, %xmm0
332; SSE2-NEXT:    movaps %xmm3, %xmm1
333; SSE2-NEXT:    retq
334;
335; SSSE3-LABEL: vsel_i328:
336; SSSE3:       # BB#0: # %entry
337; SSSE3-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
338; SSSE3-NEXT:    movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
339; SSSE3-NEXT:    movaps %xmm2, %xmm0
340; SSSE3-NEXT:    movaps %xmm3, %xmm1
341; SSSE3-NEXT:    retq
342;
343; SSE41-LABEL: vsel_i328:
344; SSE41:       # BB#0: # %entry
345; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
346; SSE41-NEXT:    pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3,4,5,6,7]
347; SSE41-NEXT:    retq
348;
349; AVX-LABEL: vsel_i328:
350; AVX:       # BB#0: # %entry
351; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]
352; AVX-NEXT:    retq
353entry:
354  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
355  ret <8 x i32> %vsel
356}
357
358define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
359; SSE2-LABEL: vsel_double8:
360; SSE2:       # BB#0: # %entry
361; SSE2-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
362; SSE2-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
363; SSE2-NEXT:    movapd %xmm4, %xmm0
364; SSE2-NEXT:    movaps %xmm5, %xmm1
365; SSE2-NEXT:    movapd %xmm6, %xmm2
366; SSE2-NEXT:    movaps %xmm7, %xmm3
367; SSE2-NEXT:    retq
368;
369; SSSE3-LABEL: vsel_double8:
370; SSSE3:       # BB#0: # %entry
371; SSSE3-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
372; SSSE3-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
373; SSSE3-NEXT:    movapd %xmm4, %xmm0
374; SSSE3-NEXT:    movaps %xmm5, %xmm1
375; SSSE3-NEXT:    movapd %xmm6, %xmm2
376; SSSE3-NEXT:    movaps %xmm7, %xmm3
377; SSSE3-NEXT:    retq
378;
379; SSE41-LABEL: vsel_double8:
380; SSE41:       # BB#0: # %entry
381; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm4[1]
382; SSE41-NEXT:    blendpd {{.*#+}} xmm2 = xmm2[0],xmm6[1]
383; SSE41-NEXT:    movaps %xmm5, %xmm1
384; SSE41-NEXT:    movaps %xmm7, %xmm3
385; SSE41-NEXT:    retq
386;
387; AVX-LABEL: vsel_double8:
388; AVX:       # BB#0: # %entry
389; AVX-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3]
390; AVX-NEXT:    vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3]
391; AVX-NEXT:    retq
392entry:
393  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
394  ret <8 x double> %vsel
395}
396
397define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
398; SSE2-LABEL: vsel_i648:
399; SSE2:       # BB#0: # %entry
400; SSE2-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
401; SSE2-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
402; SSE2-NEXT:    movapd %xmm4, %xmm0
403; SSE2-NEXT:    movaps %xmm5, %xmm1
404; SSE2-NEXT:    movapd %xmm6, %xmm2
405; SSE2-NEXT:    movaps %xmm7, %xmm3
406; SSE2-NEXT:    retq
407;
408; SSSE3-LABEL: vsel_i648:
409; SSSE3:       # BB#0: # %entry
410; SSSE3-NEXT:    movsd {{.*#+}} xmm4 = xmm0[0],xmm4[1]
411; SSSE3-NEXT:    movsd {{.*#+}} xmm6 = xmm2[0],xmm6[1]
412; SSSE3-NEXT:    movapd %xmm4, %xmm0
413; SSSE3-NEXT:    movaps %xmm5, %xmm1
414; SSSE3-NEXT:    movapd %xmm6, %xmm2
415; SSSE3-NEXT:    movaps %xmm7, %xmm3
416; SSSE3-NEXT:    retq
417;
418; SSE41-LABEL: vsel_i648:
419; SSE41:       # BB#0: # %entry
420; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm4[4,5,6,7]
421; SSE41-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm6[4,5,6,7]
422; SSE41-NEXT:    movaps %xmm5, %xmm1
423; SSE41-NEXT:    movaps %xmm7, %xmm3
424; SSE41-NEXT:    retq
425;
426; AVX1-LABEL: vsel_i648:
427; AVX1:       # BB#0: # %entry
428; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3]
429; AVX1-NEXT:    vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3]
430; AVX1-NEXT:    retq
431;
432; AVX2-LABEL: vsel_i648:
433; AVX2:       # BB#0: # %entry
434; AVX2-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3,4,5,6,7]
435; AVX2-NEXT:    vblendps {{.*#+}} ymm1 = ymm1[0,1],ymm3[2,3,4,5,6,7]
436; AVX2-NEXT:    retq
437entry:
438  %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
439  ret <8 x i64> %vsel
440}
441
442define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {
443; SSE2-LABEL: vsel_double4:
444; SSE2:       # BB#0: # %entry
445; SSE2-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
446; SSE2-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
447; SSE2-NEXT:    movapd %xmm2, %xmm0
448; SSE2-NEXT:    movapd %xmm3, %xmm1
449; SSE2-NEXT:    retq
450;
451; SSSE3-LABEL: vsel_double4:
452; SSSE3:       # BB#0: # %entry
453; SSSE3-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
454; SSSE3-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
455; SSSE3-NEXT:    movapd %xmm2, %xmm0
456; SSSE3-NEXT:    movapd %xmm3, %xmm1
457; SSSE3-NEXT:    retq
458;
459; SSE41-LABEL: vsel_double4:
460; SSE41:       # BB#0: # %entry
461; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm2[1]
462; SSE41-NEXT:    blendpd {{.*#+}} xmm1 = xmm1[0],xmm3[1]
463; SSE41-NEXT:    retq
464;
465; AVX-LABEL: vsel_double4:
466; AVX:       # BB#0: # %entry
467; AVX-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3]
468; AVX-NEXT:    retq
469entry:
470  %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v1, <4 x double> %v2
471  ret <4 x double> %vsel
472}
473
474define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
475; SSE2-LABEL: testa:
476; SSE2:       # BB#0: # %entry
477; SSE2-NEXT:    movapd %xmm1, %xmm2
478; SSE2-NEXT:    cmplepd %xmm0, %xmm2
479; SSE2-NEXT:    andpd %xmm2, %xmm0
480; SSE2-NEXT:    andnpd %xmm1, %xmm2
481; SSE2-NEXT:    orpd %xmm2, %xmm0
482; SSE2-NEXT:    retq
483;
484; SSSE3-LABEL: testa:
485; SSSE3:       # BB#0: # %entry
486; SSSE3-NEXT:    movapd %xmm1, %xmm2
487; SSSE3-NEXT:    cmplepd %xmm0, %xmm2
488; SSSE3-NEXT:    andpd %xmm2, %xmm0
489; SSSE3-NEXT:    andnpd %xmm1, %xmm2
490; SSSE3-NEXT:    orpd %xmm2, %xmm0
491; SSSE3-NEXT:    retq
492;
493; SSE41-LABEL: testa:
494; SSE41:       # BB#0: # %entry
495; SSE41-NEXT:    movapd %xmm0, %xmm2
496; SSE41-NEXT:    movapd %xmm1, %xmm0
497; SSE41-NEXT:    cmplepd %xmm2, %xmm0
498; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
499; SSE41-NEXT:    movapd %xmm1, %xmm0
500; SSE41-NEXT:    retq
501;
502; AVX-LABEL: testa:
503; AVX:       # BB#0: # %entry
504; AVX-NEXT:    vcmplepd %xmm0, %xmm1, %xmm2
505; AVX-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
506; AVX-NEXT:    retq
507entry:
508  %max_is_x = fcmp oge <2 x double> %x, %y
509  %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
510  ret <2 x double> %max
511}
512
513define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
514; SSE2-LABEL: testb:
515; SSE2:       # BB#0: # %entry
516; SSE2-NEXT:    movapd %xmm1, %xmm2
517; SSE2-NEXT:    cmpnlepd %xmm0, %xmm2
518; SSE2-NEXT:    andpd %xmm2, %xmm0
519; SSE2-NEXT:    andnpd %xmm1, %xmm2
520; SSE2-NEXT:    orpd %xmm2, %xmm0
521; SSE2-NEXT:    retq
522;
523; SSSE3-LABEL: testb:
524; SSSE3:       # BB#0: # %entry
525; SSSE3-NEXT:    movapd %xmm1, %xmm2
526; SSSE3-NEXT:    cmpnlepd %xmm0, %xmm2
527; SSSE3-NEXT:    andpd %xmm2, %xmm0
528; SSSE3-NEXT:    andnpd %xmm1, %xmm2
529; SSSE3-NEXT:    orpd %xmm2, %xmm0
530; SSSE3-NEXT:    retq
531;
532; SSE41-LABEL: testb:
533; SSE41:       # BB#0: # %entry
534; SSE41-NEXT:    movapd %xmm0, %xmm2
535; SSE41-NEXT:    movapd %xmm1, %xmm0
536; SSE41-NEXT:    cmpnlepd %xmm2, %xmm0
537; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
538; SSE41-NEXT:    movapd %xmm1, %xmm0
539; SSE41-NEXT:    retq
540;
541; AVX-LABEL: testb:
542; AVX:       # BB#0: # %entry
543; AVX-NEXT:    vcmpnlepd %xmm0, %xmm1, %xmm2
544; AVX-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
545; AVX-NEXT:    retq
546entry:
547  %min_is_x = fcmp ult <2 x double> %x, %y
548  %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
549  ret <2 x double> %min
550}
551
552; If we can figure out a blend has a constant mask, we should emit the
553; blend instruction with an immediate mask
554define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {
555; SSE2-LABEL: constant_blendvpd_avx:
556; SSE2:       # BB#0: # %entry
557; SSE2-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
558; SSE2-NEXT:    movaps %xmm2, %xmm0
559; SSE2-NEXT:    movapd %xmm3, %xmm1
560; SSE2-NEXT:    retq
561;
562; SSSE3-LABEL: constant_blendvpd_avx:
563; SSSE3:       # BB#0: # %entry
564; SSSE3-NEXT:    movsd {{.*#+}} xmm3 = xmm1[0],xmm3[1]
565; SSSE3-NEXT:    movaps %xmm2, %xmm0
566; SSSE3-NEXT:    movapd %xmm3, %xmm1
567; SSSE3-NEXT:    retq
568;
569; SSE41-LABEL: constant_blendvpd_avx:
570; SSE41:       # BB#0: # %entry
571; SSE41-NEXT:    blendpd {{.*#+}} xmm1 = xmm1[0],xmm3[1]
572; SSE41-NEXT:    movaps %xmm2, %xmm0
573; SSE41-NEXT:    retq
574;
575; AVX-LABEL: constant_blendvpd_avx:
576; AVX:       # BB#0: # %entry
577; AVX-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3]
578; AVX-NEXT:    retq
579entry:
580  %select = select <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %xy, <4 x double> %ab
581  ret <4 x double> %select
582}
583
584define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {
585; SSE2-LABEL: constant_blendvps_avx:
586; SSE2:       # BB#0: # %entry
587; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm2[2,0]
588; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]
589; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm3[2,0]
590; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,0]
591; SSE2-NEXT:    movaps %xmm2, %xmm0
592; SSE2-NEXT:    movaps %xmm3, %xmm1
593; SSE2-NEXT:    retq
594;
595; SSSE3-LABEL: constant_blendvps_avx:
596; SSSE3:       # BB#0: # %entry
597; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm2[2,0]
598; SSSE3-NEXT:    shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]
599; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[3,0],xmm3[2,0]
600; SSSE3-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,0]
601; SSSE3-NEXT:    movaps %xmm2, %xmm0
602; SSSE3-NEXT:    movaps %xmm3, %xmm1
603; SSSE3-NEXT:    retq
604;
605; SSE41-LABEL: constant_blendvps_avx:
606; SSE41:       # BB#0: # %entry
607; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3]
608; SSE41-NEXT:    blendps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[3]
609; SSE41-NEXT:    retq
610;
611; AVX-LABEL: constant_blendvps_avx:
612; AVX:       # BB#0: # %entry
613; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6],ymm0[7]
614; AVX-NEXT:    retq
615entry:
616  %select = select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x float> %xyzw, <8 x float> %abcd
617  ret <8 x float> %select
618}
619
620define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {
621; SSE2-LABEL: constant_pblendvb_avx2:
622; SSE2:       # BB#0: # %entry
623; SSE2-NEXT:    movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
624; SSE2-NEXT:    movaps %xmm4, %xmm5
625; SSE2-NEXT:    andnps %xmm0, %xmm5
626; SSE2-NEXT:    andps %xmm4, %xmm2
627; SSE2-NEXT:    orps %xmm2, %xmm5
628; SSE2-NEXT:    andps %xmm4, %xmm3
629; SSE2-NEXT:    andnps %xmm1, %xmm4
630; SSE2-NEXT:    orps %xmm3, %xmm4
631; SSE2-NEXT:    movaps %xmm5, %xmm0
632; SSE2-NEXT:    movaps %xmm4, %xmm1
633; SSE2-NEXT:    retq
634;
635; SSSE3-LABEL: constant_pblendvb_avx2:
636; SSSE3:       # BB#0: # %entry
637; SSSE3-NEXT:    movdqa {{.*#+}} xmm4 = [128,128,2,128,4,5,6,128,128,128,10,128,12,13,14,128]
638; SSSE3-NEXT:    pshufb %xmm4, %xmm0
639; SSSE3-NEXT:    movdqa {{.*#+}} xmm5 = [0,1,128,3,128,128,128,7,8,9,128,11,128,128,128,15]
640; SSSE3-NEXT:    pshufb %xmm5, %xmm2
641; SSSE3-NEXT:    por %xmm2, %xmm0
642; SSSE3-NEXT:    pshufb %xmm4, %xmm1
643; SSSE3-NEXT:    pshufb %xmm5, %xmm3
644; SSSE3-NEXT:    por %xmm3, %xmm1
645; SSSE3-NEXT:    retq
646;
647; SSE41-LABEL: constant_pblendvb_avx2:
648; SSE41:       # BB#0: # %entry
649; SSE41-NEXT:    movdqa %xmm0, %xmm4
650; SSE41-NEXT:    movaps {{.*#+}} xmm0 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
651; SSE41-NEXT:    pblendvb %xmm0, %xmm4, %xmm2
652; SSE41-NEXT:    pblendvb %xmm0, %xmm1, %xmm3
653; SSE41-NEXT:    movdqa %xmm2, %xmm0
654; SSE41-NEXT:    movdqa %xmm3, %xmm1
655; SSE41-NEXT:    retq
656;
657; AVX1-LABEL: constant_pblendvb_avx2:
658; AVX1:       # BB#0: # %entry
659; AVX1-NEXT:    vmovaps {{.*#+}} ymm2 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]
660; AVX1-NEXT:    vandnps %ymm0, %ymm2, %ymm0
661; AVX1-NEXT:    vandps %ymm2, %ymm1, %ymm1
662; AVX1-NEXT:    vorps %ymm0, %ymm1, %ymm0
663; AVX1-NEXT:    retq
664;
665; AVX2-LABEL: constant_pblendvb_avx2:
666; AVX2:       # BB#0: # %entry
667; AVX2-NEXT:    vmovdqa {{.*#+}} ymm2 = [0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0,0,0,255,0,255,255,255,0]
668; AVX2-NEXT:    vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
669; AVX2-NEXT:    retq
670entry:
671  %select = select <32 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <32 x i8> %xyzw, <32 x i8> %abcd
672  ret <32 x i8> %select
673}
674
675declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)
676declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)
677
678;; 4 tests for shufflevectors that optimize to blend + immediate
679define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) {
680; SSE2-LABEL: blend_shufflevector_4xfloat:
681; SSE2:       # BB#0: # %entry
682; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
683; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
684; SSE2-NEXT:    retq
685;
686; SSSE3-LABEL: blend_shufflevector_4xfloat:
687; SSSE3:       # BB#0: # %entry
688; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
689; SSSE3-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
690; SSSE3-NEXT:    retq
691;
692; SSE41-LABEL: blend_shufflevector_4xfloat:
693; SSE41:       # BB#0: # %entry
694; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
695; SSE41-NEXT:    retq
696;
697; AVX-LABEL: blend_shufflevector_4xfloat:
698; AVX:       # BB#0: # %entry
699; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
700; AVX-NEXT:    retq
701entry:
702  %select = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
703  ret <4 x float> %select
704}
705
706define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) {
707; SSE2-LABEL: blend_shufflevector_8xfloat:
708; SSE2:       # BB#0: # %entry
709; SSE2-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
710; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]
711; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]
712; SSE2-NEXT:    movaps %xmm2, %xmm0
713; SSE2-NEXT:    movaps %xmm3, %xmm1
714; SSE2-NEXT:    retq
715;
716; SSSE3-LABEL: blend_shufflevector_8xfloat:
717; SSSE3:       # BB#0: # %entry
718; SSSE3-NEXT:    movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
719; SSSE3-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]
720; SSSE3-NEXT:    shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]
721; SSSE3-NEXT:    movaps %xmm2, %xmm0
722; SSSE3-NEXT:    movaps %xmm3, %xmm1
723; SSSE3-NEXT:    retq
724;
725; SSE41-LABEL: blend_shufflevector_8xfloat:
726; SSE41:       # BB#0: # %entry
727; SSE41-NEXT:    blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
728; SSE41-NEXT:    blendps {{.*#+}} xmm1 = xmm3[0,1],xmm1[2],xmm3[3]
729; SSE41-NEXT:    retq
730;
731; AVX-LABEL: blend_shufflevector_8xfloat:
732; AVX:       # BB#0: # %entry
733; AVX-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5],ymm0[6],ymm1[7]
734; AVX-NEXT:    retq
735entry:
736  %select = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 6, i32 15>
737  ret <8 x float> %select
738}
739
740define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) {
741; SSE2-LABEL: blend_shufflevector_4xdouble:
742; SSE2:       # BB#0: # %entry
743; SSE2-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
744; SSE2-NEXT:    movapd %xmm2, %xmm0
745; SSE2-NEXT:    retq
746;
747; SSSE3-LABEL: blend_shufflevector_4xdouble:
748; SSSE3:       # BB#0: # %entry
749; SSSE3-NEXT:    movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
750; SSSE3-NEXT:    movapd %xmm2, %xmm0
751; SSSE3-NEXT:    retq
752;
753; SSE41-LABEL: blend_shufflevector_4xdouble:
754; SSE41:       # BB#0: # %entry
755; SSE41-NEXT:    blendpd {{.*#+}} xmm0 = xmm0[0],xmm2[1]
756; SSE41-NEXT:    retq
757;
758; AVX-LABEL: blend_shufflevector_4xdouble:
759; AVX:       # BB#0: # %entry
760; AVX-NEXT:    vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3]
761; AVX-NEXT:    retq
762entry:
763  %select = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
764  ret <4 x double> %select
765}
766
767define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) {
768; SSE2-LABEL: blend_shufflevector_4xi64:
769; SSE2:       # BB#0: # %entry
770; SSE2-NEXT:    movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
771; SSE2-NEXT:    movaps %xmm3, %xmm1
772; SSE2-NEXT:    retq
773;
774; SSSE3-LABEL: blend_shufflevector_4xi64:
775; SSSE3:       # BB#0: # %entry
776; SSSE3-NEXT:    movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
777; SSSE3-NEXT:    movaps %xmm3, %xmm1
778; SSSE3-NEXT:    retq
779;
780; SSE41-LABEL: blend_shufflevector_4xi64:
781; SSE41:       # BB#0: # %entry
782; SSE41-NEXT:    pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
783; SSE41-NEXT:    movaps %xmm3, %xmm1
784; SSE41-NEXT:    retq
785;
786; AVX1-LABEL: blend_shufflevector_4xi64:
787; AVX1:       # BB#0: # %entry
788; AVX1-NEXT:    vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3]
789; AVX1-NEXT:    retq
790;
791; AVX2-LABEL: blend_shufflevector_4xi64:
792; AVX2:       # BB#0: # %entry
793; AVX2-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5,6,7]
794; AVX2-NEXT:    retq
795entry:
796  %select = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
797  ret <4 x i64> %select
798}
799
800define <4 x i32> @blend_logic_v4i32(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) {
801; SSE2-LABEL: blend_logic_v4i32:
802; SSE2:       # BB#0: # %entry
803; SSE2-NEXT:    psrad $31, %xmm0
804; SSE2-NEXT:    pand %xmm0, %xmm1
805; SSE2-NEXT:    pandn %xmm2, %xmm0
806; SSE2-NEXT:    por %xmm1, %xmm0
807; SSE2-NEXT:    retq
808;
809; SSSE3-LABEL: blend_logic_v4i32:
810; SSSE3:       # BB#0: # %entry
811; SSSE3-NEXT:    psrad $31, %xmm0
812; SSSE3-NEXT:    pand %xmm0, %xmm1
813; SSSE3-NEXT:    pandn %xmm2, %xmm0
814; SSSE3-NEXT:    por %xmm1, %xmm0
815; SSSE3-NEXT:    retq
816;
817; SSE41-LABEL: blend_logic_v4i32:
818; SSE41:       # BB#0: # %entry
819; SSE41-NEXT:    psrad $31, %xmm0
820; SSE41-NEXT:    pblendvb %xmm0, %xmm1, %xmm2
821; SSE41-NEXT:    movdqa %xmm2, %xmm0
822; SSE41-NEXT:    retq
823;
824; AVX-LABEL: blend_logic_v4i32:
825; AVX:       # BB#0: # %entry
826; AVX-NEXT:    vpsrad $31, %xmm0, %xmm0
827; AVX-NEXT:    vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
828; AVX-NEXT:    retq
829entry:
830  %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
831  %sub = sub nsw <4 x i32> zeroinitializer, %a
832  %0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
833  %1 = and <4 x i32> %c, %0
834  %2 = and <4 x i32> %a, %b.lobit
835  %cond = or <4 x i32> %1, %2
836  ret <4 x i32> %cond
837}
838
839define <8 x i32> @blend_logic_v8i32(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) {
840; SSE2-LABEL: blend_logic_v8i32:
841; SSE2:       # BB#0: # %entry
842; SSE2-NEXT:    psrad $31, %xmm0
843; SSE2-NEXT:    psrad $31, %xmm1
844; SSE2-NEXT:    pand %xmm1, %xmm3
845; SSE2-NEXT:    pandn %xmm5, %xmm1
846; SSE2-NEXT:    por %xmm3, %xmm1
847; SSE2-NEXT:    pand %xmm0, %xmm2
848; SSE2-NEXT:    pandn %xmm4, %xmm0
849; SSE2-NEXT:    por %xmm2, %xmm0
850; SSE2-NEXT:    retq
851;
852; SSSE3-LABEL: blend_logic_v8i32:
853; SSSE3:       # BB#0: # %entry
854; SSSE3-NEXT:    psrad $31, %xmm0
855; SSSE3-NEXT:    psrad $31, %xmm1
856; SSSE3-NEXT:    pand %xmm1, %xmm3
857; SSSE3-NEXT:    pandn %xmm5, %xmm1
858; SSSE3-NEXT:    por %xmm3, %xmm1
859; SSSE3-NEXT:    pand %xmm0, %xmm2
860; SSSE3-NEXT:    pandn %xmm4, %xmm0
861; SSSE3-NEXT:    por %xmm2, %xmm0
862; SSSE3-NEXT:    retq
863;
864; SSE41-LABEL: blend_logic_v8i32:
865; SSE41:       # BB#0: # %entry
866; SSE41-NEXT:    psrad $31, %xmm1
867; SSE41-NEXT:    psrad $31, %xmm0
868; SSE41-NEXT:    pblendvb %xmm0, %xmm2, %xmm4
869; SSE41-NEXT:    movdqa %xmm1, %xmm0
870; SSE41-NEXT:    pblendvb %xmm0, %xmm3, %xmm5
871; SSE41-NEXT:    movdqa %xmm4, %xmm0
872; SSE41-NEXT:    movdqa %xmm5, %xmm1
873; SSE41-NEXT:    retq
874;
875; AVX1-LABEL: blend_logic_v8i32:
876; AVX1:       # BB#0: # %entry
877; AVX1-NEXT:    vpsrad $31, %xmm0, %xmm3
878; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm0
879; AVX1-NEXT:    vpsrad $31, %xmm0, %xmm0
880; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm3, %ymm0
881; AVX1-NEXT:    vandnps %ymm2, %ymm0, %ymm2
882; AVX1-NEXT:    vandps %ymm0, %ymm1, %ymm0
883; AVX1-NEXT:    vorps %ymm0, %ymm2, %ymm0
884; AVX1-NEXT:    retq
885;
886; AVX2-LABEL: blend_logic_v8i32:
887; AVX2:       # BB#0: # %entry
888; AVX2-NEXT:    vpsrad $31, %ymm0, %ymm0
889; AVX2-NEXT:    vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
890; AVX2-NEXT:    retq
891entry:
892  %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
893  %sub = sub nsw <8 x i32> zeroinitializer, %a
894  %0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
895  %1 = and <8 x i32> %c, %0
896  %2 = and <8 x i32> %a, %b.lobit
897  %cond = or <8 x i32> %1, %2
898  ret <8 x i32> %cond
899}
900
901define <4 x i32> @blend_neg_logic_v4i32(<4 x i32> %a, <4 x i32> %b) {
902; SSE-LABEL: blend_neg_logic_v4i32:
903; SSE:       # BB#0: # %entry
904; SSE-NEXT:    psrad $31, %xmm1
905; SSE-NEXT:    pxor %xmm1, %xmm0
906; SSE-NEXT:    psubd %xmm1, %xmm0
907; SSE-NEXT:    retq
908;
909; AVX-LABEL: blend_neg_logic_v4i32:
910; AVX:       # BB#0: # %entry
911; AVX-NEXT:    vpsrad $31, %xmm1, %xmm1
912; AVX-NEXT:    vpxor %xmm1, %xmm0, %xmm0
913; AVX-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
914; AVX-NEXT:    retq
915entry:
916  %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
917  %sub = sub nsw <4 x i32> zeroinitializer, %a
918  %0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
919  %1 = and <4 x i32> %a, %0
920  %2 = and <4 x i32> %b.lobit, %sub
921  %cond = or <4 x i32> %1, %2
922  ret <4 x i32> %cond
923}
924
925define <8 x i32> @blend_neg_logic_v8i32(<8 x i32> %a, <8 x i32> %b) {
926; SSE-LABEL: blend_neg_logic_v8i32:
927; SSE:       # BB#0: # %entry
928; SSE-NEXT:    psrad $31, %xmm3
929; SSE-NEXT:    psrad $31, %xmm2
930; SSE-NEXT:    pxor %xmm2, %xmm0
931; SSE-NEXT:    psubd %xmm2, %xmm0
932; SSE-NEXT:    pxor %xmm3, %xmm1
933; SSE-NEXT:    psubd %xmm3, %xmm1
934; SSE-NEXT:    retq
935;
936; AVX1-LABEL: blend_neg_logic_v8i32:
937; AVX1:       # BB#0: # %entry
938; AVX1-NEXT:    vpsrad $31, %xmm1, %xmm2
939; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm1
940; AVX1-NEXT:    vpsrad $31, %xmm1, %xmm1
941; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm2, %ymm1
942; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
943; AVX1-NEXT:    vpxor %xmm3, %xmm3, %xmm3
944; AVX1-NEXT:    vpsubd %xmm2, %xmm3, %xmm2
945; AVX1-NEXT:    vpsubd %xmm0, %xmm3, %xmm3
946; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
947; AVX1-NEXT:    vandnps %ymm0, %ymm1, %ymm0
948; AVX1-NEXT:    vandps %ymm2, %ymm1, %ymm1
949; AVX1-NEXT:    vorps %ymm1, %ymm0, %ymm0
950; AVX1-NEXT:    retq
951;
952; AVX2-LABEL: blend_neg_logic_v8i32:
953; AVX2:       # BB#0: # %entry
954; AVX2-NEXT:    vpsrad $31, %ymm1, %ymm1
955; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm0
956; AVX2-NEXT:    vpsubd %ymm1, %ymm0, %ymm0
957; AVX2-NEXT:    retq
958entry:
959  %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
960  %sub = sub nsw <8 x i32> zeroinitializer, %a
961  %0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
962  %1 = and <8 x i32> %a, %0
963  %2 = and <8 x i32> %b.lobit, %sub
964  %cond = or <8 x i32> %1, %2
965  ret <8 x i32> %cond
966}
967
968define <4 x i32> @blend_neg_logic_v4i32_2(<4 x i32> %v, <4 x i32> %c) {
969; SSE2-LABEL: blend_neg_logic_v4i32_2:
970; SSE2:       # BB#0: # %entry
971; SSE2-NEXT:    psrad $31, %xmm1
972; SSE2-NEXT:    pxor %xmm1, %xmm0
973; SSE2-NEXT:    psubd %xmm0, %xmm1
974; SSE2-NEXT:    movdqa %xmm1, %xmm0
975; SSE2-NEXT:    retq
976;
977; SSSE3-LABEL: blend_neg_logic_v4i32_2:
978; SSSE3:       # BB#0: # %entry
979; SSSE3-NEXT:    psrad $31, %xmm1
980; SSSE3-NEXT:    pxor %xmm1, %xmm0
981; SSSE3-NEXT:    psubd %xmm0, %xmm1
982; SSSE3-NEXT:    movdqa %xmm1, %xmm0
983; SSSE3-NEXT:    retq
984;
985; SSE41-LABEL: blend_neg_logic_v4i32_2:
986; SSE41:       # BB#0: # %entry
987; SSE41-NEXT:    movdqa %xmm0, %xmm2
988; SSE41-NEXT:    pxor %xmm3, %xmm3
989; SSE41-NEXT:    psubd %xmm2, %xmm3
990; SSE41-NEXT:    movaps %xmm1, %xmm0
991; SSE41-NEXT:    blendvps %xmm0, %xmm2, %xmm3
992; SSE41-NEXT:    movaps %xmm3, %xmm0
993; SSE41-NEXT:    retq
994;
995; AVX-LABEL: blend_neg_logic_v4i32_2:
996; AVX:       # BB#0: # %entry
997; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
998; AVX-NEXT:    vpsubd %xmm0, %xmm2, %xmm2
999; AVX-NEXT:    vblendvps %xmm1, %xmm0, %xmm2, %xmm0
1000; AVX-NEXT:    retq
1001entry:
1002  %0 = ashr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
1003  %1 = trunc <4 x i32> %0 to <4 x i1>
1004  %2 = sub nsw <4 x i32> zeroinitializer, %v
1005  %3 = select <4 x i1> %1, <4 x i32> %v, <4 x i32> %2
1006  ret <4 x i32> %3
1007}
1008