1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F 8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW 9 10; 11; Unsigned Maximum (GT) 12; 13 14define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) { 15; SSE2-LABEL: max_gt_v2i64: 16; SSE2: # %bb.0: 17; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] 18; SSE2-NEXT: movdqa %xmm1, %xmm3 19; SSE2-NEXT: pxor %xmm2, %xmm3 20; SSE2-NEXT: pxor %xmm0, %xmm2 21; SSE2-NEXT: movdqa %xmm2, %xmm4 22; SSE2-NEXT: pcmpgtd %xmm3, %xmm4 23; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 24; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 25; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] 26; SSE2-NEXT: pand %xmm5, %xmm2 27; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] 28; SSE2-NEXT: por %xmm2, %xmm3 29; SSE2-NEXT: pand %xmm3, %xmm0 30; SSE2-NEXT: pandn %xmm1, %xmm3 31; SSE2-NEXT: por %xmm3, %xmm0 32; SSE2-NEXT: retq 33; 34; SSE41-LABEL: max_gt_v2i64: 35; SSE41: # %bb.0: 36; SSE41-NEXT: movdqa %xmm0, %xmm2 37; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456] 38; SSE41-NEXT: movdqa %xmm1, %xmm3 39; SSE41-NEXT: pxor %xmm0, %xmm3 40; SSE41-NEXT: pxor %xmm2, %xmm0 41; SSE41-NEXT: movdqa %xmm0, %xmm4 42; SSE41-NEXT: pcmpgtd %xmm3, %xmm4 43; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 44; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 45; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 46; SSE41-NEXT: pand %xmm5, %xmm0 47; SSE41-NEXT: por %xmm4, %xmm0 48; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 49; SSE41-NEXT: movapd %xmm1, %xmm0 50; SSE41-NEXT: retq 51; 52; SSE42-LABEL: max_gt_v2i64: 53; SSE42: # %bb.0: 54; SSE42-NEXT: movdqa %xmm0, %xmm2 55; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] 56; SSE42-NEXT: movdqa %xmm1, %xmm3 57; SSE42-NEXT: pxor %xmm0, %xmm3 58; SSE42-NEXT: pxor %xmm2, %xmm0 59; SSE42-NEXT: pcmpgtq %xmm3, %xmm0 60; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm1 61; SSE42-NEXT: movapd %xmm1, %xmm0 62; SSE42-NEXT: retq 63; 64; AVX1-LABEL: max_gt_v2i64: 65; AVX1: # %bb.0: 66; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 67; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 68; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2 69; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 70; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 71; AVX1-NEXT: retq 72; 73; AVX2-LABEL: max_gt_v2i64: 74; AVX2: # %bb.0: 75; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 76; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 77; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2 78; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 79; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 80; AVX2-NEXT: retq 81; 82; AVX512-LABEL: max_gt_v2i64: 83; AVX512: # %bb.0: 84; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 85; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 86; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 87; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 88; AVX512-NEXT: vzeroupper 89; AVX512-NEXT: retq 90 %1 = icmp ugt <2 x i64> %a, %b 91 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b 92 ret <2 x i64> %2 93} 94 95define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) { 96; SSE2-LABEL: max_gt_v4i64: 97; SSE2: # %bb.0: 98; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] 99; SSE2-NEXT: movdqa %xmm2, %xmm5 100; SSE2-NEXT: pxor %xmm4, %xmm5 101; SSE2-NEXT: movdqa %xmm0, %xmm6 102; SSE2-NEXT: pxor %xmm4, %xmm6 103; SSE2-NEXT: movdqa %xmm6, %xmm7 104; SSE2-NEXT: pcmpgtd %xmm5, %xmm7 105; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2] 106; SSE2-NEXT: pcmpeqd %xmm5, %xmm6 107; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] 108; SSE2-NEXT: pand %xmm8, %xmm5 109; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3] 110; SSE2-NEXT: por %xmm5, %xmm6 111; SSE2-NEXT: pand %xmm6, %xmm0 112; SSE2-NEXT: pandn %xmm2, %xmm6 113; SSE2-NEXT: por %xmm6, %xmm0 114; SSE2-NEXT: movdqa %xmm3, %xmm2 115; SSE2-NEXT: pxor %xmm4, %xmm2 116; SSE2-NEXT: pxor %xmm1, %xmm4 117; SSE2-NEXT: movdqa %xmm4, %xmm5 118; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 119; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] 120; SSE2-NEXT: pcmpeqd %xmm2, %xmm4 121; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] 122; SSE2-NEXT: pand %xmm6, %xmm2 123; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] 124; SSE2-NEXT: por %xmm2, %xmm4 125; SSE2-NEXT: pand %xmm4, %xmm1 126; SSE2-NEXT: pandn %xmm3, %xmm4 127; SSE2-NEXT: por %xmm4, %xmm1 128; SSE2-NEXT: retq 129; 130; SSE41-LABEL: max_gt_v4i64: 131; SSE41: # %bb.0: 132; SSE41-NEXT: movdqa %xmm0, %xmm4 133; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259456,9223372039002259456] 134; SSE41-NEXT: movdqa %xmm2, %xmm6 135; SSE41-NEXT: pxor %xmm5, %xmm6 136; SSE41-NEXT: movdqa %xmm0, %xmm7 137; SSE41-NEXT: pxor %xmm5, %xmm7 138; SSE41-NEXT: movdqa %xmm7, %xmm0 139; SSE41-NEXT: pcmpgtd %xmm6, %xmm0 140; SSE41-NEXT: pshufd {{.*#+}} xmm8 = xmm0[0,0,2,2] 141; SSE41-NEXT: pcmpeqd %xmm6, %xmm7 142; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3] 143; SSE41-NEXT: pand %xmm8, %xmm6 144; SSE41-NEXT: por %xmm6, %xmm0 145; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm2 146; SSE41-NEXT: movdqa %xmm3, %xmm0 147; SSE41-NEXT: pxor %xmm5, %xmm0 148; SSE41-NEXT: pxor %xmm1, %xmm5 149; SSE41-NEXT: movdqa %xmm5, %xmm4 150; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 151; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2] 152; SSE41-NEXT: pcmpeqd %xmm0, %xmm5 153; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3] 154; SSE41-NEXT: pand %xmm6, %xmm0 155; SSE41-NEXT: por %xmm4, %xmm0 156; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3 157; SSE41-NEXT: movapd %xmm2, %xmm0 158; SSE41-NEXT: movapd %xmm3, %xmm1 159; SSE41-NEXT: retq 160; 161; SSE42-LABEL: max_gt_v4i64: 162; SSE42: # %bb.0: 163; SSE42-NEXT: movdqa %xmm0, %xmm4 164; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808] 165; SSE42-NEXT: movdqa %xmm2, %xmm6 166; SSE42-NEXT: pxor %xmm5, %xmm6 167; SSE42-NEXT: pxor %xmm5, %xmm0 168; SSE42-NEXT: pcmpgtq %xmm6, %xmm0 169; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm2 170; SSE42-NEXT: movdqa %xmm3, %xmm0 171; SSE42-NEXT: pxor %xmm5, %xmm0 172; SSE42-NEXT: pxor %xmm1, %xmm5 173; SSE42-NEXT: pcmpgtq %xmm0, %xmm5 174; SSE42-NEXT: movdqa %xmm5, %xmm0 175; SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm3 176; SSE42-NEXT: movapd %xmm2, %xmm0 177; SSE42-NEXT: movapd %xmm3, %xmm1 178; SSE42-NEXT: retq 179; 180; AVX1-LABEL: max_gt_v4i64: 181; AVX1: # %bb.0: 182; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 183; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] 184; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 185; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 186; AVX1-NEXT: vpxor %xmm3, %xmm4, %xmm4 187; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm2 188; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm4 189; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm3 190; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm3 191; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 192; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 193; AVX1-NEXT: retq 194; 195; AVX2-LABEL: max_gt_v4i64: 196; AVX2: # %bb.0: 197; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] 198; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 199; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 200; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2 201; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 202; AVX2-NEXT: retq 203; 204; AVX512-LABEL: max_gt_v4i64: 205; AVX512: # %bb.0: 206; AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 207; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 208; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 209; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 210; AVX512-NEXT: retq 211 %1 = icmp ugt <4 x i64> %a, %b 212 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b 213 ret <4 x i64> %2 214} 215 216define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) { 217; SSE2-LABEL: max_gt_v4i32: 218; SSE2: # %bb.0: 219; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] 220; SSE2-NEXT: movdqa %xmm1, %xmm3 221; SSE2-NEXT: pxor %xmm2, %xmm3 222; SSE2-NEXT: pxor %xmm0, %xmm2 223; SSE2-NEXT: pcmpgtd %xmm3, %xmm2 224; SSE2-NEXT: pand %xmm2, %xmm0 225; SSE2-NEXT: pandn %xmm1, %xmm2 226; SSE2-NEXT: por %xmm2, %xmm0 227; SSE2-NEXT: retq 228; 229; SSE41-LABEL: max_gt_v4i32: 230; SSE41: # %bb.0: 231; SSE41-NEXT: pmaxud %xmm1, %xmm0 232; SSE41-NEXT: retq 233; 234; SSE42-LABEL: max_gt_v4i32: 235; SSE42: # %bb.0: 236; SSE42-NEXT: pmaxud %xmm1, %xmm0 237; SSE42-NEXT: retq 238; 239; AVX-LABEL: max_gt_v4i32: 240; AVX: # %bb.0: 241; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 242; AVX-NEXT: retq 243 %1 = icmp ugt <4 x i32> %a, %b 244 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b 245 ret <4 x i32> %2 246} 247 248define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) { 249; SSE2-LABEL: max_gt_v8i32: 250; SSE2: # %bb.0: 251; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648] 252; SSE2-NEXT: movdqa %xmm2, %xmm6 253; SSE2-NEXT: pxor %xmm5, %xmm6 254; SSE2-NEXT: movdqa %xmm0, %xmm4 255; SSE2-NEXT: pxor %xmm5, %xmm4 256; SSE2-NEXT: pcmpgtd %xmm6, %xmm4 257; SSE2-NEXT: pand %xmm4, %xmm0 258; SSE2-NEXT: pandn %xmm2, %xmm4 259; SSE2-NEXT: por %xmm0, %xmm4 260; SSE2-NEXT: movdqa %xmm3, %xmm0 261; SSE2-NEXT: pxor %xmm5, %xmm0 262; SSE2-NEXT: pxor %xmm1, %xmm5 263; SSE2-NEXT: pcmpgtd %xmm0, %xmm5 264; SSE2-NEXT: pand %xmm5, %xmm1 265; SSE2-NEXT: pandn %xmm3, %xmm5 266; SSE2-NEXT: por %xmm5, %xmm1 267; SSE2-NEXT: movdqa %xmm4, %xmm0 268; SSE2-NEXT: retq 269; 270; SSE41-LABEL: max_gt_v8i32: 271; SSE41: # %bb.0: 272; SSE41-NEXT: pmaxud %xmm2, %xmm0 273; SSE41-NEXT: pmaxud %xmm3, %xmm1 274; SSE41-NEXT: retq 275; 276; SSE42-LABEL: max_gt_v8i32: 277; SSE42: # %bb.0: 278; SSE42-NEXT: pmaxud %xmm2, %xmm0 279; SSE42-NEXT: pmaxud %xmm3, %xmm1 280; SSE42-NEXT: retq 281; 282; AVX1-LABEL: max_gt_v8i32: 283; AVX1: # %bb.0: 284; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 285; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 286; AVX1-NEXT: vpmaxud %xmm2, %xmm3, %xmm2 287; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 288; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 289; AVX1-NEXT: retq 290; 291; AVX2-LABEL: max_gt_v8i32: 292; AVX2: # %bb.0: 293; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 294; AVX2-NEXT: retq 295; 296; AVX512-LABEL: max_gt_v8i32: 297; AVX512: # %bb.0: 298; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 299; AVX512-NEXT: retq 300 %1 = icmp ugt <8 x i32> %a, %b 301 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b 302 ret <8 x i32> %2 303} 304 305define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) { 306; SSE2-LABEL: max_gt_v8i16: 307; SSE2: # %bb.0: 308; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] 309; SSE2-NEXT: pxor %xmm2, %xmm1 310; SSE2-NEXT: pxor %xmm2, %xmm0 311; SSE2-NEXT: pmaxsw %xmm1, %xmm0 312; SSE2-NEXT: pxor %xmm2, %xmm0 313; SSE2-NEXT: retq 314; 315; SSE41-LABEL: max_gt_v8i16: 316; SSE41: # %bb.0: 317; SSE41-NEXT: pmaxuw %xmm1, %xmm0 318; SSE41-NEXT: retq 319; 320; SSE42-LABEL: max_gt_v8i16: 321; SSE42: # %bb.0: 322; SSE42-NEXT: pmaxuw %xmm1, %xmm0 323; SSE42-NEXT: retq 324; 325; AVX-LABEL: max_gt_v8i16: 326; AVX: # %bb.0: 327; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 328; AVX-NEXT: retq 329 %1 = icmp ugt <8 x i16> %a, %b 330 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b 331 ret <8 x i16> %2 332} 333 334define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) { 335; SSE2-LABEL: max_gt_v16i16: 336; SSE2: # %bb.0: 337; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768] 338; SSE2-NEXT: pxor %xmm4, %xmm2 339; SSE2-NEXT: pxor %xmm4, %xmm0 340; SSE2-NEXT: pmaxsw %xmm2, %xmm0 341; SSE2-NEXT: pxor %xmm4, %xmm0 342; SSE2-NEXT: pxor %xmm4, %xmm3 343; SSE2-NEXT: pxor %xmm4, %xmm1 344; SSE2-NEXT: pmaxsw %xmm3, %xmm1 345; SSE2-NEXT: pxor %xmm4, %xmm1 346; SSE2-NEXT: retq 347; 348; SSE41-LABEL: max_gt_v16i16: 349; SSE41: # %bb.0: 350; SSE41-NEXT: pmaxuw %xmm2, %xmm0 351; SSE41-NEXT: pmaxuw %xmm3, %xmm1 352; SSE41-NEXT: retq 353; 354; SSE42-LABEL: max_gt_v16i16: 355; SSE42: # %bb.0: 356; SSE42-NEXT: pmaxuw %xmm2, %xmm0 357; SSE42-NEXT: pmaxuw %xmm3, %xmm1 358; SSE42-NEXT: retq 359; 360; AVX1-LABEL: max_gt_v16i16: 361; AVX1: # %bb.0: 362; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 363; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 364; AVX1-NEXT: vpmaxuw %xmm2, %xmm3, %xmm2 365; AVX1-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 366; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 367; AVX1-NEXT: retq 368; 369; AVX2-LABEL: max_gt_v16i16: 370; AVX2: # %bb.0: 371; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 372; AVX2-NEXT: retq 373; 374; AVX512-LABEL: max_gt_v16i16: 375; AVX512: # %bb.0: 376; AVX512-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 377; AVX512-NEXT: retq 378 %1 = icmp ugt <16 x i16> %a, %b 379 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b 380 ret <16 x i16> %2 381} 382 383define <16 x i8> @max_gt_v16i8(<16 x i8> %a, <16 x i8> %b) { 384; SSE-LABEL: max_gt_v16i8: 385; SSE: # %bb.0: 386; SSE-NEXT: pmaxub %xmm1, %xmm0 387; SSE-NEXT: retq 388; 389; AVX-LABEL: max_gt_v16i8: 390; AVX: # %bb.0: 391; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 392; AVX-NEXT: retq 393 %1 = icmp ugt <16 x i8> %a, %b 394 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b 395 ret <16 x i8> %2 396} 397 398define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) { 399; SSE-LABEL: max_gt_v32i8: 400; SSE: # %bb.0: 401; SSE-NEXT: pmaxub %xmm2, %xmm0 402; SSE-NEXT: pmaxub %xmm3, %xmm1 403; SSE-NEXT: retq 404; 405; AVX1-LABEL: max_gt_v32i8: 406; AVX1: # %bb.0: 407; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 408; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 409; AVX1-NEXT: vpmaxub %xmm2, %xmm3, %xmm2 410; AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 411; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 412; AVX1-NEXT: retq 413; 414; AVX2-LABEL: max_gt_v32i8: 415; AVX2: # %bb.0: 416; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 417; AVX2-NEXT: retq 418; 419; AVX512-LABEL: max_gt_v32i8: 420; AVX512: # %bb.0: 421; AVX512-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 422; AVX512-NEXT: retq 423 %1 = icmp ugt <32 x i8> %a, %b 424 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b 425 ret <32 x i8> %2 426} 427 428; 429; Unsigned Maximum (GE) 430; 431 432define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) { 433; SSE2-LABEL: max_ge_v2i64: 434; SSE2: # %bb.0: 435; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] 436; SSE2-NEXT: movdqa %xmm1, %xmm3 437; SSE2-NEXT: pxor %xmm2, %xmm3 438; SSE2-NEXT: pxor %xmm0, %xmm2 439; SSE2-NEXT: movdqa %xmm2, %xmm4 440; SSE2-NEXT: pcmpgtd %xmm3, %xmm4 441; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 442; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 443; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] 444; SSE2-NEXT: pand %xmm5, %xmm2 445; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] 446; SSE2-NEXT: por %xmm2, %xmm3 447; SSE2-NEXT: pand %xmm3, %xmm0 448; SSE2-NEXT: pandn %xmm1, %xmm3 449; SSE2-NEXT: por %xmm3, %xmm0 450; SSE2-NEXT: retq 451; 452; SSE41-LABEL: max_ge_v2i64: 453; SSE41: # %bb.0: 454; SSE41-NEXT: movdqa %xmm0, %xmm2 455; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456] 456; SSE41-NEXT: movdqa %xmm1, %xmm3 457; SSE41-NEXT: pxor %xmm0, %xmm3 458; SSE41-NEXT: pxor %xmm2, %xmm0 459; SSE41-NEXT: movdqa %xmm0, %xmm4 460; SSE41-NEXT: pcmpgtd %xmm3, %xmm4 461; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 462; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 463; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 464; SSE41-NEXT: pand %xmm5, %xmm0 465; SSE41-NEXT: por %xmm4, %xmm0 466; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 467; SSE41-NEXT: movapd %xmm1, %xmm0 468; SSE41-NEXT: retq 469; 470; SSE42-LABEL: max_ge_v2i64: 471; SSE42: # %bb.0: 472; SSE42-NEXT: movdqa %xmm0, %xmm2 473; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] 474; SSE42-NEXT: movdqa %xmm1, %xmm3 475; SSE42-NEXT: pxor %xmm0, %xmm3 476; SSE42-NEXT: pxor %xmm2, %xmm0 477; SSE42-NEXT: pcmpgtq %xmm3, %xmm0 478; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm1 479; SSE42-NEXT: movapd %xmm1, %xmm0 480; SSE42-NEXT: retq 481; 482; AVX1-LABEL: max_ge_v2i64: 483; AVX1: # %bb.0: 484; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 485; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 486; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2 487; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 488; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 489; AVX1-NEXT: retq 490; 491; AVX2-LABEL: max_ge_v2i64: 492; AVX2: # %bb.0: 493; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 494; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 495; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2 496; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 497; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 498; AVX2-NEXT: retq 499; 500; AVX512-LABEL: max_ge_v2i64: 501; AVX512: # %bb.0: 502; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 503; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 504; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 505; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 506; AVX512-NEXT: vzeroupper 507; AVX512-NEXT: retq 508 %1 = icmp uge <2 x i64> %a, %b 509 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b 510 ret <2 x i64> %2 511} 512 513define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) { 514; SSE2-LABEL: max_ge_v4i64: 515; SSE2: # %bb.0: 516; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] 517; SSE2-NEXT: movdqa %xmm2, %xmm5 518; SSE2-NEXT: pxor %xmm4, %xmm5 519; SSE2-NEXT: movdqa %xmm0, %xmm6 520; SSE2-NEXT: pxor %xmm4, %xmm6 521; SSE2-NEXT: movdqa %xmm6, %xmm7 522; SSE2-NEXT: pcmpgtd %xmm5, %xmm7 523; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2] 524; SSE2-NEXT: pcmpeqd %xmm5, %xmm6 525; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] 526; SSE2-NEXT: pand %xmm8, %xmm5 527; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3] 528; SSE2-NEXT: por %xmm5, %xmm6 529; SSE2-NEXT: pand %xmm6, %xmm0 530; SSE2-NEXT: pandn %xmm2, %xmm6 531; SSE2-NEXT: por %xmm6, %xmm0 532; SSE2-NEXT: movdqa %xmm3, %xmm2 533; SSE2-NEXT: pxor %xmm4, %xmm2 534; SSE2-NEXT: pxor %xmm1, %xmm4 535; SSE2-NEXT: movdqa %xmm4, %xmm5 536; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 537; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] 538; SSE2-NEXT: pcmpeqd %xmm2, %xmm4 539; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] 540; SSE2-NEXT: pand %xmm6, %xmm2 541; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] 542; SSE2-NEXT: por %xmm2, %xmm4 543; SSE2-NEXT: pand %xmm4, %xmm1 544; SSE2-NEXT: pandn %xmm3, %xmm4 545; SSE2-NEXT: por %xmm4, %xmm1 546; SSE2-NEXT: retq 547; 548; SSE41-LABEL: max_ge_v4i64: 549; SSE41: # %bb.0: 550; SSE41-NEXT: movdqa %xmm0, %xmm4 551; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259456,9223372039002259456] 552; SSE41-NEXT: movdqa %xmm2, %xmm6 553; SSE41-NEXT: pxor %xmm5, %xmm6 554; SSE41-NEXT: movdqa %xmm0, %xmm7 555; SSE41-NEXT: pxor %xmm5, %xmm7 556; SSE41-NEXT: movdqa %xmm7, %xmm0 557; SSE41-NEXT: pcmpgtd %xmm6, %xmm0 558; SSE41-NEXT: pshufd {{.*#+}} xmm8 = xmm0[0,0,2,2] 559; SSE41-NEXT: pcmpeqd %xmm6, %xmm7 560; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3] 561; SSE41-NEXT: pand %xmm8, %xmm6 562; SSE41-NEXT: por %xmm6, %xmm0 563; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm2 564; SSE41-NEXT: movdqa %xmm3, %xmm0 565; SSE41-NEXT: pxor %xmm5, %xmm0 566; SSE41-NEXT: pxor %xmm1, %xmm5 567; SSE41-NEXT: movdqa %xmm5, %xmm4 568; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 569; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2] 570; SSE41-NEXT: pcmpeqd %xmm0, %xmm5 571; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3] 572; SSE41-NEXT: pand %xmm6, %xmm0 573; SSE41-NEXT: por %xmm4, %xmm0 574; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3 575; SSE41-NEXT: movapd %xmm2, %xmm0 576; SSE41-NEXT: movapd %xmm3, %xmm1 577; SSE41-NEXT: retq 578; 579; SSE42-LABEL: max_ge_v4i64: 580; SSE42: # %bb.0: 581; SSE42-NEXT: movdqa %xmm0, %xmm4 582; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808] 583; SSE42-NEXT: movdqa %xmm2, %xmm6 584; SSE42-NEXT: pxor %xmm5, %xmm6 585; SSE42-NEXT: pxor %xmm5, %xmm0 586; SSE42-NEXT: pcmpgtq %xmm6, %xmm0 587; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm2 588; SSE42-NEXT: movdqa %xmm3, %xmm0 589; SSE42-NEXT: pxor %xmm5, %xmm0 590; SSE42-NEXT: pxor %xmm1, %xmm5 591; SSE42-NEXT: pcmpgtq %xmm0, %xmm5 592; SSE42-NEXT: movdqa %xmm5, %xmm0 593; SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm3 594; SSE42-NEXT: movapd %xmm2, %xmm0 595; SSE42-NEXT: movapd %xmm3, %xmm1 596; SSE42-NEXT: retq 597; 598; AVX1-LABEL: max_ge_v4i64: 599; AVX1: # %bb.0: 600; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 601; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] 602; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 603; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 604; AVX1-NEXT: vpxor %xmm3, %xmm4, %xmm4 605; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm2 606; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm4 607; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm3 608; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm3 609; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 610; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 611; AVX1-NEXT: retq 612; 613; AVX2-LABEL: max_ge_v4i64: 614; AVX2: # %bb.0: 615; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] 616; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 617; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 618; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2 619; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 620; AVX2-NEXT: retq 621; 622; AVX512-LABEL: max_ge_v4i64: 623; AVX512: # %bb.0: 624; AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 625; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 626; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 627; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 628; AVX512-NEXT: retq 629 %1 = icmp uge <4 x i64> %a, %b 630 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b 631 ret <4 x i64> %2 632} 633 634define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) { 635; SSE2-LABEL: max_ge_v4i32: 636; SSE2: # %bb.0: 637; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] 638; SSE2-NEXT: movdqa %xmm1, %xmm3 639; SSE2-NEXT: pxor %xmm2, %xmm3 640; SSE2-NEXT: pxor %xmm0, %xmm2 641; SSE2-NEXT: pcmpgtd %xmm3, %xmm2 642; SSE2-NEXT: pand %xmm2, %xmm0 643; SSE2-NEXT: pandn %xmm1, %xmm2 644; SSE2-NEXT: por %xmm2, %xmm0 645; SSE2-NEXT: retq 646; 647; SSE41-LABEL: max_ge_v4i32: 648; SSE41: # %bb.0: 649; SSE41-NEXT: pmaxud %xmm1, %xmm0 650; SSE41-NEXT: retq 651; 652; SSE42-LABEL: max_ge_v4i32: 653; SSE42: # %bb.0: 654; SSE42-NEXT: pmaxud %xmm1, %xmm0 655; SSE42-NEXT: retq 656; 657; AVX-LABEL: max_ge_v4i32: 658; AVX: # %bb.0: 659; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 660; AVX-NEXT: retq 661 %1 = icmp uge <4 x i32> %a, %b 662 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b 663 ret <4 x i32> %2 664} 665 666define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) { 667; SSE2-LABEL: max_ge_v8i32: 668; SSE2: # %bb.0: 669; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648] 670; SSE2-NEXT: movdqa %xmm2, %xmm6 671; SSE2-NEXT: pxor %xmm5, %xmm6 672; SSE2-NEXT: movdqa %xmm0, %xmm4 673; SSE2-NEXT: pxor %xmm5, %xmm4 674; SSE2-NEXT: pcmpgtd %xmm6, %xmm4 675; SSE2-NEXT: pand %xmm4, %xmm0 676; SSE2-NEXT: pandn %xmm2, %xmm4 677; SSE2-NEXT: por %xmm0, %xmm4 678; SSE2-NEXT: movdqa %xmm3, %xmm0 679; SSE2-NEXT: pxor %xmm5, %xmm0 680; SSE2-NEXT: pxor %xmm1, %xmm5 681; SSE2-NEXT: pcmpgtd %xmm0, %xmm5 682; SSE2-NEXT: pand %xmm5, %xmm1 683; SSE2-NEXT: pandn %xmm3, %xmm5 684; SSE2-NEXT: por %xmm5, %xmm1 685; SSE2-NEXT: movdqa %xmm4, %xmm0 686; SSE2-NEXT: retq 687; 688; SSE41-LABEL: max_ge_v8i32: 689; SSE41: # %bb.0: 690; SSE41-NEXT: pmaxud %xmm2, %xmm0 691; SSE41-NEXT: pmaxud %xmm3, %xmm1 692; SSE41-NEXT: retq 693; 694; SSE42-LABEL: max_ge_v8i32: 695; SSE42: # %bb.0: 696; SSE42-NEXT: pmaxud %xmm2, %xmm0 697; SSE42-NEXT: pmaxud %xmm3, %xmm1 698; SSE42-NEXT: retq 699; 700; AVX1-LABEL: max_ge_v8i32: 701; AVX1: # %bb.0: 702; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 703; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 704; AVX1-NEXT: vpmaxud %xmm2, %xmm3, %xmm2 705; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 706; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 707; AVX1-NEXT: retq 708; 709; AVX2-LABEL: max_ge_v8i32: 710; AVX2: # %bb.0: 711; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 712; AVX2-NEXT: retq 713; 714; AVX512-LABEL: max_ge_v8i32: 715; AVX512: # %bb.0: 716; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 717; AVX512-NEXT: retq 718 %1 = icmp uge <8 x i32> %a, %b 719 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b 720 ret <8 x i32> %2 721} 722 723define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) { 724; SSE2-LABEL: max_ge_v8i16: 725; SSE2: # %bb.0: 726; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] 727; SSE2-NEXT: pxor %xmm2, %xmm1 728; SSE2-NEXT: pxor %xmm2, %xmm0 729; SSE2-NEXT: pmaxsw %xmm1, %xmm0 730; SSE2-NEXT: pxor %xmm2, %xmm0 731; SSE2-NEXT: retq 732; 733; SSE41-LABEL: max_ge_v8i16: 734; SSE41: # %bb.0: 735; SSE41-NEXT: pmaxuw %xmm1, %xmm0 736; SSE41-NEXT: retq 737; 738; SSE42-LABEL: max_ge_v8i16: 739; SSE42: # %bb.0: 740; SSE42-NEXT: pmaxuw %xmm1, %xmm0 741; SSE42-NEXT: retq 742; 743; AVX-LABEL: max_ge_v8i16: 744; AVX: # %bb.0: 745; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 746; AVX-NEXT: retq 747 %1 = icmp uge <8 x i16> %a, %b 748 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b 749 ret <8 x i16> %2 750} 751 752define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) { 753; SSE2-LABEL: max_ge_v16i16: 754; SSE2: # %bb.0: 755; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768] 756; SSE2-NEXT: pxor %xmm4, %xmm2 757; SSE2-NEXT: pxor %xmm4, %xmm0 758; SSE2-NEXT: pmaxsw %xmm2, %xmm0 759; SSE2-NEXT: pxor %xmm4, %xmm0 760; SSE2-NEXT: pxor %xmm4, %xmm3 761; SSE2-NEXT: pxor %xmm4, %xmm1 762; SSE2-NEXT: pmaxsw %xmm3, %xmm1 763; SSE2-NEXT: pxor %xmm4, %xmm1 764; SSE2-NEXT: retq 765; 766; SSE41-LABEL: max_ge_v16i16: 767; SSE41: # %bb.0: 768; SSE41-NEXT: pmaxuw %xmm2, %xmm0 769; SSE41-NEXT: pmaxuw %xmm3, %xmm1 770; SSE41-NEXT: retq 771; 772; SSE42-LABEL: max_ge_v16i16: 773; SSE42: # %bb.0: 774; SSE42-NEXT: pmaxuw %xmm2, %xmm0 775; SSE42-NEXT: pmaxuw %xmm3, %xmm1 776; SSE42-NEXT: retq 777; 778; AVX1-LABEL: max_ge_v16i16: 779; AVX1: # %bb.0: 780; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 781; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 782; AVX1-NEXT: vpmaxuw %xmm2, %xmm3, %xmm2 783; AVX1-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 784; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 785; AVX1-NEXT: retq 786; 787; AVX2-LABEL: max_ge_v16i16: 788; AVX2: # %bb.0: 789; AVX2-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 790; AVX2-NEXT: retq 791; 792; AVX512-LABEL: max_ge_v16i16: 793; AVX512: # %bb.0: 794; AVX512-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 795; AVX512-NEXT: retq 796 %1 = icmp uge <16 x i16> %a, %b 797 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b 798 ret <16 x i16> %2 799} 800 801define <16 x i8> @max_ge_v16i8(<16 x i8> %a, <16 x i8> %b) { 802; SSE-LABEL: max_ge_v16i8: 803; SSE: # %bb.0: 804; SSE-NEXT: pmaxub %xmm1, %xmm0 805; SSE-NEXT: retq 806; 807; AVX-LABEL: max_ge_v16i8: 808; AVX: # %bb.0: 809; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 810; AVX-NEXT: retq 811 %1 = icmp uge <16 x i8> %a, %b 812 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b 813 ret <16 x i8> %2 814} 815 816define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) { 817; SSE-LABEL: max_ge_v32i8: 818; SSE: # %bb.0: 819; SSE-NEXT: pmaxub %xmm2, %xmm0 820; SSE-NEXT: pmaxub %xmm3, %xmm1 821; SSE-NEXT: retq 822; 823; AVX1-LABEL: max_ge_v32i8: 824; AVX1: # %bb.0: 825; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 826; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 827; AVX1-NEXT: vpmaxub %xmm2, %xmm3, %xmm2 828; AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 829; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 830; AVX1-NEXT: retq 831; 832; AVX2-LABEL: max_ge_v32i8: 833; AVX2: # %bb.0: 834; AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 835; AVX2-NEXT: retq 836; 837; AVX512-LABEL: max_ge_v32i8: 838; AVX512: # %bb.0: 839; AVX512-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 840; AVX512-NEXT: retq 841 %1 = icmp uge <32 x i8> %a, %b 842 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b 843 ret <32 x i8> %2 844} 845 846; 847; Unsigned Minimum (LT) 848; 849 850define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) { 851; SSE2-LABEL: min_lt_v2i64: 852; SSE2: # %bb.0: 853; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] 854; SSE2-NEXT: movdqa %xmm0, %xmm3 855; SSE2-NEXT: pxor %xmm2, %xmm3 856; SSE2-NEXT: pxor %xmm1, %xmm2 857; SSE2-NEXT: movdqa %xmm2, %xmm4 858; SSE2-NEXT: pcmpgtd %xmm3, %xmm4 859; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 860; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 861; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] 862; SSE2-NEXT: pand %xmm5, %xmm2 863; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] 864; SSE2-NEXT: por %xmm2, %xmm3 865; SSE2-NEXT: pand %xmm3, %xmm0 866; SSE2-NEXT: pandn %xmm1, %xmm3 867; SSE2-NEXT: por %xmm3, %xmm0 868; SSE2-NEXT: retq 869; 870; SSE41-LABEL: min_lt_v2i64: 871; SSE41: # %bb.0: 872; SSE41-NEXT: movdqa %xmm0, %xmm2 873; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456] 874; SSE41-NEXT: movdqa %xmm2, %xmm3 875; SSE41-NEXT: pxor %xmm0, %xmm3 876; SSE41-NEXT: pxor %xmm1, %xmm0 877; SSE41-NEXT: movdqa %xmm0, %xmm4 878; SSE41-NEXT: pcmpgtd %xmm3, %xmm4 879; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 880; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 881; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 882; SSE41-NEXT: pand %xmm5, %xmm0 883; SSE41-NEXT: por %xmm4, %xmm0 884; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 885; SSE41-NEXT: movapd %xmm1, %xmm0 886; SSE41-NEXT: retq 887; 888; SSE42-LABEL: min_lt_v2i64: 889; SSE42: # %bb.0: 890; SSE42-NEXT: movdqa %xmm0, %xmm2 891; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] 892; SSE42-NEXT: movdqa %xmm2, %xmm3 893; SSE42-NEXT: pxor %xmm0, %xmm3 894; SSE42-NEXT: pxor %xmm1, %xmm0 895; SSE42-NEXT: pcmpgtq %xmm3, %xmm0 896; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm1 897; SSE42-NEXT: movapd %xmm1, %xmm0 898; SSE42-NEXT: retq 899; 900; AVX1-LABEL: min_lt_v2i64: 901; AVX1: # %bb.0: 902; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 903; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3 904; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm2 905; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 906; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 907; AVX1-NEXT: retq 908; 909; AVX2-LABEL: min_lt_v2i64: 910; AVX2: # %bb.0: 911; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 912; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3 913; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 914; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 915; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 916; AVX2-NEXT: retq 917; 918; AVX512-LABEL: min_lt_v2i64: 919; AVX512: # %bb.0: 920; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 921; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 922; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 923; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 924; AVX512-NEXT: vzeroupper 925; AVX512-NEXT: retq 926 %1 = icmp ult <2 x i64> %a, %b 927 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b 928 ret <2 x i64> %2 929} 930 931define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) { 932; SSE2-LABEL: min_lt_v4i64: 933; SSE2: # %bb.0: 934; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] 935; SSE2-NEXT: movdqa %xmm0, %xmm5 936; SSE2-NEXT: pxor %xmm4, %xmm5 937; SSE2-NEXT: movdqa %xmm2, %xmm6 938; SSE2-NEXT: pxor %xmm4, %xmm6 939; SSE2-NEXT: movdqa %xmm6, %xmm7 940; SSE2-NEXT: pcmpgtd %xmm5, %xmm7 941; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2] 942; SSE2-NEXT: pcmpeqd %xmm5, %xmm6 943; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] 944; SSE2-NEXT: pand %xmm8, %xmm5 945; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3] 946; SSE2-NEXT: por %xmm5, %xmm6 947; SSE2-NEXT: pand %xmm6, %xmm0 948; SSE2-NEXT: pandn %xmm2, %xmm6 949; SSE2-NEXT: por %xmm6, %xmm0 950; SSE2-NEXT: movdqa %xmm1, %xmm2 951; SSE2-NEXT: pxor %xmm4, %xmm2 952; SSE2-NEXT: pxor %xmm3, %xmm4 953; SSE2-NEXT: movdqa %xmm4, %xmm5 954; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 955; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] 956; SSE2-NEXT: pcmpeqd %xmm2, %xmm4 957; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] 958; SSE2-NEXT: pand %xmm6, %xmm2 959; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] 960; SSE2-NEXT: por %xmm2, %xmm4 961; SSE2-NEXT: pand %xmm4, %xmm1 962; SSE2-NEXT: pandn %xmm3, %xmm4 963; SSE2-NEXT: por %xmm4, %xmm1 964; SSE2-NEXT: retq 965; 966; SSE41-LABEL: min_lt_v4i64: 967; SSE41: # %bb.0: 968; SSE41-NEXT: movdqa %xmm0, %xmm4 969; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259456,9223372039002259456] 970; SSE41-NEXT: pxor %xmm5, %xmm0 971; SSE41-NEXT: movdqa %xmm2, %xmm6 972; SSE41-NEXT: pxor %xmm5, %xmm6 973; SSE41-NEXT: movdqa %xmm6, %xmm7 974; SSE41-NEXT: pcmpgtd %xmm0, %xmm7 975; SSE41-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2] 976; SSE41-NEXT: pcmpeqd %xmm0, %xmm6 977; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] 978; SSE41-NEXT: pand %xmm8, %xmm0 979; SSE41-NEXT: por %xmm7, %xmm0 980; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm2 981; SSE41-NEXT: movdqa %xmm1, %xmm0 982; SSE41-NEXT: pxor %xmm5, %xmm0 983; SSE41-NEXT: pxor %xmm3, %xmm5 984; SSE41-NEXT: movdqa %xmm5, %xmm4 985; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 986; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2] 987; SSE41-NEXT: pcmpeqd %xmm0, %xmm5 988; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3] 989; SSE41-NEXT: pand %xmm6, %xmm0 990; SSE41-NEXT: por %xmm4, %xmm0 991; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3 992; SSE41-NEXT: movapd %xmm2, %xmm0 993; SSE41-NEXT: movapd %xmm3, %xmm1 994; SSE41-NEXT: retq 995; 996; SSE42-LABEL: min_lt_v4i64: 997; SSE42: # %bb.0: 998; SSE42-NEXT: movdqa %xmm0, %xmm4 999; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808] 1000; SSE42-NEXT: movdqa %xmm0, %xmm6 1001; SSE42-NEXT: pxor %xmm5, %xmm6 1002; SSE42-NEXT: movdqa %xmm2, %xmm0 1003; SSE42-NEXT: pxor %xmm5, %xmm0 1004; SSE42-NEXT: pcmpgtq %xmm6, %xmm0 1005; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm2 1006; SSE42-NEXT: movdqa %xmm1, %xmm0 1007; SSE42-NEXT: pxor %xmm5, %xmm0 1008; SSE42-NEXT: pxor %xmm3, %xmm5 1009; SSE42-NEXT: pcmpgtq %xmm0, %xmm5 1010; SSE42-NEXT: movdqa %xmm5, %xmm0 1011; SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm3 1012; SSE42-NEXT: movapd %xmm2, %xmm0 1013; SSE42-NEXT: movapd %xmm3, %xmm1 1014; SSE42-NEXT: retq 1015; 1016; AVX1-LABEL: min_lt_v4i64: 1017; AVX1: # %bb.0: 1018; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 1019; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] 1020; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 1021; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 1022; AVX1-NEXT: vpxor %xmm3, %xmm4, %xmm4 1023; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm2 1024; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm4 1025; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm3 1026; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm3 1027; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 1028; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 1029; AVX1-NEXT: retq 1030; 1031; AVX2-LABEL: min_lt_v4i64: 1032; AVX2: # %bb.0: 1033; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] 1034; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm3 1035; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm2 1036; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2 1037; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 1038; AVX2-NEXT: retq 1039; 1040; AVX512-LABEL: min_lt_v4i64: 1041; AVX512: # %bb.0: 1042; AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 1043; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 1044; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 1045; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 1046; AVX512-NEXT: retq 1047 %1 = icmp ult <4 x i64> %a, %b 1048 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b 1049 ret <4 x i64> %2 1050} 1051 1052define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) { 1053; SSE2-LABEL: min_lt_v4i32: 1054; SSE2: # %bb.0: 1055; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] 1056; SSE2-NEXT: movdqa %xmm0, %xmm3 1057; SSE2-NEXT: pxor %xmm2, %xmm3 1058; SSE2-NEXT: pxor %xmm1, %xmm2 1059; SSE2-NEXT: pcmpgtd %xmm3, %xmm2 1060; SSE2-NEXT: pand %xmm2, %xmm0 1061; SSE2-NEXT: pandn %xmm1, %xmm2 1062; SSE2-NEXT: por %xmm2, %xmm0 1063; SSE2-NEXT: retq 1064; 1065; SSE41-LABEL: min_lt_v4i32: 1066; SSE41: # %bb.0: 1067; SSE41-NEXT: pminud %xmm1, %xmm0 1068; SSE41-NEXT: retq 1069; 1070; SSE42-LABEL: min_lt_v4i32: 1071; SSE42: # %bb.0: 1072; SSE42-NEXT: pminud %xmm1, %xmm0 1073; SSE42-NEXT: retq 1074; 1075; AVX-LABEL: min_lt_v4i32: 1076; AVX: # %bb.0: 1077; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0 1078; AVX-NEXT: retq 1079 %1 = icmp ult <4 x i32> %a, %b 1080 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b 1081 ret <4 x i32> %2 1082} 1083 1084define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) { 1085; SSE2-LABEL: min_lt_v8i32: 1086; SSE2: # %bb.0: 1087; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] 1088; SSE2-NEXT: movdqa %xmm0, %xmm5 1089; SSE2-NEXT: pxor %xmm4, %xmm5 1090; SSE2-NEXT: movdqa %xmm2, %xmm6 1091; SSE2-NEXT: pxor %xmm4, %xmm6 1092; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 1093; SSE2-NEXT: pand %xmm6, %xmm0 1094; SSE2-NEXT: pandn %xmm2, %xmm6 1095; SSE2-NEXT: por %xmm6, %xmm0 1096; SSE2-NEXT: movdqa %xmm1, %xmm2 1097; SSE2-NEXT: pxor %xmm4, %xmm2 1098; SSE2-NEXT: pxor %xmm3, %xmm4 1099; SSE2-NEXT: pcmpgtd %xmm2, %xmm4 1100; SSE2-NEXT: pand %xmm4, %xmm1 1101; SSE2-NEXT: pandn %xmm3, %xmm4 1102; SSE2-NEXT: por %xmm4, %xmm1 1103; SSE2-NEXT: retq 1104; 1105; SSE41-LABEL: min_lt_v8i32: 1106; SSE41: # %bb.0: 1107; SSE41-NEXT: pminud %xmm2, %xmm0 1108; SSE41-NEXT: pminud %xmm3, %xmm1 1109; SSE41-NEXT: retq 1110; 1111; SSE42-LABEL: min_lt_v8i32: 1112; SSE42: # %bb.0: 1113; SSE42-NEXT: pminud %xmm2, %xmm0 1114; SSE42-NEXT: pminud %xmm3, %xmm1 1115; SSE42-NEXT: retq 1116; 1117; AVX1-LABEL: min_lt_v8i32: 1118; AVX1: # %bb.0: 1119; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 1120; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 1121; AVX1-NEXT: vpminud %xmm2, %xmm3, %xmm2 1122; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0 1123; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 1124; AVX1-NEXT: retq 1125; 1126; AVX2-LABEL: min_lt_v8i32: 1127; AVX2: # %bb.0: 1128; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0 1129; AVX2-NEXT: retq 1130; 1131; AVX512-LABEL: min_lt_v8i32: 1132; AVX512: # %bb.0: 1133; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0 1134; AVX512-NEXT: retq 1135 %1 = icmp ult <8 x i32> %a, %b 1136 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b 1137 ret <8 x i32> %2 1138} 1139 1140define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) { 1141; SSE2-LABEL: min_lt_v8i16: 1142; SSE2: # %bb.0: 1143; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] 1144; SSE2-NEXT: pxor %xmm2, %xmm1 1145; SSE2-NEXT: pxor %xmm2, %xmm0 1146; SSE2-NEXT: pminsw %xmm1, %xmm0 1147; SSE2-NEXT: pxor %xmm2, %xmm0 1148; SSE2-NEXT: retq 1149; 1150; SSE41-LABEL: min_lt_v8i16: 1151; SSE41: # %bb.0: 1152; SSE41-NEXT: pminuw %xmm1, %xmm0 1153; SSE41-NEXT: retq 1154; 1155; SSE42-LABEL: min_lt_v8i16: 1156; SSE42: # %bb.0: 1157; SSE42-NEXT: pminuw %xmm1, %xmm0 1158; SSE42-NEXT: retq 1159; 1160; AVX-LABEL: min_lt_v8i16: 1161; AVX: # %bb.0: 1162; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0 1163; AVX-NEXT: retq 1164 %1 = icmp ult <8 x i16> %a, %b 1165 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b 1166 ret <8 x i16> %2 1167} 1168 1169define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) { 1170; SSE2-LABEL: min_lt_v16i16: 1171; SSE2: # %bb.0: 1172; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768] 1173; SSE2-NEXT: pxor %xmm4, %xmm2 1174; SSE2-NEXT: pxor %xmm4, %xmm0 1175; SSE2-NEXT: pminsw %xmm2, %xmm0 1176; SSE2-NEXT: pxor %xmm4, %xmm0 1177; SSE2-NEXT: pxor %xmm4, %xmm3 1178; SSE2-NEXT: pxor %xmm4, %xmm1 1179; SSE2-NEXT: pminsw %xmm3, %xmm1 1180; SSE2-NEXT: pxor %xmm4, %xmm1 1181; SSE2-NEXT: retq 1182; 1183; SSE41-LABEL: min_lt_v16i16: 1184; SSE41: # %bb.0: 1185; SSE41-NEXT: pminuw %xmm2, %xmm0 1186; SSE41-NEXT: pminuw %xmm3, %xmm1 1187; SSE41-NEXT: retq 1188; 1189; SSE42-LABEL: min_lt_v16i16: 1190; SSE42: # %bb.0: 1191; SSE42-NEXT: pminuw %xmm2, %xmm0 1192; SSE42-NEXT: pminuw %xmm3, %xmm1 1193; SSE42-NEXT: retq 1194; 1195; AVX1-LABEL: min_lt_v16i16: 1196; AVX1: # %bb.0: 1197; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 1198; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 1199; AVX1-NEXT: vpminuw %xmm2, %xmm3, %xmm2 1200; AVX1-NEXT: vpminuw %xmm1, %xmm0, %xmm0 1201; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 1202; AVX1-NEXT: retq 1203; 1204; AVX2-LABEL: min_lt_v16i16: 1205; AVX2: # %bb.0: 1206; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm0 1207; AVX2-NEXT: retq 1208; 1209; AVX512-LABEL: min_lt_v16i16: 1210; AVX512: # %bb.0: 1211; AVX512-NEXT: vpminuw %ymm1, %ymm0, %ymm0 1212; AVX512-NEXT: retq 1213 %1 = icmp ult <16 x i16> %a, %b 1214 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b 1215 ret <16 x i16> %2 1216} 1217 1218define <16 x i8> @min_lt_v16i8(<16 x i8> %a, <16 x i8> %b) { 1219; SSE-LABEL: min_lt_v16i8: 1220; SSE: # %bb.0: 1221; SSE-NEXT: pminub %xmm1, %xmm0 1222; SSE-NEXT: retq 1223; 1224; AVX-LABEL: min_lt_v16i8: 1225; AVX: # %bb.0: 1226; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0 1227; AVX-NEXT: retq 1228 %1 = icmp ult <16 x i8> %a, %b 1229 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b 1230 ret <16 x i8> %2 1231} 1232 1233define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) { 1234; SSE-LABEL: min_lt_v32i8: 1235; SSE: # %bb.0: 1236; SSE-NEXT: pminub %xmm2, %xmm0 1237; SSE-NEXT: pminub %xmm3, %xmm1 1238; SSE-NEXT: retq 1239; 1240; AVX1-LABEL: min_lt_v32i8: 1241; AVX1: # %bb.0: 1242; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 1243; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 1244; AVX1-NEXT: vpminub %xmm2, %xmm3, %xmm2 1245; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0 1246; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 1247; AVX1-NEXT: retq 1248; 1249; AVX2-LABEL: min_lt_v32i8: 1250; AVX2: # %bb.0: 1251; AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 1252; AVX2-NEXT: retq 1253; 1254; AVX512-LABEL: min_lt_v32i8: 1255; AVX512: # %bb.0: 1256; AVX512-NEXT: vpminub %ymm1, %ymm0, %ymm0 1257; AVX512-NEXT: retq 1258 %1 = icmp ult <32 x i8> %a, %b 1259 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b 1260 ret <32 x i8> %2 1261} 1262 1263; 1264; Unsigned Minimum (LE) 1265; 1266 1267define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) { 1268; SSE2-LABEL: min_le_v2i64: 1269; SSE2: # %bb.0: 1270; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] 1271; SSE2-NEXT: movdqa %xmm0, %xmm3 1272; SSE2-NEXT: pxor %xmm2, %xmm3 1273; SSE2-NEXT: pxor %xmm1, %xmm2 1274; SSE2-NEXT: movdqa %xmm2, %xmm4 1275; SSE2-NEXT: pcmpgtd %xmm3, %xmm4 1276; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 1277; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 1278; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] 1279; SSE2-NEXT: pand %xmm5, %xmm2 1280; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] 1281; SSE2-NEXT: por %xmm2, %xmm3 1282; SSE2-NEXT: pand %xmm3, %xmm0 1283; SSE2-NEXT: pandn %xmm1, %xmm3 1284; SSE2-NEXT: por %xmm3, %xmm0 1285; SSE2-NEXT: retq 1286; 1287; SSE41-LABEL: min_le_v2i64: 1288; SSE41: # %bb.0: 1289; SSE41-NEXT: movdqa %xmm0, %xmm2 1290; SSE41-NEXT: movdqa {{.*#+}} xmm0 = [9223372039002259456,9223372039002259456] 1291; SSE41-NEXT: movdqa %xmm2, %xmm3 1292; SSE41-NEXT: pxor %xmm0, %xmm3 1293; SSE41-NEXT: pxor %xmm1, %xmm0 1294; SSE41-NEXT: movdqa %xmm0, %xmm4 1295; SSE41-NEXT: pcmpgtd %xmm3, %xmm4 1296; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] 1297; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 1298; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 1299; SSE41-NEXT: pand %xmm5, %xmm0 1300; SSE41-NEXT: por %xmm4, %xmm0 1301; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 1302; SSE41-NEXT: movapd %xmm1, %xmm0 1303; SSE41-NEXT: retq 1304; 1305; SSE42-LABEL: min_le_v2i64: 1306; SSE42: # %bb.0: 1307; SSE42-NEXT: movdqa %xmm0, %xmm2 1308; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808] 1309; SSE42-NEXT: movdqa %xmm2, %xmm3 1310; SSE42-NEXT: pxor %xmm0, %xmm3 1311; SSE42-NEXT: pxor %xmm1, %xmm0 1312; SSE42-NEXT: pcmpgtq %xmm3, %xmm0 1313; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm1 1314; SSE42-NEXT: movapd %xmm1, %xmm0 1315; SSE42-NEXT: retq 1316; 1317; AVX1-LABEL: min_le_v2i64: 1318; AVX1: # %bb.0: 1319; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 1320; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3 1321; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm2 1322; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 1323; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 1324; AVX1-NEXT: retq 1325; 1326; AVX2-LABEL: min_le_v2i64: 1327; AVX2: # %bb.0: 1328; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] 1329; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3 1330; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 1331; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 1332; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 1333; AVX2-NEXT: retq 1334; 1335; AVX512-LABEL: min_le_v2i64: 1336; AVX512: # %bb.0: 1337; AVX512-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 1338; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 1339; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 1340; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 1341; AVX512-NEXT: vzeroupper 1342; AVX512-NEXT: retq 1343 %1 = icmp ule <2 x i64> %a, %b 1344 %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b 1345 ret <2 x i64> %2 1346} 1347 1348define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) { 1349; SSE2-LABEL: min_le_v4i64: 1350; SSE2: # %bb.0: 1351; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] 1352; SSE2-NEXT: movdqa %xmm0, %xmm5 1353; SSE2-NEXT: pxor %xmm4, %xmm5 1354; SSE2-NEXT: movdqa %xmm2, %xmm6 1355; SSE2-NEXT: pxor %xmm4, %xmm6 1356; SSE2-NEXT: movdqa %xmm6, %xmm7 1357; SSE2-NEXT: pcmpgtd %xmm5, %xmm7 1358; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2] 1359; SSE2-NEXT: pcmpeqd %xmm5, %xmm6 1360; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] 1361; SSE2-NEXT: pand %xmm8, %xmm5 1362; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3] 1363; SSE2-NEXT: por %xmm5, %xmm6 1364; SSE2-NEXT: pand %xmm6, %xmm0 1365; SSE2-NEXT: pandn %xmm2, %xmm6 1366; SSE2-NEXT: por %xmm6, %xmm0 1367; SSE2-NEXT: movdqa %xmm1, %xmm2 1368; SSE2-NEXT: pxor %xmm4, %xmm2 1369; SSE2-NEXT: pxor %xmm3, %xmm4 1370; SSE2-NEXT: movdqa %xmm4, %xmm5 1371; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 1372; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] 1373; SSE2-NEXT: pcmpeqd %xmm2, %xmm4 1374; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] 1375; SSE2-NEXT: pand %xmm6, %xmm2 1376; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] 1377; SSE2-NEXT: por %xmm2, %xmm4 1378; SSE2-NEXT: pand %xmm4, %xmm1 1379; SSE2-NEXT: pandn %xmm3, %xmm4 1380; SSE2-NEXT: por %xmm4, %xmm1 1381; SSE2-NEXT: retq 1382; 1383; SSE41-LABEL: min_le_v4i64: 1384; SSE41: # %bb.0: 1385; SSE41-NEXT: movdqa %xmm0, %xmm4 1386; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [9223372039002259456,9223372039002259456] 1387; SSE41-NEXT: pxor %xmm5, %xmm0 1388; SSE41-NEXT: movdqa %xmm2, %xmm6 1389; SSE41-NEXT: pxor %xmm5, %xmm6 1390; SSE41-NEXT: movdqa %xmm6, %xmm7 1391; SSE41-NEXT: pcmpgtd %xmm0, %xmm7 1392; SSE41-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2] 1393; SSE41-NEXT: pcmpeqd %xmm0, %xmm6 1394; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] 1395; SSE41-NEXT: pand %xmm8, %xmm0 1396; SSE41-NEXT: por %xmm7, %xmm0 1397; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm2 1398; SSE41-NEXT: movdqa %xmm1, %xmm0 1399; SSE41-NEXT: pxor %xmm5, %xmm0 1400; SSE41-NEXT: pxor %xmm3, %xmm5 1401; SSE41-NEXT: movdqa %xmm5, %xmm4 1402; SSE41-NEXT: pcmpgtd %xmm0, %xmm4 1403; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2] 1404; SSE41-NEXT: pcmpeqd %xmm0, %xmm5 1405; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3] 1406; SSE41-NEXT: pand %xmm6, %xmm0 1407; SSE41-NEXT: por %xmm4, %xmm0 1408; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3 1409; SSE41-NEXT: movapd %xmm2, %xmm0 1410; SSE41-NEXT: movapd %xmm3, %xmm1 1411; SSE41-NEXT: retq 1412; 1413; SSE42-LABEL: min_le_v4i64: 1414; SSE42: # %bb.0: 1415; SSE42-NEXT: movdqa %xmm0, %xmm4 1416; SSE42-NEXT: movdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808] 1417; SSE42-NEXT: movdqa %xmm0, %xmm6 1418; SSE42-NEXT: pxor %xmm5, %xmm6 1419; SSE42-NEXT: movdqa %xmm2, %xmm0 1420; SSE42-NEXT: pxor %xmm5, %xmm0 1421; SSE42-NEXT: pcmpgtq %xmm6, %xmm0 1422; SSE42-NEXT: blendvpd %xmm0, %xmm4, %xmm2 1423; SSE42-NEXT: movdqa %xmm1, %xmm0 1424; SSE42-NEXT: pxor %xmm5, %xmm0 1425; SSE42-NEXT: pxor %xmm3, %xmm5 1426; SSE42-NEXT: pcmpgtq %xmm0, %xmm5 1427; SSE42-NEXT: movdqa %xmm5, %xmm0 1428; SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm3 1429; SSE42-NEXT: movapd %xmm2, %xmm0 1430; SSE42-NEXT: movapd %xmm3, %xmm1 1431; SSE42-NEXT: retq 1432; 1433; AVX1-LABEL: min_le_v4i64: 1434; AVX1: # %bb.0: 1435; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 1436; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] 1437; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm2 1438; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 1439; AVX1-NEXT: vpxor %xmm3, %xmm4, %xmm4 1440; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm2 1441; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm4 1442; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm3 1443; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm3 1444; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 1445; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 1446; AVX1-NEXT: retq 1447; 1448; AVX2-LABEL: min_le_v4i64: 1449; AVX2: # %bb.0: 1450; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] 1451; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm3 1452; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm2 1453; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2 1454; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 1455; AVX2-NEXT: retq 1456; 1457; AVX512-LABEL: min_le_v4i64: 1458; AVX512: # %bb.0: 1459; AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 1460; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 1461; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 1462; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 1463; AVX512-NEXT: retq 1464 %1 = icmp ule <4 x i64> %a, %b 1465 %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b 1466 ret <4 x i64> %2 1467} 1468 1469define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) { 1470; SSE2-LABEL: min_le_v4i32: 1471; SSE2: # %bb.0: 1472; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] 1473; SSE2-NEXT: movdqa %xmm0, %xmm3 1474; SSE2-NEXT: pxor %xmm2, %xmm3 1475; SSE2-NEXT: pxor %xmm1, %xmm2 1476; SSE2-NEXT: pcmpgtd %xmm3, %xmm2 1477; SSE2-NEXT: pand %xmm2, %xmm0 1478; SSE2-NEXT: pandn %xmm1, %xmm2 1479; SSE2-NEXT: por %xmm2, %xmm0 1480; SSE2-NEXT: retq 1481; 1482; SSE41-LABEL: min_le_v4i32: 1483; SSE41: # %bb.0: 1484; SSE41-NEXT: pminud %xmm1, %xmm0 1485; SSE41-NEXT: retq 1486; 1487; SSE42-LABEL: min_le_v4i32: 1488; SSE42: # %bb.0: 1489; SSE42-NEXT: pminud %xmm1, %xmm0 1490; SSE42-NEXT: retq 1491; 1492; AVX-LABEL: min_le_v4i32: 1493; AVX: # %bb.0: 1494; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0 1495; AVX-NEXT: retq 1496 %1 = icmp ule <4 x i32> %a, %b 1497 %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b 1498 ret <4 x i32> %2 1499} 1500 1501define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) { 1502; SSE2-LABEL: min_le_v8i32: 1503; SSE2: # %bb.0: 1504; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] 1505; SSE2-NEXT: movdqa %xmm0, %xmm5 1506; SSE2-NEXT: pxor %xmm4, %xmm5 1507; SSE2-NEXT: movdqa %xmm2, %xmm6 1508; SSE2-NEXT: pxor %xmm4, %xmm6 1509; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 1510; SSE2-NEXT: pand %xmm6, %xmm0 1511; SSE2-NEXT: pandn %xmm2, %xmm6 1512; SSE2-NEXT: por %xmm6, %xmm0 1513; SSE2-NEXT: movdqa %xmm1, %xmm2 1514; SSE2-NEXT: pxor %xmm4, %xmm2 1515; SSE2-NEXT: pxor %xmm3, %xmm4 1516; SSE2-NEXT: pcmpgtd %xmm2, %xmm4 1517; SSE2-NEXT: pand %xmm4, %xmm1 1518; SSE2-NEXT: pandn %xmm3, %xmm4 1519; SSE2-NEXT: por %xmm4, %xmm1 1520; SSE2-NEXT: retq 1521; 1522; SSE41-LABEL: min_le_v8i32: 1523; SSE41: # %bb.0: 1524; SSE41-NEXT: pminud %xmm2, %xmm0 1525; SSE41-NEXT: pminud %xmm3, %xmm1 1526; SSE41-NEXT: retq 1527; 1528; SSE42-LABEL: min_le_v8i32: 1529; SSE42: # %bb.0: 1530; SSE42-NEXT: pminud %xmm2, %xmm0 1531; SSE42-NEXT: pminud %xmm3, %xmm1 1532; SSE42-NEXT: retq 1533; 1534; AVX1-LABEL: min_le_v8i32: 1535; AVX1: # %bb.0: 1536; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 1537; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 1538; AVX1-NEXT: vpminud %xmm2, %xmm3, %xmm2 1539; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0 1540; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 1541; AVX1-NEXT: retq 1542; 1543; AVX2-LABEL: min_le_v8i32: 1544; AVX2: # %bb.0: 1545; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0 1546; AVX2-NEXT: retq 1547; 1548; AVX512-LABEL: min_le_v8i32: 1549; AVX512: # %bb.0: 1550; AVX512-NEXT: vpminud %ymm1, %ymm0, %ymm0 1551; AVX512-NEXT: retq 1552 %1 = icmp ule <8 x i32> %a, %b 1553 %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b 1554 ret <8 x i32> %2 1555} 1556 1557define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) { 1558; SSE2-LABEL: min_le_v8i16: 1559; SSE2: # %bb.0: 1560; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] 1561; SSE2-NEXT: pxor %xmm2, %xmm1 1562; SSE2-NEXT: pxor %xmm2, %xmm0 1563; SSE2-NEXT: pminsw %xmm1, %xmm0 1564; SSE2-NEXT: pxor %xmm2, %xmm0 1565; SSE2-NEXT: retq 1566; 1567; SSE41-LABEL: min_le_v8i16: 1568; SSE41: # %bb.0: 1569; SSE41-NEXT: pminuw %xmm1, %xmm0 1570; SSE41-NEXT: retq 1571; 1572; SSE42-LABEL: min_le_v8i16: 1573; SSE42: # %bb.0: 1574; SSE42-NEXT: pminuw %xmm1, %xmm0 1575; SSE42-NEXT: retq 1576; 1577; AVX-LABEL: min_le_v8i16: 1578; AVX: # %bb.0: 1579; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0 1580; AVX-NEXT: retq 1581 %1 = icmp ule <8 x i16> %a, %b 1582 %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b 1583 ret <8 x i16> %2 1584} 1585 1586define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) { 1587; SSE2-LABEL: min_le_v16i16: 1588; SSE2: # %bb.0: 1589; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768] 1590; SSE2-NEXT: pxor %xmm4, %xmm2 1591; SSE2-NEXT: pxor %xmm4, %xmm0 1592; SSE2-NEXT: pminsw %xmm2, %xmm0 1593; SSE2-NEXT: pxor %xmm4, %xmm0 1594; SSE2-NEXT: pxor %xmm4, %xmm3 1595; SSE2-NEXT: pxor %xmm4, %xmm1 1596; SSE2-NEXT: pminsw %xmm3, %xmm1 1597; SSE2-NEXT: pxor %xmm4, %xmm1 1598; SSE2-NEXT: retq 1599; 1600; SSE41-LABEL: min_le_v16i16: 1601; SSE41: # %bb.0: 1602; SSE41-NEXT: pminuw %xmm2, %xmm0 1603; SSE41-NEXT: pminuw %xmm3, %xmm1 1604; SSE41-NEXT: retq 1605; 1606; SSE42-LABEL: min_le_v16i16: 1607; SSE42: # %bb.0: 1608; SSE42-NEXT: pminuw %xmm2, %xmm0 1609; SSE42-NEXT: pminuw %xmm3, %xmm1 1610; SSE42-NEXT: retq 1611; 1612; AVX1-LABEL: min_le_v16i16: 1613; AVX1: # %bb.0: 1614; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 1615; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 1616; AVX1-NEXT: vpminuw %xmm2, %xmm3, %xmm2 1617; AVX1-NEXT: vpminuw %xmm1, %xmm0, %xmm0 1618; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 1619; AVX1-NEXT: retq 1620; 1621; AVX2-LABEL: min_le_v16i16: 1622; AVX2: # %bb.0: 1623; AVX2-NEXT: vpminuw %ymm1, %ymm0, %ymm0 1624; AVX2-NEXT: retq 1625; 1626; AVX512-LABEL: min_le_v16i16: 1627; AVX512: # %bb.0: 1628; AVX512-NEXT: vpminuw %ymm1, %ymm0, %ymm0 1629; AVX512-NEXT: retq 1630 %1 = icmp ule <16 x i16> %a, %b 1631 %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b 1632 ret <16 x i16> %2 1633} 1634 1635define <16 x i8> @min_le_v16i8(<16 x i8> %a, <16 x i8> %b) { 1636; SSE-LABEL: min_le_v16i8: 1637; SSE: # %bb.0: 1638; SSE-NEXT: pminub %xmm1, %xmm0 1639; SSE-NEXT: retq 1640; 1641; AVX-LABEL: min_le_v16i8: 1642; AVX: # %bb.0: 1643; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0 1644; AVX-NEXT: retq 1645 %1 = icmp ule <16 x i8> %a, %b 1646 %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b 1647 ret <16 x i8> %2 1648} 1649 1650define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) { 1651; SSE-LABEL: min_le_v32i8: 1652; SSE: # %bb.0: 1653; SSE-NEXT: pminub %xmm2, %xmm0 1654; SSE-NEXT: pminub %xmm3, %xmm1 1655; SSE-NEXT: retq 1656; 1657; AVX1-LABEL: min_le_v32i8: 1658; AVX1: # %bb.0: 1659; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 1660; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 1661; AVX1-NEXT: vpminub %xmm2, %xmm3, %xmm2 1662; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0 1663; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 1664; AVX1-NEXT: retq 1665; 1666; AVX2-LABEL: min_le_v32i8: 1667; AVX2: # %bb.0: 1668; AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 1669; AVX2-NEXT: retq 1670; 1671; AVX512-LABEL: min_le_v32i8: 1672; AVX512: # %bb.0: 1673; AVX512-NEXT: vpminub %ymm1, %ymm0, %ymm0 1674; AVX512-NEXT: retq 1675 %1 = icmp ule <32 x i8> %a, %b 1676 %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b 1677 ret <32 x i8> %2 1678} 1679 1680; 1681; Constant Folding 1682; 1683 1684define <2 x i64> @max_gt_v2i64c() { 1685; SSE-LABEL: max_gt_v2i64c: 1686; SSE: # %bb.0: 1687; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7] 1688; SSE-NEXT: retq 1689; 1690; AVX-LABEL: max_gt_v2i64c: 1691; AVX: # %bb.0: 1692; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7] 1693; AVX-NEXT: retq 1694 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 1695 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0 1696 %3 = icmp ugt <2 x i64> %1, %2 1697 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2 1698 ret <2 x i64> %4 1699} 1700 1701define <4 x i64> @max_gt_v4i64c() { 1702; SSE-LABEL: max_gt_v4i64c: 1703; SSE: # %bb.0: 1704; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] 1705; SSE-NEXT: pcmpeqd %xmm0, %xmm0 1706; SSE-NEXT: retq 1707; 1708; AVX-LABEL: max_gt_v4i64c: 1709; AVX: # %bb.0: 1710; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7] 1711; AVX-NEXT: retq 1712 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 1713 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0 1714 %3 = icmp ugt <4 x i64> %1, %2 1715 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2 1716 ret <4 x i64> %4 1717} 1718 1719define <4 x i32> @max_gt_v4i32c() { 1720; SSE-LABEL: max_gt_v4i32c: 1721; SSE: # %bb.0: 1722; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] 1723; SSE-NEXT: retq 1724; 1725; AVX-LABEL: max_gt_v4i32c: 1726; AVX: # %bb.0: 1727; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] 1728; AVX-NEXT: retq 1729 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 1730 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 1731 %3 = icmp ugt <4 x i32> %1, %2 1732 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 1733 ret <4 x i32> %4 1734} 1735 1736define <8 x i32> @max_gt_v8i32c() { 1737; SSE-LABEL: max_gt_v8i32c: 1738; SSE: # %bb.0: 1739; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295] 1740; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7] 1741; SSE-NEXT: retq 1742; 1743; AVX-LABEL: max_gt_v8i32c: 1744; AVX: # %bb.0: 1745; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7] 1746; AVX-NEXT: retq 1747 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 1748 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 1749 %3 = icmp ugt <8 x i32> %1, %2 1750 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 1751 ret <8 x i32> %4 1752} 1753 1754define <8 x i16> @max_gt_v8i16c() { 1755; SSE-LABEL: max_gt_v8i16c: 1756; SSE: # %bb.0: 1757; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] 1758; SSE-NEXT: retq 1759; 1760; AVX-LABEL: max_gt_v8i16c: 1761; AVX: # %bb.0: 1762; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] 1763; AVX-NEXT: retq 1764 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 1765 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 1766 %3 = icmp ugt <8 x i16> %1, %2 1767 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 1768 ret <8 x i16> %4 1769} 1770 1771define <16 x i16> @max_gt_v16i16c() { 1772; SSE-LABEL: max_gt_v16i16c: 1773; SSE: # %bb.0: 1774; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0] 1775; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8] 1776; SSE-NEXT: retq 1777; 1778; AVX-LABEL: max_gt_v16i16c: 1779; AVX: # %bb.0: 1780; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8] 1781; AVX-NEXT: retq 1782 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 1783 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 1784 %3 = icmp ugt <16 x i16> %1, %2 1785 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 1786 ret <16 x i16> %4 1787} 1788 1789define <16 x i8> @max_gt_v16i8c() { 1790; SSE-LABEL: max_gt_v16i8c: 1791; SSE: # %bb.0: 1792; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] 1793; SSE-NEXT: retq 1794; 1795; AVX-LABEL: max_gt_v16i8c: 1796; AVX: # %bb.0: 1797; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] 1798; AVX-NEXT: retq 1799 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 1800 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 1801 %3 = icmp ugt <16 x i8> %1, %2 1802 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 1803 ret <16 x i8> %4 1804} 1805 1806define <2 x i64> @max_ge_v2i64c() { 1807; SSE-LABEL: max_ge_v2i64c: 1808; SSE: # %bb.0: 1809; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551615,7] 1810; SSE-NEXT: retq 1811; 1812; AVX-LABEL: max_ge_v2i64c: 1813; AVX: # %bb.0: 1814; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551615,7] 1815; AVX-NEXT: retq 1816 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 1817 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0 1818 %3 = icmp uge <2 x i64> %1, %2 1819 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2 1820 ret <2 x i64> %4 1821} 1822 1823define <4 x i64> @max_ge_v4i64c() { 1824; SSE-LABEL: max_ge_v4i64c: 1825; SSE: # %bb.0: 1826; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] 1827; SSE-NEXT: pcmpeqd %xmm0, %xmm0 1828; SSE-NEXT: retq 1829; 1830; AVX-LABEL: max_ge_v4i64c: 1831; AVX: # %bb.0: 1832; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7] 1833; AVX-NEXT: retq 1834 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 1835 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0 1836 %3 = icmp uge <4 x i64> %1, %2 1837 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2 1838 ret <4 x i64> %4 1839} 1840 1841define <4 x i32> @max_ge_v4i32c() { 1842; SSE-LABEL: max_ge_v4i32c: 1843; SSE: # %bb.0: 1844; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] 1845; SSE-NEXT: retq 1846; 1847; AVX-LABEL: max_ge_v4i32c: 1848; AVX: # %bb.0: 1849; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7] 1850; AVX-NEXT: retq 1851 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 1852 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 1853 %3 = icmp uge <4 x i32> %1, %2 1854 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 1855 ret <4 x i32> %4 1856} 1857 1858define <8 x i32> @max_ge_v8i32c() { 1859; SSE-LABEL: max_ge_v8i32c: 1860; SSE: # %bb.0: 1861; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295] 1862; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,5,5,7] 1863; SSE-NEXT: retq 1864; 1865; AVX-LABEL: max_ge_v8i32c: 1866; AVX: # %bb.0: 1867; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7] 1868; AVX-NEXT: retq 1869 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 1870 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 1871 %3 = icmp uge <8 x i32> %1, %2 1872 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 1873 ret <8 x i32> %4 1874} 1875 1876define <8 x i16> @max_ge_v8i16c() { 1877; SSE-LABEL: max_ge_v8i16c: 1878; SSE: # %bb.0: 1879; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] 1880; SSE-NEXT: retq 1881; 1882; AVX-LABEL: max_ge_v8i16c: 1883; AVX: # %bb.0: 1884; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7] 1885; AVX-NEXT: retq 1886 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 1887 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 1888 %3 = icmp uge <8 x i16> %1, %2 1889 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 1890 ret <8 x i16> %4 1891} 1892 1893define <16 x i16> @max_ge_v16i16c() { 1894; SSE-LABEL: max_ge_v16i16c: 1895; SSE: # %bb.0: 1896; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0] 1897; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8] 1898; SSE-NEXT: retq 1899; 1900; AVX-LABEL: max_ge_v16i16c: 1901; AVX: # %bb.0: 1902; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8] 1903; AVX-NEXT: retq 1904 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 1905 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 1906 %3 = icmp uge <16 x i16> %1, %2 1907 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 1908 ret <16 x i16> %4 1909} 1910 1911define <16 x i8> @max_ge_v16i8c() { 1912; SSE-LABEL: max_ge_v16i8c: 1913; SSE: # %bb.0: 1914; SSE-NEXT: movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] 1915; SSE-NEXT: retq 1916; 1917; AVX-LABEL: max_ge_v16i8c: 1918; AVX: # %bb.0: 1919; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8] 1920; AVX-NEXT: retq 1921 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 1922 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 1923 %3 = icmp uge <16 x i8> %1, %2 1924 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 1925 ret <16 x i8> %4 1926} 1927 1928define <2 x i64> @min_lt_v2i64c() { 1929; SSE-LABEL: min_lt_v2i64c: 1930; SSE: # %bb.0: 1931; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1] 1932; SSE-NEXT: retq 1933; 1934; AVX-LABEL: min_lt_v2i64c: 1935; AVX: # %bb.0: 1936; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1] 1937; AVX-NEXT: retq 1938 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 1939 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0 1940 %3 = icmp ult <2 x i64> %1, %2 1941 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2 1942 ret <2 x i64> %4 1943} 1944 1945define <4 x i64> @min_lt_v4i64c() { 1946; SSE-LABEL: min_lt_v4i64c: 1947; SSE: # %bb.0: 1948; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609] 1949; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1] 1950; SSE-NEXT: retq 1951; 1952; AVX-LABEL: min_lt_v4i64c: 1953; AVX: # %bb.0: 1954; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1] 1955; AVX-NEXT: retq 1956 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 1957 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0 1958 %3 = icmp ult <4 x i64> %1, %2 1959 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2 1960 ret <4 x i64> %4 1961} 1962 1963define <4 x i32> @min_lt_v4i32c() { 1964; SSE-LABEL: min_lt_v4i32c: 1965; SSE: # %bb.0: 1966; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] 1967; SSE-NEXT: retq 1968; 1969; AVX-LABEL: min_lt_v4i32c: 1970; AVX: # %bb.0: 1971; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] 1972; AVX-NEXT: retq 1973 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 1974 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 1975 %3 = icmp ult <4 x i32> %1, %2 1976 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 1977 ret <4 x i32> %4 1978} 1979 1980define <8 x i32> @min_lt_v8i32c() { 1981; SSE-LABEL: min_lt_v8i32c: 1982; SSE: # %bb.0: 1983; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289] 1984; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1] 1985; SSE-NEXT: retq 1986; 1987; AVX-LABEL: min_lt_v8i32c: 1988; AVX: # %bb.0: 1989; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1] 1990; AVX-NEXT: retq 1991 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 1992 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 1993 %3 = icmp ult <8 x i32> %1, %2 1994 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 1995 ret <8 x i32> %4 1996} 1997 1998define <8 x i16> @min_lt_v8i16c() { 1999; SSE-LABEL: min_lt_v8i16c: 2000; SSE: # %bb.0: 2001; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1] 2002; SSE-NEXT: retq 2003; 2004; AVX-LABEL: min_lt_v8i16c: 2005; AVX: # %bb.0: 2006; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,65531,65531,65529,1,3,3,1] 2007; AVX-NEXT: retq 2008 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 2009 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 1, i32 0 2010 %3 = icmp ult <8 x i16> %1, %2 2011 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 2012 ret <8 x i16> %4 2013} 2014 2015define <16 x i16> @min_lt_v16i16c() { 2016; SSE-LABEL: min_lt_v16i16c: 2017; SSE: # %bb.0: 2018; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,65530,65531,65532,65531,65530,65529,0] 2019; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0] 2020; SSE-NEXT: retq 2021; 2022; AVX-LABEL: min_lt_v16i16c: 2023; AVX: # %bb.0: 2024; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [1,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0] 2025; AVX-NEXT: retq 2026 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 2027 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 1, i32 0 2028 %3 = icmp ult <16 x i16> %1, %2 2029 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 2030 ret <16 x i16> %4 2031} 2032 2033define <16 x i8> @min_lt_v16i8c() { 2034; SSE-LABEL: min_lt_v16i8c: 2035; SSE: # %bb.0: 2036; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] 2037; SSE-NEXT: retq 2038; 2039; AVX-LABEL: min_lt_v16i8c: 2040; AVX: # %bb.0: 2041; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] 2042; AVX-NEXT: retq 2043 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 2044 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 1, i32 0 2045 %3 = icmp ult <16 x i8> %1, %2 2046 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 2047 ret <16 x i8> %4 2048} 2049 2050define <2 x i64> @min_le_v2i64c() { 2051; SSE-LABEL: min_le_v2i64c: 2052; SSE: # %bb.0: 2053; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,1] 2054; SSE-NEXT: retq 2055; 2056; AVX-LABEL: min_le_v2i64c: 2057; AVX: # %bb.0: 2058; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [18446744073709551609,1] 2059; AVX-NEXT: retq 2060 %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0 2061 %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0 2062 %3 = icmp ule <2 x i64> %1, %2 2063 %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2 2064 ret <2 x i64> %4 2065} 2066 2067define <4 x i64> @min_le_v4i64c() { 2068; SSE-LABEL: min_le_v4i64c: 2069; SSE: # %bb.0: 2070; SSE-NEXT: movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609] 2071; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,1] 2072; SSE-NEXT: retq 2073; 2074; AVX-LABEL: min_le_v4i64c: 2075; AVX: # %bb.0: 2076; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1] 2077; AVX-NEXT: retq 2078 %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0 2079 %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0 2080 %3 = icmp ule <4 x i64> %1, %2 2081 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2 2082 ret <4 x i64> %4 2083} 2084 2085define <4 x i32> @min_le_v4i32c() { 2086; SSE-LABEL: min_le_v4i32c: 2087; SSE: # %bb.0: 2088; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] 2089; SSE-NEXT: retq 2090; 2091; AVX-LABEL: min_le_v4i32c: 2092; AVX: # %bb.0: 2093; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1] 2094; AVX-NEXT: retq 2095 %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0 2096 %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0 2097 %3 = icmp ule <4 x i32> %1, %2 2098 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 2099 ret <4 x i32> %4 2100} 2101 2102define <8 x i32> @min_le_v8i32c() { 2103; SSE-LABEL: min_le_v8i32c: 2104; SSE: # %bb.0: 2105; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289] 2106; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,3,3,1] 2107; SSE-NEXT: retq 2108; 2109; AVX-LABEL: min_le_v8i32c: 2110; AVX: # %bb.0: 2111; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1] 2112; AVX-NEXT: retq 2113 %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0 2114 %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0 2115 %3 = icmp ule <8 x i32> %1, %2 2116 %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2 2117 ret <8 x i32> %4 2118} 2119 2120define <8 x i16> @min_le_v8i16c() { 2121; SSE-LABEL: min_le_v8i16c: 2122; SSE: # %bb.0: 2123; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1] 2124; SSE-NEXT: retq 2125; 2126; AVX-LABEL: min_le_v8i16c: 2127; AVX: # %bb.0: 2128; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1] 2129; AVX-NEXT: retq 2130 %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0 2131 %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0 2132 %3 = icmp ule <8 x i16> %1, %2 2133 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 2134 ret <8 x i16> %4 2135} 2136 2137define <16 x i16> @min_le_v16i16c() { 2138; SSE-LABEL: min_le_v16i16c: 2139; SSE: # %bb.0: 2140; SSE-NEXT: movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0] 2141; SSE-NEXT: movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0] 2142; SSE-NEXT: retq 2143; 2144; AVX-LABEL: min_le_v16i16c: 2145; AVX: # %bb.0: 2146; AVX-NEXT: vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0] 2147; AVX-NEXT: retq 2148 %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0 2149 %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0 2150 %3 = icmp ule <16 x i16> %1, %2 2151 %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2 2152 ret <16 x i16> %4 2153} 2154 2155define <16 x i8> @min_le_v16i8c() { 2156; SSE-LABEL: min_le_v16i8c: 2157; SSE: # %bb.0: 2158; SSE-NEXT: movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] 2159; SSE-NEXT: retq 2160; 2161; AVX-LABEL: min_le_v16i8c: 2162; AVX: # %bb.0: 2163; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0] 2164; AVX-NEXT: retq 2165 %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0 2166 %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0 2167 %3 = icmp ule <16 x i8> %1, %2 2168 %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2 2169 ret <16 x i8> %4 2170} 2171