1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512
8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512
9
10;
11; Signed Maximum (GT)
12;
13
14define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) {
15; SSE2-LABEL: max_gt_v2i64:
16; SSE2:       # %bb.0:
17; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
18; SSE2-NEXT:    movdqa %xmm1, %xmm3
19; SSE2-NEXT:    pxor %xmm2, %xmm3
20; SSE2-NEXT:    pxor %xmm0, %xmm2
21; SSE2-NEXT:    movdqa %xmm2, %xmm4
22; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
23; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
24; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
25; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
26; SSE2-NEXT:    pand %xmm5, %xmm2
27; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
28; SSE2-NEXT:    por %xmm2, %xmm3
29; SSE2-NEXT:    pand %xmm3, %xmm0
30; SSE2-NEXT:    pandn %xmm1, %xmm3
31; SSE2-NEXT:    por %xmm3, %xmm0
32; SSE2-NEXT:    retq
33;
34; SSE41-LABEL: max_gt_v2i64:
35; SSE41:       # %bb.0:
36; SSE41-NEXT:    movdqa %xmm0, %xmm2
37; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
38; SSE41-NEXT:    movdqa %xmm1, %xmm0
39; SSE41-NEXT:    pxor %xmm3, %xmm0
40; SSE41-NEXT:    pxor %xmm2, %xmm3
41; SSE41-NEXT:    movdqa %xmm3, %xmm4
42; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
43; SSE41-NEXT:    pcmpgtd %xmm0, %xmm3
44; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
45; SSE41-NEXT:    pand %xmm4, %xmm0
46; SSE41-NEXT:    por %xmm3, %xmm0
47; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
48; SSE41-NEXT:    movapd %xmm1, %xmm0
49; SSE41-NEXT:    retq
50;
51; SSE42-LABEL: max_gt_v2i64:
52; SSE42:       # %bb.0:
53; SSE42-NEXT:    movdqa %xmm0, %xmm2
54; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
55; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
56; SSE42-NEXT:    movapd %xmm1, %xmm0
57; SSE42-NEXT:    retq
58;
59; AVX1-LABEL: max_gt_v2i64:
60; AVX1:       # %bb.0:
61; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
62; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
63; AVX1-NEXT:    retq
64;
65; AVX2-LABEL: max_gt_v2i64:
66; AVX2:       # %bb.0:
67; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
68; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
69; AVX2-NEXT:    retq
70;
71; AVX512-LABEL: max_gt_v2i64:
72; AVX512:       # %bb.0:
73; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
74; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
75; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
76; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
77; AVX512-NEXT:    vzeroupper
78; AVX512-NEXT:    retq
79  %1 = icmp sgt <2 x i64> %a, %b
80  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
81  ret <2 x i64> %2
82}
83
84define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) {
85; SSE2-LABEL: max_gt_v4i64:
86; SSE2:       # %bb.0:
87; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
88; SSE2-NEXT:    movdqa %xmm2, %xmm5
89; SSE2-NEXT:    pxor %xmm4, %xmm5
90; SSE2-NEXT:    movdqa %xmm0, %xmm6
91; SSE2-NEXT:    pxor %xmm4, %xmm6
92; SSE2-NEXT:    movdqa %xmm6, %xmm7
93; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
94; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
95; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
96; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
97; SSE2-NEXT:    pand %xmm8, %xmm5
98; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
99; SSE2-NEXT:    por %xmm5, %xmm6
100; SSE2-NEXT:    pand %xmm6, %xmm0
101; SSE2-NEXT:    pandn %xmm2, %xmm6
102; SSE2-NEXT:    por %xmm6, %xmm0
103; SSE2-NEXT:    movdqa %xmm3, %xmm2
104; SSE2-NEXT:    pxor %xmm4, %xmm2
105; SSE2-NEXT:    pxor %xmm1, %xmm4
106; SSE2-NEXT:    movdqa %xmm4, %xmm5
107; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
108; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
109; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
110; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
111; SSE2-NEXT:    pand %xmm6, %xmm2
112; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
113; SSE2-NEXT:    por %xmm2, %xmm4
114; SSE2-NEXT:    pand %xmm4, %xmm1
115; SSE2-NEXT:    pandn %xmm3, %xmm4
116; SSE2-NEXT:    por %xmm4, %xmm1
117; SSE2-NEXT:    retq
118;
119; SSE41-LABEL: max_gt_v4i64:
120; SSE41:       # %bb.0:
121; SSE41-NEXT:    movdqa %xmm0, %xmm4
122; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
123; SSE41-NEXT:    movdqa %xmm2, %xmm0
124; SSE41-NEXT:    pxor %xmm5, %xmm0
125; SSE41-NEXT:    movdqa %xmm4, %xmm6
126; SSE41-NEXT:    pxor %xmm5, %xmm6
127; SSE41-NEXT:    movdqa %xmm6, %xmm7
128; SSE41-NEXT:    pcmpeqd %xmm0, %xmm7
129; SSE41-NEXT:    pcmpgtd %xmm0, %xmm6
130; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
131; SSE41-NEXT:    pand %xmm7, %xmm0
132; SSE41-NEXT:    por %xmm6, %xmm0
133; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
134; SSE41-NEXT:    movdqa %xmm3, %xmm0
135; SSE41-NEXT:    pxor %xmm5, %xmm0
136; SSE41-NEXT:    pxor %xmm1, %xmm5
137; SSE41-NEXT:    movdqa %xmm5, %xmm4
138; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
139; SSE41-NEXT:    pcmpgtd %xmm0, %xmm5
140; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[0,0,2,2]
141; SSE41-NEXT:    pand %xmm4, %xmm0
142; SSE41-NEXT:    por %xmm5, %xmm0
143; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
144; SSE41-NEXT:    movapd %xmm2, %xmm0
145; SSE41-NEXT:    movapd %xmm3, %xmm1
146; SSE41-NEXT:    retq
147;
148; SSE42-LABEL: max_gt_v4i64:
149; SSE42:       # %bb.0:
150; SSE42-NEXT:    movdqa %xmm0, %xmm4
151; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
152; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
153; SSE42-NEXT:    movdqa %xmm1, %xmm0
154; SSE42-NEXT:    pcmpgtq %xmm3, %xmm0
155; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
156; SSE42-NEXT:    movapd %xmm2, %xmm0
157; SSE42-NEXT:    movapd %xmm3, %xmm1
158; SSE42-NEXT:    retq
159;
160; AVX1-LABEL: max_gt_v4i64:
161; AVX1:       # %bb.0:
162; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
163; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
164; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
165; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm3
166; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
167; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
168; AVX1-NEXT:    retq
169;
170; AVX2-LABEL: max_gt_v4i64:
171; AVX2:       # %bb.0:
172; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
173; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
174; AVX2-NEXT:    retq
175;
176; AVX512-LABEL: max_gt_v4i64:
177; AVX512:       # %bb.0:
178; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
179; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
180; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
181; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
182; AVX512-NEXT:    retq
183  %1 = icmp sgt <4 x i64> %a, %b
184  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
185  ret <4 x i64> %2
186}
187
188define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) {
189; SSE2-LABEL: max_gt_v4i32:
190; SSE2:       # %bb.0:
191; SSE2-NEXT:    movdqa %xmm0, %xmm2
192; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
193; SSE2-NEXT:    pand %xmm2, %xmm0
194; SSE2-NEXT:    pandn %xmm1, %xmm2
195; SSE2-NEXT:    por %xmm2, %xmm0
196; SSE2-NEXT:    retq
197;
198; SSE41-LABEL: max_gt_v4i32:
199; SSE41:       # %bb.0:
200; SSE41-NEXT:    pmaxsd %xmm1, %xmm0
201; SSE41-NEXT:    retq
202;
203; SSE42-LABEL: max_gt_v4i32:
204; SSE42:       # %bb.0:
205; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
206; SSE42-NEXT:    retq
207;
208; AVX-LABEL: max_gt_v4i32:
209; AVX:       # %bb.0:
210; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
211; AVX-NEXT:    retq
212  %1 = icmp sgt <4 x i32> %a, %b
213  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
214  ret <4 x i32> %2
215}
216
217define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) {
218; SSE2-LABEL: max_gt_v8i32:
219; SSE2:       # %bb.0:
220; SSE2-NEXT:    movdqa %xmm0, %xmm4
221; SSE2-NEXT:    pcmpgtd %xmm2, %xmm4
222; SSE2-NEXT:    pand %xmm4, %xmm0
223; SSE2-NEXT:    pandn %xmm2, %xmm4
224; SSE2-NEXT:    por %xmm4, %xmm0
225; SSE2-NEXT:    movdqa %xmm1, %xmm2
226; SSE2-NEXT:    pcmpgtd %xmm3, %xmm2
227; SSE2-NEXT:    pand %xmm2, %xmm1
228; SSE2-NEXT:    pandn %xmm3, %xmm2
229; SSE2-NEXT:    por %xmm2, %xmm1
230; SSE2-NEXT:    retq
231;
232; SSE41-LABEL: max_gt_v8i32:
233; SSE41:       # %bb.0:
234; SSE41-NEXT:    pmaxsd %xmm2, %xmm0
235; SSE41-NEXT:    pmaxsd %xmm3, %xmm1
236; SSE41-NEXT:    retq
237;
238; SSE42-LABEL: max_gt_v8i32:
239; SSE42:       # %bb.0:
240; SSE42-NEXT:    pmaxsd %xmm2, %xmm0
241; SSE42-NEXT:    pmaxsd %xmm3, %xmm1
242; SSE42-NEXT:    retq
243;
244; AVX1-LABEL: max_gt_v8i32:
245; AVX1:       # %bb.0:
246; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
247; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
248; AVX1-NEXT:    vpmaxsd %xmm2, %xmm3, %xmm2
249; AVX1-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
250; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
251; AVX1-NEXT:    retq
252;
253; AVX2-LABEL: max_gt_v8i32:
254; AVX2:       # %bb.0:
255; AVX2-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
256; AVX2-NEXT:    retq
257;
258; AVX512-LABEL: max_gt_v8i32:
259; AVX512:       # %bb.0:
260; AVX512-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
261; AVX512-NEXT:    retq
262  %1 = icmp sgt <8 x i32> %a, %b
263  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
264  ret <8 x i32> %2
265}
266
267define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) {
268; SSE-LABEL: max_gt_v8i16:
269; SSE:       # %bb.0:
270; SSE-NEXT:    pmaxsw %xmm1, %xmm0
271; SSE-NEXT:    retq
272;
273; AVX-LABEL: max_gt_v8i16:
274; AVX:       # %bb.0:
275; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
276; AVX-NEXT:    retq
277  %1 = icmp sgt <8 x i16> %a, %b
278  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
279  ret <8 x i16> %2
280}
281
282define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) {
283; SSE-LABEL: max_gt_v16i16:
284; SSE:       # %bb.0:
285; SSE-NEXT:    pmaxsw %xmm2, %xmm0
286; SSE-NEXT:    pmaxsw %xmm3, %xmm1
287; SSE-NEXT:    retq
288;
289; AVX1-LABEL: max_gt_v16i16:
290; AVX1:       # %bb.0:
291; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
292; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
293; AVX1-NEXT:    vpmaxsw %xmm2, %xmm3, %xmm2
294; AVX1-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
295; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
296; AVX1-NEXT:    retq
297;
298; AVX2-LABEL: max_gt_v16i16:
299; AVX2:       # %bb.0:
300; AVX2-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
301; AVX2-NEXT:    retq
302;
303; AVX512-LABEL: max_gt_v16i16:
304; AVX512:       # %bb.0:
305; AVX512-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
306; AVX512-NEXT:    retq
307  %1 = icmp sgt <16 x i16> %a, %b
308  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
309  ret <16 x i16> %2
310}
311
312define <16 x i8> @max_gt_v16i8(<16 x i8> %a, <16 x i8> %b) {
313; SSE2-LABEL: max_gt_v16i8:
314; SSE2:       # %bb.0:
315; SSE2-NEXT:    movdqa %xmm0, %xmm2
316; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
317; SSE2-NEXT:    pand %xmm2, %xmm0
318; SSE2-NEXT:    pandn %xmm1, %xmm2
319; SSE2-NEXT:    por %xmm2, %xmm0
320; SSE2-NEXT:    retq
321;
322; SSE41-LABEL: max_gt_v16i8:
323; SSE41:       # %bb.0:
324; SSE41-NEXT:    pmaxsb %xmm1, %xmm0
325; SSE41-NEXT:    retq
326;
327; SSE42-LABEL: max_gt_v16i8:
328; SSE42:       # %bb.0:
329; SSE42-NEXT:    pmaxsb %xmm1, %xmm0
330; SSE42-NEXT:    retq
331;
332; AVX-LABEL: max_gt_v16i8:
333; AVX:       # %bb.0:
334; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
335; AVX-NEXT:    retq
336  %1 = icmp sgt <16 x i8> %a, %b
337  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
338  ret <16 x i8> %2
339}
340
341define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) {
342; SSE2-LABEL: max_gt_v32i8:
343; SSE2:       # %bb.0:
344; SSE2-NEXT:    movdqa %xmm0, %xmm4
345; SSE2-NEXT:    pcmpgtb %xmm2, %xmm4
346; SSE2-NEXT:    pand %xmm4, %xmm0
347; SSE2-NEXT:    pandn %xmm2, %xmm4
348; SSE2-NEXT:    por %xmm4, %xmm0
349; SSE2-NEXT:    movdqa %xmm1, %xmm2
350; SSE2-NEXT:    pcmpgtb %xmm3, %xmm2
351; SSE2-NEXT:    pand %xmm2, %xmm1
352; SSE2-NEXT:    pandn %xmm3, %xmm2
353; SSE2-NEXT:    por %xmm2, %xmm1
354; SSE2-NEXT:    retq
355;
356; SSE41-LABEL: max_gt_v32i8:
357; SSE41:       # %bb.0:
358; SSE41-NEXT:    pmaxsb %xmm2, %xmm0
359; SSE41-NEXT:    pmaxsb %xmm3, %xmm1
360; SSE41-NEXT:    retq
361;
362; SSE42-LABEL: max_gt_v32i8:
363; SSE42:       # %bb.0:
364; SSE42-NEXT:    pmaxsb %xmm2, %xmm0
365; SSE42-NEXT:    pmaxsb %xmm3, %xmm1
366; SSE42-NEXT:    retq
367;
368; AVX1-LABEL: max_gt_v32i8:
369; AVX1:       # %bb.0:
370; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
371; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
372; AVX1-NEXT:    vpmaxsb %xmm2, %xmm3, %xmm2
373; AVX1-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
374; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
375; AVX1-NEXT:    retq
376;
377; AVX2-LABEL: max_gt_v32i8:
378; AVX2:       # %bb.0:
379; AVX2-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
380; AVX2-NEXT:    retq
381;
382; AVX512-LABEL: max_gt_v32i8:
383; AVX512:       # %bb.0:
384; AVX512-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
385; AVX512-NEXT:    retq
386  %1 = icmp sgt <32 x i8> %a, %b
387  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
388  ret <32 x i8> %2
389}
390
391;
392; Signed Maximum (GE)
393;
394
395define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) {
396; SSE2-LABEL: max_ge_v2i64:
397; SSE2:       # %bb.0:
398; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
399; SSE2-NEXT:    movdqa %xmm1, %xmm3
400; SSE2-NEXT:    pxor %xmm2, %xmm3
401; SSE2-NEXT:    pxor %xmm0, %xmm2
402; SSE2-NEXT:    movdqa %xmm2, %xmm4
403; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
404; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
405; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
406; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
407; SSE2-NEXT:    pand %xmm5, %xmm2
408; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
409; SSE2-NEXT:    por %xmm2, %xmm3
410; SSE2-NEXT:    pand %xmm3, %xmm0
411; SSE2-NEXT:    pandn %xmm1, %xmm3
412; SSE2-NEXT:    por %xmm3, %xmm0
413; SSE2-NEXT:    retq
414;
415; SSE41-LABEL: max_ge_v2i64:
416; SSE41:       # %bb.0:
417; SSE41-NEXT:    movdqa %xmm0, %xmm2
418; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
419; SSE41-NEXT:    movdqa %xmm1, %xmm0
420; SSE41-NEXT:    pxor %xmm3, %xmm0
421; SSE41-NEXT:    pxor %xmm2, %xmm3
422; SSE41-NEXT:    movdqa %xmm3, %xmm4
423; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
424; SSE41-NEXT:    pcmpgtd %xmm0, %xmm3
425; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
426; SSE41-NEXT:    pand %xmm4, %xmm0
427; SSE41-NEXT:    por %xmm3, %xmm0
428; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
429; SSE41-NEXT:    movapd %xmm1, %xmm0
430; SSE41-NEXT:    retq
431;
432; SSE42-LABEL: max_ge_v2i64:
433; SSE42:       # %bb.0:
434; SSE42-NEXT:    movdqa %xmm0, %xmm2
435; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
436; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
437; SSE42-NEXT:    movapd %xmm1, %xmm0
438; SSE42-NEXT:    retq
439;
440; AVX1-LABEL: max_ge_v2i64:
441; AVX1:       # %bb.0:
442; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
443; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
444; AVX1-NEXT:    retq
445;
446; AVX2-LABEL: max_ge_v2i64:
447; AVX2:       # %bb.0:
448; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
449; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
450; AVX2-NEXT:    retq
451;
452; AVX512-LABEL: max_ge_v2i64:
453; AVX512:       # %bb.0:
454; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
455; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
456; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
457; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
458; AVX512-NEXT:    vzeroupper
459; AVX512-NEXT:    retq
460  %1 = icmp sge <2 x i64> %a, %b
461  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
462  ret <2 x i64> %2
463}
464
465define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) {
466; SSE2-LABEL: max_ge_v4i64:
467; SSE2:       # %bb.0:
468; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
469; SSE2-NEXT:    movdqa %xmm2, %xmm5
470; SSE2-NEXT:    pxor %xmm4, %xmm5
471; SSE2-NEXT:    movdqa %xmm0, %xmm6
472; SSE2-NEXT:    pxor %xmm4, %xmm6
473; SSE2-NEXT:    movdqa %xmm6, %xmm7
474; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
475; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
476; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
477; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
478; SSE2-NEXT:    pand %xmm8, %xmm5
479; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
480; SSE2-NEXT:    por %xmm5, %xmm6
481; SSE2-NEXT:    pand %xmm6, %xmm0
482; SSE2-NEXT:    pandn %xmm2, %xmm6
483; SSE2-NEXT:    por %xmm6, %xmm0
484; SSE2-NEXT:    movdqa %xmm3, %xmm2
485; SSE2-NEXT:    pxor %xmm4, %xmm2
486; SSE2-NEXT:    pxor %xmm1, %xmm4
487; SSE2-NEXT:    movdqa %xmm4, %xmm5
488; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
489; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
490; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
491; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
492; SSE2-NEXT:    pand %xmm6, %xmm2
493; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
494; SSE2-NEXT:    por %xmm2, %xmm4
495; SSE2-NEXT:    pand %xmm4, %xmm1
496; SSE2-NEXT:    pandn %xmm3, %xmm4
497; SSE2-NEXT:    por %xmm4, %xmm1
498; SSE2-NEXT:    retq
499;
500; SSE41-LABEL: max_ge_v4i64:
501; SSE41:       # %bb.0:
502; SSE41-NEXT:    movdqa %xmm0, %xmm4
503; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
504; SSE41-NEXT:    movdqa %xmm2, %xmm0
505; SSE41-NEXT:    pxor %xmm5, %xmm0
506; SSE41-NEXT:    movdqa %xmm4, %xmm6
507; SSE41-NEXT:    pxor %xmm5, %xmm6
508; SSE41-NEXT:    movdqa %xmm6, %xmm7
509; SSE41-NEXT:    pcmpeqd %xmm0, %xmm7
510; SSE41-NEXT:    pcmpgtd %xmm0, %xmm6
511; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
512; SSE41-NEXT:    pand %xmm7, %xmm0
513; SSE41-NEXT:    por %xmm6, %xmm0
514; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
515; SSE41-NEXT:    movdqa %xmm3, %xmm0
516; SSE41-NEXT:    pxor %xmm5, %xmm0
517; SSE41-NEXT:    pxor %xmm1, %xmm5
518; SSE41-NEXT:    movdqa %xmm5, %xmm4
519; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
520; SSE41-NEXT:    pcmpgtd %xmm0, %xmm5
521; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[0,0,2,2]
522; SSE41-NEXT:    pand %xmm4, %xmm0
523; SSE41-NEXT:    por %xmm5, %xmm0
524; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
525; SSE41-NEXT:    movapd %xmm2, %xmm0
526; SSE41-NEXT:    movapd %xmm3, %xmm1
527; SSE41-NEXT:    retq
528;
529; SSE42-LABEL: max_ge_v4i64:
530; SSE42:       # %bb.0:
531; SSE42-NEXT:    movdqa %xmm0, %xmm4
532; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
533; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
534; SSE42-NEXT:    movdqa %xmm1, %xmm0
535; SSE42-NEXT:    pcmpgtq %xmm3, %xmm0
536; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
537; SSE42-NEXT:    movapd %xmm2, %xmm0
538; SSE42-NEXT:    movapd %xmm3, %xmm1
539; SSE42-NEXT:    retq
540;
541; AVX1-LABEL: max_ge_v4i64:
542; AVX1:       # %bb.0:
543; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
544; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
545; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
546; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm3
547; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
548; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
549; AVX1-NEXT:    retq
550;
551; AVX2-LABEL: max_ge_v4i64:
552; AVX2:       # %bb.0:
553; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
554; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
555; AVX2-NEXT:    retq
556;
557; AVX512-LABEL: max_ge_v4i64:
558; AVX512:       # %bb.0:
559; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
560; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
561; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
562; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
563; AVX512-NEXT:    retq
564  %1 = icmp sge <4 x i64> %a, %b
565  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
566  ret <4 x i64> %2
567}
568
569define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) {
570; SSE2-LABEL: max_ge_v4i32:
571; SSE2:       # %bb.0:
572; SSE2-NEXT:    movdqa %xmm0, %xmm2
573; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
574; SSE2-NEXT:    pand %xmm2, %xmm0
575; SSE2-NEXT:    pandn %xmm1, %xmm2
576; SSE2-NEXT:    por %xmm2, %xmm0
577; SSE2-NEXT:    retq
578;
579; SSE41-LABEL: max_ge_v4i32:
580; SSE41:       # %bb.0:
581; SSE41-NEXT:    pmaxsd %xmm1, %xmm0
582; SSE41-NEXT:    retq
583;
584; SSE42-LABEL: max_ge_v4i32:
585; SSE42:       # %bb.0:
586; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
587; SSE42-NEXT:    retq
588;
589; AVX-LABEL: max_ge_v4i32:
590; AVX:       # %bb.0:
591; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
592; AVX-NEXT:    retq
593  %1 = icmp sge <4 x i32> %a, %b
594  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
595  ret <4 x i32> %2
596}
597
598define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) {
599; SSE2-LABEL: max_ge_v8i32:
600; SSE2:       # %bb.0:
601; SSE2-NEXT:    movdqa %xmm0, %xmm4
602; SSE2-NEXT:    pcmpgtd %xmm2, %xmm4
603; SSE2-NEXT:    pand %xmm4, %xmm0
604; SSE2-NEXT:    pandn %xmm2, %xmm4
605; SSE2-NEXT:    por %xmm4, %xmm0
606; SSE2-NEXT:    movdqa %xmm1, %xmm2
607; SSE2-NEXT:    pcmpgtd %xmm3, %xmm2
608; SSE2-NEXT:    pand %xmm2, %xmm1
609; SSE2-NEXT:    pandn %xmm3, %xmm2
610; SSE2-NEXT:    por %xmm2, %xmm1
611; SSE2-NEXT:    retq
612;
613; SSE41-LABEL: max_ge_v8i32:
614; SSE41:       # %bb.0:
615; SSE41-NEXT:    pmaxsd %xmm2, %xmm0
616; SSE41-NEXT:    pmaxsd %xmm3, %xmm1
617; SSE41-NEXT:    retq
618;
619; SSE42-LABEL: max_ge_v8i32:
620; SSE42:       # %bb.0:
621; SSE42-NEXT:    pmaxsd %xmm2, %xmm0
622; SSE42-NEXT:    pmaxsd %xmm3, %xmm1
623; SSE42-NEXT:    retq
624;
625; AVX1-LABEL: max_ge_v8i32:
626; AVX1:       # %bb.0:
627; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
628; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
629; AVX1-NEXT:    vpmaxsd %xmm2, %xmm3, %xmm2
630; AVX1-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
631; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
632; AVX1-NEXT:    retq
633;
634; AVX2-LABEL: max_ge_v8i32:
635; AVX2:       # %bb.0:
636; AVX2-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
637; AVX2-NEXT:    retq
638;
639; AVX512-LABEL: max_ge_v8i32:
640; AVX512:       # %bb.0:
641; AVX512-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
642; AVX512-NEXT:    retq
643  %1 = icmp sge <8 x i32> %a, %b
644  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
645  ret <8 x i32> %2
646}
647
648define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) {
649; SSE-LABEL: max_ge_v8i16:
650; SSE:       # %bb.0:
651; SSE-NEXT:    pmaxsw %xmm1, %xmm0
652; SSE-NEXT:    retq
653;
654; AVX-LABEL: max_ge_v8i16:
655; AVX:       # %bb.0:
656; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
657; AVX-NEXT:    retq
658  %1 = icmp sge <8 x i16> %a, %b
659  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
660  ret <8 x i16> %2
661}
662
663define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) {
664; SSE-LABEL: max_ge_v16i16:
665; SSE:       # %bb.0:
666; SSE-NEXT:    pmaxsw %xmm2, %xmm0
667; SSE-NEXT:    pmaxsw %xmm3, %xmm1
668; SSE-NEXT:    retq
669;
670; AVX1-LABEL: max_ge_v16i16:
671; AVX1:       # %bb.0:
672; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
673; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
674; AVX1-NEXT:    vpmaxsw %xmm2, %xmm3, %xmm2
675; AVX1-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
676; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
677; AVX1-NEXT:    retq
678;
679; AVX2-LABEL: max_ge_v16i16:
680; AVX2:       # %bb.0:
681; AVX2-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
682; AVX2-NEXT:    retq
683;
684; AVX512-LABEL: max_ge_v16i16:
685; AVX512:       # %bb.0:
686; AVX512-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
687; AVX512-NEXT:    retq
688  %1 = icmp sge <16 x i16> %a, %b
689  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
690  ret <16 x i16> %2
691}
692
693define <16 x i8> @max_ge_v16i8(<16 x i8> %a, <16 x i8> %b) {
694; SSE2-LABEL: max_ge_v16i8:
695; SSE2:       # %bb.0:
696; SSE2-NEXT:    movdqa %xmm0, %xmm2
697; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
698; SSE2-NEXT:    pand %xmm2, %xmm0
699; SSE2-NEXT:    pandn %xmm1, %xmm2
700; SSE2-NEXT:    por %xmm2, %xmm0
701; SSE2-NEXT:    retq
702;
703; SSE41-LABEL: max_ge_v16i8:
704; SSE41:       # %bb.0:
705; SSE41-NEXT:    pmaxsb %xmm1, %xmm0
706; SSE41-NEXT:    retq
707;
708; SSE42-LABEL: max_ge_v16i8:
709; SSE42:       # %bb.0:
710; SSE42-NEXT:    pmaxsb %xmm1, %xmm0
711; SSE42-NEXT:    retq
712;
713; AVX-LABEL: max_ge_v16i8:
714; AVX:       # %bb.0:
715; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
716; AVX-NEXT:    retq
717  %1 = icmp sge <16 x i8> %a, %b
718  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
719  ret <16 x i8> %2
720}
721
722define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) {
723; SSE2-LABEL: max_ge_v32i8:
724; SSE2:       # %bb.0:
725; SSE2-NEXT:    movdqa %xmm0, %xmm4
726; SSE2-NEXT:    pcmpgtb %xmm2, %xmm4
727; SSE2-NEXT:    pand %xmm4, %xmm0
728; SSE2-NEXT:    pandn %xmm2, %xmm4
729; SSE2-NEXT:    por %xmm4, %xmm0
730; SSE2-NEXT:    movdqa %xmm1, %xmm2
731; SSE2-NEXT:    pcmpgtb %xmm3, %xmm2
732; SSE2-NEXT:    pand %xmm2, %xmm1
733; SSE2-NEXT:    pandn %xmm3, %xmm2
734; SSE2-NEXT:    por %xmm2, %xmm1
735; SSE2-NEXT:    retq
736;
737; SSE41-LABEL: max_ge_v32i8:
738; SSE41:       # %bb.0:
739; SSE41-NEXT:    pmaxsb %xmm2, %xmm0
740; SSE41-NEXT:    pmaxsb %xmm3, %xmm1
741; SSE41-NEXT:    retq
742;
743; SSE42-LABEL: max_ge_v32i8:
744; SSE42:       # %bb.0:
745; SSE42-NEXT:    pmaxsb %xmm2, %xmm0
746; SSE42-NEXT:    pmaxsb %xmm3, %xmm1
747; SSE42-NEXT:    retq
748;
749; AVX1-LABEL: max_ge_v32i8:
750; AVX1:       # %bb.0:
751; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
752; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
753; AVX1-NEXT:    vpmaxsb %xmm2, %xmm3, %xmm2
754; AVX1-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
755; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
756; AVX1-NEXT:    retq
757;
758; AVX2-LABEL: max_ge_v32i8:
759; AVX2:       # %bb.0:
760; AVX2-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
761; AVX2-NEXT:    retq
762;
763; AVX512-LABEL: max_ge_v32i8:
764; AVX512:       # %bb.0:
765; AVX512-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
766; AVX512-NEXT:    retq
767  %1 = icmp sge <32 x i8> %a, %b
768  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
769  ret <32 x i8> %2
770}
771
772;
773; Signed Minimum (LT)
774;
775
776define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) {
777; SSE2-LABEL: min_lt_v2i64:
778; SSE2:       # %bb.0:
779; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
780; SSE2-NEXT:    movdqa %xmm0, %xmm3
781; SSE2-NEXT:    pxor %xmm2, %xmm3
782; SSE2-NEXT:    pxor %xmm1, %xmm2
783; SSE2-NEXT:    movdqa %xmm2, %xmm4
784; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
785; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
786; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
787; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
788; SSE2-NEXT:    pand %xmm5, %xmm2
789; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
790; SSE2-NEXT:    por %xmm2, %xmm3
791; SSE2-NEXT:    pand %xmm3, %xmm0
792; SSE2-NEXT:    pandn %xmm1, %xmm3
793; SSE2-NEXT:    por %xmm3, %xmm0
794; SSE2-NEXT:    retq
795;
796; SSE41-LABEL: min_lt_v2i64:
797; SSE41:       # %bb.0:
798; SSE41-NEXT:    movdqa %xmm0, %xmm2
799; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
800; SSE41-NEXT:    pxor %xmm3, %xmm0
801; SSE41-NEXT:    pxor %xmm1, %xmm3
802; SSE41-NEXT:    movdqa %xmm3, %xmm4
803; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
804; SSE41-NEXT:    pcmpgtd %xmm0, %xmm3
805; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
806; SSE41-NEXT:    pand %xmm4, %xmm0
807; SSE41-NEXT:    por %xmm3, %xmm0
808; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
809; SSE41-NEXT:    movapd %xmm1, %xmm0
810; SSE41-NEXT:    retq
811;
812; SSE42-LABEL: min_lt_v2i64:
813; SSE42:       # %bb.0:
814; SSE42-NEXT:    movdqa %xmm0, %xmm2
815; SSE42-NEXT:    movdqa %xmm1, %xmm0
816; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
817; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
818; SSE42-NEXT:    movapd %xmm1, %xmm0
819; SSE42-NEXT:    retq
820;
821; AVX1-LABEL: min_lt_v2i64:
822; AVX1:       # %bb.0:
823; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
824; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
825; AVX1-NEXT:    retq
826;
827; AVX2-LABEL: min_lt_v2i64:
828; AVX2:       # %bb.0:
829; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
830; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
831; AVX2-NEXT:    retq
832;
833; AVX512-LABEL: min_lt_v2i64:
834; AVX512:       # %bb.0:
835; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
836; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
837; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
838; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
839; AVX512-NEXT:    vzeroupper
840; AVX512-NEXT:    retq
841  %1 = icmp slt <2 x i64> %a, %b
842  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
843  ret <2 x i64> %2
844}
845
846define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) {
847; SSE2-LABEL: min_lt_v4i64:
848; SSE2:       # %bb.0:
849; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
850; SSE2-NEXT:    movdqa %xmm0, %xmm5
851; SSE2-NEXT:    pxor %xmm4, %xmm5
852; SSE2-NEXT:    movdqa %xmm2, %xmm6
853; SSE2-NEXT:    pxor %xmm4, %xmm6
854; SSE2-NEXT:    movdqa %xmm6, %xmm7
855; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
856; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
857; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
858; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
859; SSE2-NEXT:    pand %xmm8, %xmm5
860; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
861; SSE2-NEXT:    por %xmm5, %xmm6
862; SSE2-NEXT:    pand %xmm6, %xmm0
863; SSE2-NEXT:    pandn %xmm2, %xmm6
864; SSE2-NEXT:    por %xmm6, %xmm0
865; SSE2-NEXT:    movdqa %xmm1, %xmm2
866; SSE2-NEXT:    pxor %xmm4, %xmm2
867; SSE2-NEXT:    pxor %xmm3, %xmm4
868; SSE2-NEXT:    movdqa %xmm4, %xmm5
869; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
870; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
871; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
872; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
873; SSE2-NEXT:    pand %xmm6, %xmm2
874; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
875; SSE2-NEXT:    por %xmm2, %xmm4
876; SSE2-NEXT:    pand %xmm4, %xmm1
877; SSE2-NEXT:    pandn %xmm3, %xmm4
878; SSE2-NEXT:    por %xmm4, %xmm1
879; SSE2-NEXT:    retq
880;
881; SSE41-LABEL: min_lt_v4i64:
882; SSE41:       # %bb.0:
883; SSE41-NEXT:    movdqa %xmm0, %xmm4
884; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
885; SSE41-NEXT:    pxor %xmm5, %xmm0
886; SSE41-NEXT:    movdqa %xmm2, %xmm6
887; SSE41-NEXT:    pxor %xmm5, %xmm6
888; SSE41-NEXT:    movdqa %xmm6, %xmm7
889; SSE41-NEXT:    pcmpeqd %xmm0, %xmm7
890; SSE41-NEXT:    pcmpgtd %xmm0, %xmm6
891; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
892; SSE41-NEXT:    pand %xmm7, %xmm0
893; SSE41-NEXT:    por %xmm6, %xmm0
894; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
895; SSE41-NEXT:    movdqa %xmm1, %xmm0
896; SSE41-NEXT:    pxor %xmm5, %xmm0
897; SSE41-NEXT:    pxor %xmm3, %xmm5
898; SSE41-NEXT:    movdqa %xmm5, %xmm4
899; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
900; SSE41-NEXT:    pcmpgtd %xmm0, %xmm5
901; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[0,0,2,2]
902; SSE41-NEXT:    pand %xmm4, %xmm0
903; SSE41-NEXT:    por %xmm5, %xmm0
904; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
905; SSE41-NEXT:    movapd %xmm2, %xmm0
906; SSE41-NEXT:    movapd %xmm3, %xmm1
907; SSE41-NEXT:    retq
908;
909; SSE42-LABEL: min_lt_v4i64:
910; SSE42:       # %bb.0:
911; SSE42-NEXT:    movdqa %xmm0, %xmm4
912; SSE42-NEXT:    movdqa %xmm2, %xmm0
913; SSE42-NEXT:    pcmpgtq %xmm4, %xmm0
914; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
915; SSE42-NEXT:    movdqa %xmm3, %xmm0
916; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
917; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
918; SSE42-NEXT:    movapd %xmm2, %xmm0
919; SSE42-NEXT:    movapd %xmm3, %xmm1
920; SSE42-NEXT:    retq
921;
922; AVX1-LABEL: min_lt_v4i64:
923; AVX1:       # %bb.0:
924; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
925; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
926; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
927; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm3
928; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
929; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
930; AVX1-NEXT:    retq
931;
932; AVX2-LABEL: min_lt_v4i64:
933; AVX2:       # %bb.0:
934; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
935; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
936; AVX2-NEXT:    retq
937;
938; AVX512-LABEL: min_lt_v4i64:
939; AVX512:       # %bb.0:
940; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
941; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
942; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
943; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
944; AVX512-NEXT:    retq
945  %1 = icmp slt <4 x i64> %a, %b
946  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
947  ret <4 x i64> %2
948}
949
950define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) {
951; SSE2-LABEL: min_lt_v4i32:
952; SSE2:       # %bb.0:
953; SSE2-NEXT:    movdqa %xmm1, %xmm2
954; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
955; SSE2-NEXT:    pand %xmm2, %xmm0
956; SSE2-NEXT:    pandn %xmm1, %xmm2
957; SSE2-NEXT:    por %xmm2, %xmm0
958; SSE2-NEXT:    retq
959;
960; SSE41-LABEL: min_lt_v4i32:
961; SSE41:       # %bb.0:
962; SSE41-NEXT:    pminsd %xmm1, %xmm0
963; SSE41-NEXT:    retq
964;
965; SSE42-LABEL: min_lt_v4i32:
966; SSE42:       # %bb.0:
967; SSE42-NEXT:    pminsd %xmm1, %xmm0
968; SSE42-NEXT:    retq
969;
970; AVX-LABEL: min_lt_v4i32:
971; AVX:       # %bb.0:
972; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
973; AVX-NEXT:    retq
974  %1 = icmp slt <4 x i32> %a, %b
975  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
976  ret <4 x i32> %2
977}
978
979define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) {
980; SSE2-LABEL: min_lt_v8i32:
981; SSE2:       # %bb.0:
982; SSE2-NEXT:    movdqa %xmm2, %xmm4
983; SSE2-NEXT:    pcmpgtd %xmm0, %xmm4
984; SSE2-NEXT:    pand %xmm4, %xmm0
985; SSE2-NEXT:    pandn %xmm2, %xmm4
986; SSE2-NEXT:    por %xmm4, %xmm0
987; SSE2-NEXT:    movdqa %xmm3, %xmm2
988; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
989; SSE2-NEXT:    pand %xmm2, %xmm1
990; SSE2-NEXT:    pandn %xmm3, %xmm2
991; SSE2-NEXT:    por %xmm2, %xmm1
992; SSE2-NEXT:    retq
993;
994; SSE41-LABEL: min_lt_v8i32:
995; SSE41:       # %bb.0:
996; SSE41-NEXT:    pminsd %xmm2, %xmm0
997; SSE41-NEXT:    pminsd %xmm3, %xmm1
998; SSE41-NEXT:    retq
999;
1000; SSE42-LABEL: min_lt_v8i32:
1001; SSE42:       # %bb.0:
1002; SSE42-NEXT:    pminsd %xmm2, %xmm0
1003; SSE42-NEXT:    pminsd %xmm3, %xmm1
1004; SSE42-NEXT:    retq
1005;
1006; AVX1-LABEL: min_lt_v8i32:
1007; AVX1:       # %bb.0:
1008; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1009; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1010; AVX1-NEXT:    vpminsd %xmm2, %xmm3, %xmm2
1011; AVX1-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1012; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1013; AVX1-NEXT:    retq
1014;
1015; AVX2-LABEL: min_lt_v8i32:
1016; AVX2:       # %bb.0:
1017; AVX2-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1018; AVX2-NEXT:    retq
1019;
1020; AVX512-LABEL: min_lt_v8i32:
1021; AVX512:       # %bb.0:
1022; AVX512-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1023; AVX512-NEXT:    retq
1024  %1 = icmp slt <8 x i32> %a, %b
1025  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1026  ret <8 x i32> %2
1027}
1028
1029define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) {
1030; SSE-LABEL: min_lt_v8i16:
1031; SSE:       # %bb.0:
1032; SSE-NEXT:    pminsw %xmm1, %xmm0
1033; SSE-NEXT:    retq
1034;
1035; AVX-LABEL: min_lt_v8i16:
1036; AVX:       # %bb.0:
1037; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1038; AVX-NEXT:    retq
1039  %1 = icmp slt <8 x i16> %a, %b
1040  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1041  ret <8 x i16> %2
1042}
1043
1044define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) {
1045; SSE-LABEL: min_lt_v16i16:
1046; SSE:       # %bb.0:
1047; SSE-NEXT:    pminsw %xmm2, %xmm0
1048; SSE-NEXT:    pminsw %xmm3, %xmm1
1049; SSE-NEXT:    retq
1050;
1051; AVX1-LABEL: min_lt_v16i16:
1052; AVX1:       # %bb.0:
1053; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1054; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1055; AVX1-NEXT:    vpminsw %xmm2, %xmm3, %xmm2
1056; AVX1-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1057; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1058; AVX1-NEXT:    retq
1059;
1060; AVX2-LABEL: min_lt_v16i16:
1061; AVX2:       # %bb.0:
1062; AVX2-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1063; AVX2-NEXT:    retq
1064;
1065; AVX512-LABEL: min_lt_v16i16:
1066; AVX512:       # %bb.0:
1067; AVX512-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1068; AVX512-NEXT:    retq
1069  %1 = icmp slt <16 x i16> %a, %b
1070  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1071  ret <16 x i16> %2
1072}
1073
1074define <16 x i8> @min_lt_v16i8(<16 x i8> %a, <16 x i8> %b) {
1075; SSE2-LABEL: min_lt_v16i8:
1076; SSE2:       # %bb.0:
1077; SSE2-NEXT:    movdqa %xmm1, %xmm2
1078; SSE2-NEXT:    pcmpgtb %xmm0, %xmm2
1079; SSE2-NEXT:    pand %xmm2, %xmm0
1080; SSE2-NEXT:    pandn %xmm1, %xmm2
1081; SSE2-NEXT:    por %xmm2, %xmm0
1082; SSE2-NEXT:    retq
1083;
1084; SSE41-LABEL: min_lt_v16i8:
1085; SSE41:       # %bb.0:
1086; SSE41-NEXT:    pminsb %xmm1, %xmm0
1087; SSE41-NEXT:    retq
1088;
1089; SSE42-LABEL: min_lt_v16i8:
1090; SSE42:       # %bb.0:
1091; SSE42-NEXT:    pminsb %xmm1, %xmm0
1092; SSE42-NEXT:    retq
1093;
1094; AVX-LABEL: min_lt_v16i8:
1095; AVX:       # %bb.0:
1096; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1097; AVX-NEXT:    retq
1098  %1 = icmp slt <16 x i8> %a, %b
1099  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1100  ret <16 x i8> %2
1101}
1102
1103define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) {
1104; SSE2-LABEL: min_lt_v32i8:
1105; SSE2:       # %bb.0:
1106; SSE2-NEXT:    movdqa %xmm2, %xmm4
1107; SSE2-NEXT:    pcmpgtb %xmm0, %xmm4
1108; SSE2-NEXT:    pand %xmm4, %xmm0
1109; SSE2-NEXT:    pandn %xmm2, %xmm4
1110; SSE2-NEXT:    por %xmm4, %xmm0
1111; SSE2-NEXT:    movdqa %xmm3, %xmm2
1112; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
1113; SSE2-NEXT:    pand %xmm2, %xmm1
1114; SSE2-NEXT:    pandn %xmm3, %xmm2
1115; SSE2-NEXT:    por %xmm2, %xmm1
1116; SSE2-NEXT:    retq
1117;
1118; SSE41-LABEL: min_lt_v32i8:
1119; SSE41:       # %bb.0:
1120; SSE41-NEXT:    pminsb %xmm2, %xmm0
1121; SSE41-NEXT:    pminsb %xmm3, %xmm1
1122; SSE41-NEXT:    retq
1123;
1124; SSE42-LABEL: min_lt_v32i8:
1125; SSE42:       # %bb.0:
1126; SSE42-NEXT:    pminsb %xmm2, %xmm0
1127; SSE42-NEXT:    pminsb %xmm3, %xmm1
1128; SSE42-NEXT:    retq
1129;
1130; AVX1-LABEL: min_lt_v32i8:
1131; AVX1:       # %bb.0:
1132; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1133; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1134; AVX1-NEXT:    vpminsb %xmm2, %xmm3, %xmm2
1135; AVX1-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1136; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1137; AVX1-NEXT:    retq
1138;
1139; AVX2-LABEL: min_lt_v32i8:
1140; AVX2:       # %bb.0:
1141; AVX2-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1142; AVX2-NEXT:    retq
1143;
1144; AVX512-LABEL: min_lt_v32i8:
1145; AVX512:       # %bb.0:
1146; AVX512-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1147; AVX512-NEXT:    retq
1148  %1 = icmp slt <32 x i8> %a, %b
1149  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1150  ret <32 x i8> %2
1151}
1152
1153;
1154; Signed Minimum (LE)
1155;
1156
1157define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) {
1158; SSE2-LABEL: min_le_v2i64:
1159; SSE2:       # %bb.0:
1160; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
1161; SSE2-NEXT:    movdqa %xmm0, %xmm3
1162; SSE2-NEXT:    pxor %xmm2, %xmm3
1163; SSE2-NEXT:    pxor %xmm1, %xmm2
1164; SSE2-NEXT:    movdqa %xmm2, %xmm4
1165; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
1166; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
1167; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
1168; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
1169; SSE2-NEXT:    pand %xmm5, %xmm2
1170; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
1171; SSE2-NEXT:    por %xmm2, %xmm3
1172; SSE2-NEXT:    pand %xmm3, %xmm0
1173; SSE2-NEXT:    pandn %xmm1, %xmm3
1174; SSE2-NEXT:    por %xmm3, %xmm0
1175; SSE2-NEXT:    retq
1176;
1177; SSE41-LABEL: min_le_v2i64:
1178; SSE41:       # %bb.0:
1179; SSE41-NEXT:    movdqa %xmm0, %xmm2
1180; SSE41-NEXT:    movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
1181; SSE41-NEXT:    pxor %xmm3, %xmm0
1182; SSE41-NEXT:    pxor %xmm1, %xmm3
1183; SSE41-NEXT:    movdqa %xmm3, %xmm4
1184; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
1185; SSE41-NEXT:    pcmpgtd %xmm0, %xmm3
1186; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2]
1187; SSE41-NEXT:    pand %xmm4, %xmm0
1188; SSE41-NEXT:    por %xmm3, %xmm0
1189; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
1190; SSE41-NEXT:    movapd %xmm1, %xmm0
1191; SSE41-NEXT:    retq
1192;
1193; SSE42-LABEL: min_le_v2i64:
1194; SSE42:       # %bb.0:
1195; SSE42-NEXT:    movdqa %xmm0, %xmm2
1196; SSE42-NEXT:    movdqa %xmm1, %xmm0
1197; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
1198; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
1199; SSE42-NEXT:    movapd %xmm1, %xmm0
1200; SSE42-NEXT:    retq
1201;
1202; AVX1-LABEL: min_le_v2i64:
1203; AVX1:       # %bb.0:
1204; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
1205; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
1206; AVX1-NEXT:    retq
1207;
1208; AVX2-LABEL: min_le_v2i64:
1209; AVX2:       # %bb.0:
1210; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
1211; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
1212; AVX2-NEXT:    retq
1213;
1214; AVX512-LABEL: min_le_v2i64:
1215; AVX512:       # %bb.0:
1216; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
1217; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
1218; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
1219; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
1220; AVX512-NEXT:    vzeroupper
1221; AVX512-NEXT:    retq
1222  %1 = icmp sle <2 x i64> %a, %b
1223  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
1224  ret <2 x i64> %2
1225}
1226
1227define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) {
1228; SSE2-LABEL: min_le_v4i64:
1229; SSE2:       # %bb.0:
1230; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
1231; SSE2-NEXT:    movdqa %xmm0, %xmm5
1232; SSE2-NEXT:    pxor %xmm4, %xmm5
1233; SSE2-NEXT:    movdqa %xmm2, %xmm6
1234; SSE2-NEXT:    pxor %xmm4, %xmm6
1235; SSE2-NEXT:    movdqa %xmm6, %xmm7
1236; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
1237; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
1238; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
1239; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
1240; SSE2-NEXT:    pand %xmm8, %xmm5
1241; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
1242; SSE2-NEXT:    por %xmm5, %xmm6
1243; SSE2-NEXT:    pand %xmm6, %xmm0
1244; SSE2-NEXT:    pandn %xmm2, %xmm6
1245; SSE2-NEXT:    por %xmm6, %xmm0
1246; SSE2-NEXT:    movdqa %xmm1, %xmm2
1247; SSE2-NEXT:    pxor %xmm4, %xmm2
1248; SSE2-NEXT:    pxor %xmm3, %xmm4
1249; SSE2-NEXT:    movdqa %xmm4, %xmm5
1250; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
1251; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
1252; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
1253; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
1254; SSE2-NEXT:    pand %xmm6, %xmm2
1255; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
1256; SSE2-NEXT:    por %xmm2, %xmm4
1257; SSE2-NEXT:    pand %xmm4, %xmm1
1258; SSE2-NEXT:    pandn %xmm3, %xmm4
1259; SSE2-NEXT:    por %xmm4, %xmm1
1260; SSE2-NEXT:    retq
1261;
1262; SSE41-LABEL: min_le_v4i64:
1263; SSE41:       # %bb.0:
1264; SSE41-NEXT:    movdqa %xmm0, %xmm4
1265; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
1266; SSE41-NEXT:    pxor %xmm5, %xmm0
1267; SSE41-NEXT:    movdqa %xmm2, %xmm6
1268; SSE41-NEXT:    pxor %xmm5, %xmm6
1269; SSE41-NEXT:    movdqa %xmm6, %xmm7
1270; SSE41-NEXT:    pcmpeqd %xmm0, %xmm7
1271; SSE41-NEXT:    pcmpgtd %xmm0, %xmm6
1272; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
1273; SSE41-NEXT:    pand %xmm7, %xmm0
1274; SSE41-NEXT:    por %xmm6, %xmm0
1275; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
1276; SSE41-NEXT:    movdqa %xmm1, %xmm0
1277; SSE41-NEXT:    pxor %xmm5, %xmm0
1278; SSE41-NEXT:    pxor %xmm3, %xmm5
1279; SSE41-NEXT:    movdqa %xmm5, %xmm4
1280; SSE41-NEXT:    pcmpeqd %xmm0, %xmm4
1281; SSE41-NEXT:    pcmpgtd %xmm0, %xmm5
1282; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[0,0,2,2]
1283; SSE41-NEXT:    pand %xmm4, %xmm0
1284; SSE41-NEXT:    por %xmm5, %xmm0
1285; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
1286; SSE41-NEXT:    movapd %xmm2, %xmm0
1287; SSE41-NEXT:    movapd %xmm3, %xmm1
1288; SSE41-NEXT:    retq
1289;
1290; SSE42-LABEL: min_le_v4i64:
1291; SSE42:       # %bb.0:
1292; SSE42-NEXT:    movdqa %xmm0, %xmm4
1293; SSE42-NEXT:    movdqa %xmm2, %xmm0
1294; SSE42-NEXT:    pcmpgtq %xmm4, %xmm0
1295; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
1296; SSE42-NEXT:    movdqa %xmm3, %xmm0
1297; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
1298; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
1299; SSE42-NEXT:    movapd %xmm2, %xmm0
1300; SSE42-NEXT:    movapd %xmm3, %xmm1
1301; SSE42-NEXT:    retq
1302;
1303; AVX1-LABEL: min_le_v4i64:
1304; AVX1:       # %bb.0:
1305; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
1306; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
1307; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
1308; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm3
1309; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
1310; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1311; AVX1-NEXT:    retq
1312;
1313; AVX2-LABEL: min_le_v4i64:
1314; AVX2:       # %bb.0:
1315; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
1316; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1317; AVX2-NEXT:    retq
1318;
1319; AVX512-LABEL: min_le_v4i64:
1320; AVX512:       # %bb.0:
1321; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
1322; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
1323; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
1324; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
1325; AVX512-NEXT:    retq
1326  %1 = icmp sle <4 x i64> %a, %b
1327  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
1328  ret <4 x i64> %2
1329}
1330
1331define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) {
1332; SSE2-LABEL: min_le_v4i32:
1333; SSE2:       # %bb.0:
1334; SSE2-NEXT:    movdqa %xmm1, %xmm2
1335; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
1336; SSE2-NEXT:    pand %xmm2, %xmm0
1337; SSE2-NEXT:    pandn %xmm1, %xmm2
1338; SSE2-NEXT:    por %xmm2, %xmm0
1339; SSE2-NEXT:    retq
1340;
1341; SSE41-LABEL: min_le_v4i32:
1342; SSE41:       # %bb.0:
1343; SSE41-NEXT:    pminsd %xmm1, %xmm0
1344; SSE41-NEXT:    retq
1345;
1346; SSE42-LABEL: min_le_v4i32:
1347; SSE42:       # %bb.0:
1348; SSE42-NEXT:    pminsd %xmm1, %xmm0
1349; SSE42-NEXT:    retq
1350;
1351; AVX-LABEL: min_le_v4i32:
1352; AVX:       # %bb.0:
1353; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1354; AVX-NEXT:    retq
1355  %1 = icmp sle <4 x i32> %a, %b
1356  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
1357  ret <4 x i32> %2
1358}
1359
1360define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) {
1361; SSE2-LABEL: min_le_v8i32:
1362; SSE2:       # %bb.0:
1363; SSE2-NEXT:    movdqa %xmm2, %xmm4
1364; SSE2-NEXT:    pcmpgtd %xmm0, %xmm4
1365; SSE2-NEXT:    pand %xmm4, %xmm0
1366; SSE2-NEXT:    pandn %xmm2, %xmm4
1367; SSE2-NEXT:    por %xmm4, %xmm0
1368; SSE2-NEXT:    movdqa %xmm3, %xmm2
1369; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
1370; SSE2-NEXT:    pand %xmm2, %xmm1
1371; SSE2-NEXT:    pandn %xmm3, %xmm2
1372; SSE2-NEXT:    por %xmm2, %xmm1
1373; SSE2-NEXT:    retq
1374;
1375; SSE41-LABEL: min_le_v8i32:
1376; SSE41:       # %bb.0:
1377; SSE41-NEXT:    pminsd %xmm2, %xmm0
1378; SSE41-NEXT:    pminsd %xmm3, %xmm1
1379; SSE41-NEXT:    retq
1380;
1381; SSE42-LABEL: min_le_v8i32:
1382; SSE42:       # %bb.0:
1383; SSE42-NEXT:    pminsd %xmm2, %xmm0
1384; SSE42-NEXT:    pminsd %xmm3, %xmm1
1385; SSE42-NEXT:    retq
1386;
1387; AVX1-LABEL: min_le_v8i32:
1388; AVX1:       # %bb.0:
1389; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1390; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1391; AVX1-NEXT:    vpminsd %xmm2, %xmm3, %xmm2
1392; AVX1-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1393; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1394; AVX1-NEXT:    retq
1395;
1396; AVX2-LABEL: min_le_v8i32:
1397; AVX2:       # %bb.0:
1398; AVX2-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1399; AVX2-NEXT:    retq
1400;
1401; AVX512-LABEL: min_le_v8i32:
1402; AVX512:       # %bb.0:
1403; AVX512-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1404; AVX512-NEXT:    retq
1405  %1 = icmp sle <8 x i32> %a, %b
1406  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1407  ret <8 x i32> %2
1408}
1409
1410define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) {
1411; SSE-LABEL: min_le_v8i16:
1412; SSE:       # %bb.0:
1413; SSE-NEXT:    pminsw %xmm1, %xmm0
1414; SSE-NEXT:    retq
1415;
1416; AVX-LABEL: min_le_v8i16:
1417; AVX:       # %bb.0:
1418; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1419; AVX-NEXT:    retq
1420  %1 = icmp sle <8 x i16> %a, %b
1421  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1422  ret <8 x i16> %2
1423}
1424
1425define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) {
1426; SSE-LABEL: min_le_v16i16:
1427; SSE:       # %bb.0:
1428; SSE-NEXT:    pminsw %xmm2, %xmm0
1429; SSE-NEXT:    pminsw %xmm3, %xmm1
1430; SSE-NEXT:    retq
1431;
1432; AVX1-LABEL: min_le_v16i16:
1433; AVX1:       # %bb.0:
1434; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1435; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1436; AVX1-NEXT:    vpminsw %xmm2, %xmm3, %xmm2
1437; AVX1-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1438; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1439; AVX1-NEXT:    retq
1440;
1441; AVX2-LABEL: min_le_v16i16:
1442; AVX2:       # %bb.0:
1443; AVX2-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1444; AVX2-NEXT:    retq
1445;
1446; AVX512-LABEL: min_le_v16i16:
1447; AVX512:       # %bb.0:
1448; AVX512-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1449; AVX512-NEXT:    retq
1450  %1 = icmp sle <16 x i16> %a, %b
1451  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1452  ret <16 x i16> %2
1453}
1454
1455define <16 x i8> @min_le_v16i8(<16 x i8> %a, <16 x i8> %b) {
1456; SSE2-LABEL: min_le_v16i8:
1457; SSE2:       # %bb.0:
1458; SSE2-NEXT:    movdqa %xmm1, %xmm2
1459; SSE2-NEXT:    pcmpgtb %xmm0, %xmm2
1460; SSE2-NEXT:    pand %xmm2, %xmm0
1461; SSE2-NEXT:    pandn %xmm1, %xmm2
1462; SSE2-NEXT:    por %xmm2, %xmm0
1463; SSE2-NEXT:    retq
1464;
1465; SSE41-LABEL: min_le_v16i8:
1466; SSE41:       # %bb.0:
1467; SSE41-NEXT:    pminsb %xmm1, %xmm0
1468; SSE41-NEXT:    retq
1469;
1470; SSE42-LABEL: min_le_v16i8:
1471; SSE42:       # %bb.0:
1472; SSE42-NEXT:    pminsb %xmm1, %xmm0
1473; SSE42-NEXT:    retq
1474;
1475; AVX-LABEL: min_le_v16i8:
1476; AVX:       # %bb.0:
1477; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1478; AVX-NEXT:    retq
1479  %1 = icmp sle <16 x i8> %a, %b
1480  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1481  ret <16 x i8> %2
1482}
1483
1484define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) {
1485; SSE2-LABEL: min_le_v32i8:
1486; SSE2:       # %bb.0:
1487; SSE2-NEXT:    movdqa %xmm2, %xmm4
1488; SSE2-NEXT:    pcmpgtb %xmm0, %xmm4
1489; SSE2-NEXT:    pand %xmm4, %xmm0
1490; SSE2-NEXT:    pandn %xmm2, %xmm4
1491; SSE2-NEXT:    por %xmm4, %xmm0
1492; SSE2-NEXT:    movdqa %xmm3, %xmm2
1493; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
1494; SSE2-NEXT:    pand %xmm2, %xmm1
1495; SSE2-NEXT:    pandn %xmm3, %xmm2
1496; SSE2-NEXT:    por %xmm2, %xmm1
1497; SSE2-NEXT:    retq
1498;
1499; SSE41-LABEL: min_le_v32i8:
1500; SSE41:       # %bb.0:
1501; SSE41-NEXT:    pminsb %xmm2, %xmm0
1502; SSE41-NEXT:    pminsb %xmm3, %xmm1
1503; SSE41-NEXT:    retq
1504;
1505; SSE42-LABEL: min_le_v32i8:
1506; SSE42:       # %bb.0:
1507; SSE42-NEXT:    pminsb %xmm2, %xmm0
1508; SSE42-NEXT:    pminsb %xmm3, %xmm1
1509; SSE42-NEXT:    retq
1510;
1511; AVX1-LABEL: min_le_v32i8:
1512; AVX1:       # %bb.0:
1513; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1514; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1515; AVX1-NEXT:    vpminsb %xmm2, %xmm3, %xmm2
1516; AVX1-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1517; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1518; AVX1-NEXT:    retq
1519;
1520; AVX2-LABEL: min_le_v32i8:
1521; AVX2:       # %bb.0:
1522; AVX2-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1523; AVX2-NEXT:    retq
1524;
1525; AVX512-LABEL: min_le_v32i8:
1526; AVX512:       # %bb.0:
1527; AVX512-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1528; AVX512-NEXT:    retq
1529  %1 = icmp sle <32 x i8> %a, %b
1530  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1531  ret <32 x i8> %2
1532}
1533
1534;
1535; Constant Folding
1536;
1537
1538define <2 x i64> @max_gt_v2i64c() {
1539; SSE-LABEL: max_gt_v2i64c:
1540; SSE:       # %bb.0:
1541; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1542; SSE-NEXT:    retq
1543;
1544; AVX-LABEL: max_gt_v2i64c:
1545; AVX:       # %bb.0:
1546; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1547; AVX-NEXT:    retq
1548  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1549  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1550  %3 = icmp sgt <2 x i64> %1, %2
1551  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1552  ret <2 x i64> %4
1553}
1554
1555define <4 x i64> @max_gt_v4i64c() {
1556; SSE-LABEL: max_gt_v4i64c:
1557; SSE:       # %bb.0:
1558; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,7]
1559; SSE-NEXT:    pcmpeqd %xmm0, %xmm0
1560; SSE-NEXT:    retq
1561;
1562; AVX-LABEL: max_gt_v4i64c:
1563; AVX:       # %bb.0:
1564; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1565; AVX-NEXT:    retq
1566  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1567  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1568  %3 = icmp sgt <4 x i64> %1, %2
1569  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1570  ret <4 x i64> %4
1571}
1572
1573define <4 x i32> @max_gt_v4i32c() {
1574; SSE-LABEL: max_gt_v4i32c:
1575; SSE:       # %bb.0:
1576; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1577; SSE-NEXT:    retq
1578;
1579; AVX-LABEL: max_gt_v4i32c:
1580; AVX:       # %bb.0:
1581; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1582; AVX-NEXT:    retq
1583  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1584  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1585  %3 = icmp sgt <4 x i32> %1, %2
1586  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1587  ret <4 x i32> %4
1588}
1589
1590define <8 x i32> @max_gt_v8i32c() {
1591; SSE-LABEL: max_gt_v8i32c:
1592; SSE:       # %bb.0:
1593; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1594; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,5,5,7]
1595; SSE-NEXT:    retq
1596;
1597; AVX-LABEL: max_gt_v8i32c:
1598; AVX:       # %bb.0:
1599; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1600; AVX-NEXT:    retq
1601  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1602  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1603  %3 = icmp sgt <8 x i32> %1, %2
1604  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1605  ret <8 x i32> %4
1606}
1607
1608define <8 x i16> @max_gt_v8i16c() {
1609; SSE-LABEL: max_gt_v8i16c:
1610; SSE:       # %bb.0:
1611; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1612; SSE-NEXT:    retq
1613;
1614; AVX-LABEL: max_gt_v8i16c:
1615; AVX:       # %bb.0:
1616; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1617; AVX-NEXT:    retq
1618  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1619  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1620  %3 = icmp sgt <8 x i16> %1, %2
1621  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1622  ret <8 x i16> %4
1623}
1624
1625define <16 x i16> @max_gt_v16i16c() {
1626; SSE-LABEL: max_gt_v16i16c:
1627; SSE:       # %bb.0:
1628; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1629; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1630; SSE-NEXT:    retq
1631;
1632; AVX-LABEL: max_gt_v16i16c:
1633; AVX:       # %bb.0:
1634; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1635; AVX-NEXT:    retq
1636  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1637  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1638  %3 = icmp sgt <16 x i16> %1, %2
1639  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1640  ret <16 x i16> %4
1641}
1642
1643define <16 x i8> @max_gt_v16i8c() {
1644; SSE-LABEL: max_gt_v16i8c:
1645; SSE:       # %bb.0:
1646; SSE-NEXT:    movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1647; SSE-NEXT:    retq
1648;
1649; AVX-LABEL: max_gt_v16i8c:
1650; AVX:       # %bb.0:
1651; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1652; AVX-NEXT:    retq
1653  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1654  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1655  %3 = icmp sgt <16 x i8> %1, %2
1656  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1657  ret <16 x i8> %4
1658}
1659
1660define <2 x i64> @max_ge_v2i64c() {
1661; SSE-LABEL: max_ge_v2i64c:
1662; SSE:       # %bb.0:
1663; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1664; SSE-NEXT:    retq
1665;
1666; AVX-LABEL: max_ge_v2i64c:
1667; AVX:       # %bb.0:
1668; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1669; AVX-NEXT:    retq
1670  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1671  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1672  %3 = icmp sge <2 x i64> %1, %2
1673  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1674  ret <2 x i64> %4
1675}
1676
1677define <4 x i64> @max_ge_v4i64c() {
1678; SSE-LABEL: max_ge_v4i64c:
1679; SSE:       # %bb.0:
1680; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,7]
1681; SSE-NEXT:    pcmpeqd %xmm0, %xmm0
1682; SSE-NEXT:    retq
1683;
1684; AVX-LABEL: max_ge_v4i64c:
1685; AVX:       # %bb.0:
1686; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1687; AVX-NEXT:    retq
1688  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1689  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1690  %3 = icmp sge <4 x i64> %1, %2
1691  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1692  ret <4 x i64> %4
1693}
1694
1695define <4 x i32> @max_ge_v4i32c() {
1696; SSE-LABEL: max_ge_v4i32c:
1697; SSE:       # %bb.0:
1698; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1699; SSE-NEXT:    retq
1700;
1701; AVX-LABEL: max_ge_v4i32c:
1702; AVX:       # %bb.0:
1703; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1704; AVX-NEXT:    retq
1705  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1706  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1707  %3 = icmp sge <4 x i32> %1, %2
1708  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1709  ret <4 x i32> %4
1710}
1711
1712define <8 x i32> @max_ge_v8i32c() {
1713; SSE-LABEL: max_ge_v8i32c:
1714; SSE:       # %bb.0:
1715; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1716; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,5,5,7]
1717; SSE-NEXT:    retq
1718;
1719; AVX-LABEL: max_ge_v8i32c:
1720; AVX:       # %bb.0:
1721; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1722; AVX-NEXT:    retq
1723  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1724  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1725  %3 = icmp sge <8 x i32> %1, %2
1726  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1727  ret <8 x i32> %4
1728}
1729
1730define <8 x i16> @max_ge_v8i16c() {
1731; SSE-LABEL: max_ge_v8i16c:
1732; SSE:       # %bb.0:
1733; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1734; SSE-NEXT:    retq
1735;
1736; AVX-LABEL: max_ge_v8i16c:
1737; AVX:       # %bb.0:
1738; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1739; AVX-NEXT:    retq
1740  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1741  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1742  %3 = icmp sge <8 x i16> %1, %2
1743  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1744  ret <8 x i16> %4
1745}
1746
1747define <16 x i16> @max_ge_v16i16c() {
1748; SSE-LABEL: max_ge_v16i16c:
1749; SSE:       # %bb.0:
1750; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1751; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1752; SSE-NEXT:    retq
1753;
1754; AVX-LABEL: max_ge_v16i16c:
1755; AVX:       # %bb.0:
1756; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1757; AVX-NEXT:    retq
1758  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1759  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1760  %3 = icmp sge <16 x i16> %1, %2
1761  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1762  ret <16 x i16> %4
1763}
1764
1765define <16 x i8> @max_ge_v16i8c() {
1766; SSE-LABEL: max_ge_v16i8c:
1767; SSE:       # %bb.0:
1768; SSE-NEXT:    movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1769; SSE-NEXT:    retq
1770;
1771; AVX-LABEL: max_ge_v16i8c:
1772; AVX:       # %bb.0:
1773; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1774; AVX-NEXT:    retq
1775  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1776  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1777  %3 = icmp sge <16 x i8> %1, %2
1778  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1779  ret <16 x i8> %4
1780}
1781
1782define <2 x i64> @min_lt_v2i64c() {
1783; SSE-LABEL: min_lt_v2i64c:
1784; SSE:       # %bb.0:
1785; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1786; SSE-NEXT:    retq
1787;
1788; AVX-LABEL: min_lt_v2i64c:
1789; AVX:       # %bb.0:
1790; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1791; AVX-NEXT:    retq
1792  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1793  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1794  %3 = icmp slt <2 x i64> %1, %2
1795  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1796  ret <2 x i64> %4
1797}
1798
1799define <4 x i64> @min_lt_v4i64c() {
1800; SSE-LABEL: min_lt_v4i64c:
1801; SSE:       # %bb.0:
1802; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1803; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,1]
1804; SSE-NEXT:    retq
1805;
1806; AVX-LABEL: min_lt_v4i64c:
1807; AVX:       # %bb.0:
1808; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1809; AVX-NEXT:    retq
1810  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1811  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1812  %3 = icmp slt <4 x i64> %1, %2
1813  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1814  ret <4 x i64> %4
1815}
1816
1817define <4 x i32> @min_lt_v4i32c() {
1818; SSE-LABEL: min_lt_v4i32c:
1819; SSE:       # %bb.0:
1820; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1821; SSE-NEXT:    retq
1822;
1823; AVX-LABEL: min_lt_v4i32c:
1824; AVX:       # %bb.0:
1825; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1826; AVX-NEXT:    retq
1827  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1828  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1829  %3 = icmp slt <4 x i32> %1, %2
1830  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1831  ret <4 x i32> %4
1832}
1833
1834define <8 x i32> @min_lt_v8i32c() {
1835; SSE-LABEL: min_lt_v8i32c:
1836; SSE:       # %bb.0:
1837; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
1838; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,3,3,1]
1839; SSE-NEXT:    retq
1840;
1841; AVX-LABEL: min_lt_v8i32c:
1842; AVX:       # %bb.0:
1843; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
1844; AVX-NEXT:    retq
1845  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1846  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1847  %3 = icmp slt <8 x i32> %1, %2
1848  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1849  ret <8 x i32> %4
1850}
1851
1852define <8 x i16> @min_lt_v8i16c() {
1853; SSE-LABEL: min_lt_v8i16c:
1854; SSE:       # %bb.0:
1855; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1856; SSE-NEXT:    retq
1857;
1858; AVX-LABEL: min_lt_v8i16c:
1859; AVX:       # %bb.0:
1860; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1861; AVX-NEXT:    retq
1862  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1863  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1864  %3 = icmp slt <8 x i16> %1, %2
1865  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1866  ret <8 x i16> %4
1867}
1868
1869define <16 x i16> @min_lt_v16i16c() {
1870; SSE-LABEL: min_lt_v16i16c:
1871; SSE:       # %bb.0:
1872; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
1873; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
1874; SSE-NEXT:    retq
1875;
1876; AVX-LABEL: min_lt_v16i16c:
1877; AVX:       # %bb.0:
1878; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
1879; AVX-NEXT:    retq
1880  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1881  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1882  %3 = icmp slt <16 x i16> %1, %2
1883  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1884  ret <16 x i16> %4
1885}
1886
1887define <16 x i8> @min_lt_v16i8c() {
1888; SSE-LABEL: min_lt_v16i8c:
1889; SSE:       # %bb.0:
1890; SSE-NEXT:    movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1891; SSE-NEXT:    retq
1892;
1893; AVX-LABEL: min_lt_v16i8c:
1894; AVX:       # %bb.0:
1895; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1896; AVX-NEXT:    retq
1897  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1898  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1899  %3 = icmp slt <16 x i8> %1, %2
1900  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1901  ret <16 x i8> %4
1902}
1903
1904define <2 x i64> @min_le_v2i64c() {
1905; SSE-LABEL: min_le_v2i64c:
1906; SSE:       # %bb.0:
1907; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1908; SSE-NEXT:    retq
1909;
1910; AVX-LABEL: min_le_v2i64c:
1911; AVX:       # %bb.0:
1912; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1913; AVX-NEXT:    retq
1914  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1915  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1916  %3 = icmp sle <2 x i64> %1, %2
1917  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1918  ret <2 x i64> %4
1919}
1920
1921define <4 x i64> @min_le_v4i64c() {
1922; SSE-LABEL: min_le_v4i64c:
1923; SSE:       # %bb.0:
1924; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1925; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,1]
1926; SSE-NEXT:    retq
1927;
1928; AVX-LABEL: min_le_v4i64c:
1929; AVX:       # %bb.0:
1930; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1931; AVX-NEXT:    retq
1932  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1933  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1934  %3 = icmp sle <4 x i64> %1, %2
1935  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1936  ret <4 x i64> %4
1937}
1938
1939define <4 x i32> @min_le_v4i32c() {
1940; SSE-LABEL: min_le_v4i32c:
1941; SSE:       # %bb.0:
1942; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1943; SSE-NEXT:    retq
1944;
1945; AVX-LABEL: min_le_v4i32c:
1946; AVX:       # %bb.0:
1947; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1948; AVX-NEXT:    retq
1949  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1950  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1951  %3 = icmp sle <4 x i32> %1, %2
1952  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1953  ret <4 x i32> %4
1954}
1955
1956define <8 x i32> @min_le_v8i32c() {
1957; SSE-LABEL: min_le_v8i32c:
1958; SSE:       # %bb.0:
1959; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
1960; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,3,3,1]
1961; SSE-NEXT:    retq
1962;
1963; AVX-LABEL: min_le_v8i32c:
1964; AVX:       # %bb.0:
1965; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
1966; AVX-NEXT:    retq
1967  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1968  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1969  %3 = icmp sle <8 x i32> %1, %2
1970  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1971  ret <8 x i32> %4
1972}
1973
1974define <8 x i16> @min_le_v8i16c() {
1975; SSE-LABEL: min_le_v8i16c:
1976; SSE:       # %bb.0:
1977; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1978; SSE-NEXT:    retq
1979;
1980; AVX-LABEL: min_le_v8i16c:
1981; AVX:       # %bb.0:
1982; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1983; AVX-NEXT:    retq
1984  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1985  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1986  %3 = icmp sle <8 x i16> %1, %2
1987  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1988  ret <8 x i16> %4
1989}
1990
1991define <16 x i16> @min_le_v16i16c() {
1992; SSE-LABEL: min_le_v16i16c:
1993; SSE:       # %bb.0:
1994; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
1995; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
1996; SSE-NEXT:    retq
1997;
1998; AVX-LABEL: min_le_v16i16c:
1999; AVX:       # %bb.0:
2000; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
2001; AVX-NEXT:    retq
2002  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
2003  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
2004  %3 = icmp sle <16 x i16> %1, %2
2005  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
2006  ret <16 x i16> %4
2007}
2008
2009define <16 x i8> @min_le_v16i8c() {
2010; SSE-LABEL: min_le_v16i8c:
2011; SSE:       # %bb.0:
2012; SSE-NEXT:    movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2013; SSE-NEXT:    retq
2014;
2015; AVX-LABEL: min_le_v16i8c:
2016; AVX:       # %bb.0:
2017; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2018; AVX-NEXT:    retq
2019  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
2020  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
2021  %3 = icmp sle <16 x i8> %1, %2
2022  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
2023  ret <16 x i8> %4
2024}
2025