1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE42
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
9
10;
11; Signed Maximum (GT)
12;
13
14define <2 x i64> @max_gt_v2i64(<2 x i64> %a, <2 x i64> %b) {
15; SSE2-LABEL: max_gt_v2i64:
16; SSE2:       # %bb.0:
17; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
18; SSE2-NEXT:    movdqa %xmm1, %xmm3
19; SSE2-NEXT:    pxor %xmm2, %xmm3
20; SSE2-NEXT:    pxor %xmm0, %xmm2
21; SSE2-NEXT:    movdqa %xmm2, %xmm4
22; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
23; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
24; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
25; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
26; SSE2-NEXT:    pand %xmm5, %xmm2
27; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
28; SSE2-NEXT:    por %xmm2, %xmm3
29; SSE2-NEXT:    pand %xmm3, %xmm0
30; SSE2-NEXT:    pandn %xmm1, %xmm3
31; SSE2-NEXT:    por %xmm3, %xmm0
32; SSE2-NEXT:    retq
33;
34; SSE41-LABEL: max_gt_v2i64:
35; SSE41:       # %bb.0:
36; SSE41-NEXT:    movdqa %xmm0, %xmm2
37; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
38; SSE41-NEXT:    movdqa %xmm1, %xmm3
39; SSE41-NEXT:    pxor %xmm0, %xmm3
40; SSE41-NEXT:    pxor %xmm2, %xmm0
41; SSE41-NEXT:    movdqa %xmm0, %xmm4
42; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
43; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
44; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
45; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
46; SSE41-NEXT:    pand %xmm5, %xmm0
47; SSE41-NEXT:    por %xmm4, %xmm0
48; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
49; SSE41-NEXT:    movapd %xmm1, %xmm0
50; SSE41-NEXT:    retq
51;
52; SSE42-LABEL: max_gt_v2i64:
53; SSE42:       # %bb.0:
54; SSE42-NEXT:    movdqa %xmm0, %xmm2
55; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
56; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
57; SSE42-NEXT:    movapd %xmm1, %xmm0
58; SSE42-NEXT:    retq
59;
60; AVX1-LABEL: max_gt_v2i64:
61; AVX1:       # %bb.0:
62; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
63; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
64; AVX1-NEXT:    retq
65;
66; AVX2-LABEL: max_gt_v2i64:
67; AVX2:       # %bb.0:
68; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
69; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
70; AVX2-NEXT:    retq
71;
72; AVX512-LABEL: max_gt_v2i64:
73; AVX512:       # %bb.0:
74; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
75; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
76; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
77; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
78; AVX512-NEXT:    vzeroupper
79; AVX512-NEXT:    retq
80  %1 = icmp sgt <2 x i64> %a, %b
81  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
82  ret <2 x i64> %2
83}
84
85define <4 x i64> @max_gt_v4i64(<4 x i64> %a, <4 x i64> %b) {
86; SSE2-LABEL: max_gt_v4i64:
87; SSE2:       # %bb.0:
88; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
89; SSE2-NEXT:    movdqa %xmm2, %xmm5
90; SSE2-NEXT:    pxor %xmm4, %xmm5
91; SSE2-NEXT:    movdqa %xmm0, %xmm6
92; SSE2-NEXT:    pxor %xmm4, %xmm6
93; SSE2-NEXT:    movdqa %xmm6, %xmm7
94; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
95; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
96; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
97; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
98; SSE2-NEXT:    pand %xmm8, %xmm5
99; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
100; SSE2-NEXT:    por %xmm5, %xmm6
101; SSE2-NEXT:    pand %xmm6, %xmm0
102; SSE2-NEXT:    pandn %xmm2, %xmm6
103; SSE2-NEXT:    por %xmm6, %xmm0
104; SSE2-NEXT:    movdqa %xmm3, %xmm2
105; SSE2-NEXT:    pxor %xmm4, %xmm2
106; SSE2-NEXT:    pxor %xmm1, %xmm4
107; SSE2-NEXT:    movdqa %xmm4, %xmm5
108; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
109; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
110; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
111; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
112; SSE2-NEXT:    pand %xmm6, %xmm2
113; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
114; SSE2-NEXT:    por %xmm2, %xmm4
115; SSE2-NEXT:    pand %xmm4, %xmm1
116; SSE2-NEXT:    pandn %xmm3, %xmm4
117; SSE2-NEXT:    por %xmm4, %xmm1
118; SSE2-NEXT:    retq
119;
120; SSE41-LABEL: max_gt_v4i64:
121; SSE41:       # %bb.0:
122; SSE41-NEXT:    movdqa %xmm0, %xmm4
123; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
124; SSE41-NEXT:    movdqa %xmm2, %xmm6
125; SSE41-NEXT:    pxor %xmm5, %xmm6
126; SSE41-NEXT:    movdqa %xmm0, %xmm7
127; SSE41-NEXT:    pxor %xmm5, %xmm7
128; SSE41-NEXT:    movdqa %xmm7, %xmm0
129; SSE41-NEXT:    pcmpgtd %xmm6, %xmm0
130; SSE41-NEXT:    pshufd {{.*#+}} xmm8 = xmm0[0,0,2,2]
131; SSE41-NEXT:    pcmpeqd %xmm6, %xmm7
132; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
133; SSE41-NEXT:    pand %xmm8, %xmm6
134; SSE41-NEXT:    por %xmm6, %xmm0
135; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
136; SSE41-NEXT:    movdqa %xmm3, %xmm0
137; SSE41-NEXT:    pxor %xmm5, %xmm0
138; SSE41-NEXT:    pxor %xmm1, %xmm5
139; SSE41-NEXT:    movdqa %xmm5, %xmm4
140; SSE41-NEXT:    pcmpgtd %xmm0, %xmm4
141; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
142; SSE41-NEXT:    pcmpeqd %xmm0, %xmm5
143; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
144; SSE41-NEXT:    pand %xmm6, %xmm0
145; SSE41-NEXT:    por %xmm4, %xmm0
146; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
147; SSE41-NEXT:    movapd %xmm2, %xmm0
148; SSE41-NEXT:    movapd %xmm3, %xmm1
149; SSE41-NEXT:    retq
150;
151; SSE42-LABEL: max_gt_v4i64:
152; SSE42:       # %bb.0:
153; SSE42-NEXT:    movdqa %xmm0, %xmm4
154; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
155; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
156; SSE42-NEXT:    movdqa %xmm1, %xmm0
157; SSE42-NEXT:    pcmpgtq %xmm3, %xmm0
158; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
159; SSE42-NEXT:    movapd %xmm2, %xmm0
160; SSE42-NEXT:    movapd %xmm3, %xmm1
161; SSE42-NEXT:    retq
162;
163; AVX1-LABEL: max_gt_v4i64:
164; AVX1:       # %bb.0:
165; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
166; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
167; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
168; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm3
169; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
170; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
171; AVX1-NEXT:    retq
172;
173; AVX2-LABEL: max_gt_v4i64:
174; AVX2:       # %bb.0:
175; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
176; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
177; AVX2-NEXT:    retq
178;
179; AVX512-LABEL: max_gt_v4i64:
180; AVX512:       # %bb.0:
181; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
182; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
183; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
184; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
185; AVX512-NEXT:    retq
186  %1 = icmp sgt <4 x i64> %a, %b
187  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
188  ret <4 x i64> %2
189}
190
191define <4 x i32> @max_gt_v4i32(<4 x i32> %a, <4 x i32> %b) {
192; SSE2-LABEL: max_gt_v4i32:
193; SSE2:       # %bb.0:
194; SSE2-NEXT:    movdqa %xmm0, %xmm2
195; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
196; SSE2-NEXT:    pand %xmm2, %xmm0
197; SSE2-NEXT:    pandn %xmm1, %xmm2
198; SSE2-NEXT:    por %xmm0, %xmm2
199; SSE2-NEXT:    movdqa %xmm2, %xmm0
200; SSE2-NEXT:    retq
201;
202; SSE41-LABEL: max_gt_v4i32:
203; SSE41:       # %bb.0:
204; SSE41-NEXT:    pmaxsd %xmm1, %xmm0
205; SSE41-NEXT:    retq
206;
207; SSE42-LABEL: max_gt_v4i32:
208; SSE42:       # %bb.0:
209; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
210; SSE42-NEXT:    retq
211;
212; AVX-LABEL: max_gt_v4i32:
213; AVX:       # %bb.0:
214; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
215; AVX-NEXT:    retq
216  %1 = icmp sgt <4 x i32> %a, %b
217  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
218  ret <4 x i32> %2
219}
220
221define <8 x i32> @max_gt_v8i32(<8 x i32> %a, <8 x i32> %b) {
222; SSE2-LABEL: max_gt_v8i32:
223; SSE2:       # %bb.0:
224; SSE2-NEXT:    movdqa %xmm0, %xmm4
225; SSE2-NEXT:    pcmpgtd %xmm2, %xmm4
226; SSE2-NEXT:    pand %xmm4, %xmm0
227; SSE2-NEXT:    pandn %xmm2, %xmm4
228; SSE2-NEXT:    por %xmm0, %xmm4
229; SSE2-NEXT:    movdqa %xmm1, %xmm2
230; SSE2-NEXT:    pcmpgtd %xmm3, %xmm2
231; SSE2-NEXT:    pand %xmm2, %xmm1
232; SSE2-NEXT:    pandn %xmm3, %xmm2
233; SSE2-NEXT:    por %xmm1, %xmm2
234; SSE2-NEXT:    movdqa %xmm4, %xmm0
235; SSE2-NEXT:    movdqa %xmm2, %xmm1
236; SSE2-NEXT:    retq
237;
238; SSE41-LABEL: max_gt_v8i32:
239; SSE41:       # %bb.0:
240; SSE41-NEXT:    pmaxsd %xmm2, %xmm0
241; SSE41-NEXT:    pmaxsd %xmm3, %xmm1
242; SSE41-NEXT:    retq
243;
244; SSE42-LABEL: max_gt_v8i32:
245; SSE42:       # %bb.0:
246; SSE42-NEXT:    pmaxsd %xmm2, %xmm0
247; SSE42-NEXT:    pmaxsd %xmm3, %xmm1
248; SSE42-NEXT:    retq
249;
250; AVX1-LABEL: max_gt_v8i32:
251; AVX1:       # %bb.0:
252; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
253; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
254; AVX1-NEXT:    vpmaxsd %xmm2, %xmm3, %xmm2
255; AVX1-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
256; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
257; AVX1-NEXT:    retq
258;
259; AVX2-LABEL: max_gt_v8i32:
260; AVX2:       # %bb.0:
261; AVX2-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
262; AVX2-NEXT:    retq
263;
264; AVX512-LABEL: max_gt_v8i32:
265; AVX512:       # %bb.0:
266; AVX512-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
267; AVX512-NEXT:    retq
268  %1 = icmp sgt <8 x i32> %a, %b
269  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
270  ret <8 x i32> %2
271}
272
273define <8 x i16> @max_gt_v8i16(<8 x i16> %a, <8 x i16> %b) {
274; SSE-LABEL: max_gt_v8i16:
275; SSE:       # %bb.0:
276; SSE-NEXT:    pmaxsw %xmm1, %xmm0
277; SSE-NEXT:    retq
278;
279; AVX-LABEL: max_gt_v8i16:
280; AVX:       # %bb.0:
281; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
282; AVX-NEXT:    retq
283  %1 = icmp sgt <8 x i16> %a, %b
284  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
285  ret <8 x i16> %2
286}
287
288define <16 x i16> @max_gt_v16i16(<16 x i16> %a, <16 x i16> %b) {
289; SSE-LABEL: max_gt_v16i16:
290; SSE:       # %bb.0:
291; SSE-NEXT:    pmaxsw %xmm2, %xmm0
292; SSE-NEXT:    pmaxsw %xmm3, %xmm1
293; SSE-NEXT:    retq
294;
295; AVX1-LABEL: max_gt_v16i16:
296; AVX1:       # %bb.0:
297; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
298; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
299; AVX1-NEXT:    vpmaxsw %xmm2, %xmm3, %xmm2
300; AVX1-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
301; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
302; AVX1-NEXT:    retq
303;
304; AVX2-LABEL: max_gt_v16i16:
305; AVX2:       # %bb.0:
306; AVX2-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
307; AVX2-NEXT:    retq
308;
309; AVX512-LABEL: max_gt_v16i16:
310; AVX512:       # %bb.0:
311; AVX512-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
312; AVX512-NEXT:    retq
313  %1 = icmp sgt <16 x i16> %a, %b
314  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
315  ret <16 x i16> %2
316}
317
318define <16 x i8> @max_gt_v16i8(<16 x i8> %a, <16 x i8> %b) {
319; SSE2-LABEL: max_gt_v16i8:
320; SSE2:       # %bb.0:
321; SSE2-NEXT:    movdqa %xmm0, %xmm2
322; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
323; SSE2-NEXT:    pand %xmm2, %xmm0
324; SSE2-NEXT:    pandn %xmm1, %xmm2
325; SSE2-NEXT:    por %xmm0, %xmm2
326; SSE2-NEXT:    movdqa %xmm2, %xmm0
327; SSE2-NEXT:    retq
328;
329; SSE41-LABEL: max_gt_v16i8:
330; SSE41:       # %bb.0:
331; SSE41-NEXT:    pmaxsb %xmm1, %xmm0
332; SSE41-NEXT:    retq
333;
334; SSE42-LABEL: max_gt_v16i8:
335; SSE42:       # %bb.0:
336; SSE42-NEXT:    pmaxsb %xmm1, %xmm0
337; SSE42-NEXT:    retq
338;
339; AVX-LABEL: max_gt_v16i8:
340; AVX:       # %bb.0:
341; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
342; AVX-NEXT:    retq
343  %1 = icmp sgt <16 x i8> %a, %b
344  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
345  ret <16 x i8> %2
346}
347
348define <32 x i8> @max_gt_v32i8(<32 x i8> %a, <32 x i8> %b) {
349; SSE2-LABEL: max_gt_v32i8:
350; SSE2:       # %bb.0:
351; SSE2-NEXT:    movdqa %xmm0, %xmm4
352; SSE2-NEXT:    pcmpgtb %xmm2, %xmm4
353; SSE2-NEXT:    pand %xmm4, %xmm0
354; SSE2-NEXT:    pandn %xmm2, %xmm4
355; SSE2-NEXT:    por %xmm0, %xmm4
356; SSE2-NEXT:    movdqa %xmm1, %xmm2
357; SSE2-NEXT:    pcmpgtb %xmm3, %xmm2
358; SSE2-NEXT:    pand %xmm2, %xmm1
359; SSE2-NEXT:    pandn %xmm3, %xmm2
360; SSE2-NEXT:    por %xmm1, %xmm2
361; SSE2-NEXT:    movdqa %xmm4, %xmm0
362; SSE2-NEXT:    movdqa %xmm2, %xmm1
363; SSE2-NEXT:    retq
364;
365; SSE41-LABEL: max_gt_v32i8:
366; SSE41:       # %bb.0:
367; SSE41-NEXT:    pmaxsb %xmm2, %xmm0
368; SSE41-NEXT:    pmaxsb %xmm3, %xmm1
369; SSE41-NEXT:    retq
370;
371; SSE42-LABEL: max_gt_v32i8:
372; SSE42:       # %bb.0:
373; SSE42-NEXT:    pmaxsb %xmm2, %xmm0
374; SSE42-NEXT:    pmaxsb %xmm3, %xmm1
375; SSE42-NEXT:    retq
376;
377; AVX1-LABEL: max_gt_v32i8:
378; AVX1:       # %bb.0:
379; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
380; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
381; AVX1-NEXT:    vpmaxsb %xmm2, %xmm3, %xmm2
382; AVX1-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
383; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
384; AVX1-NEXT:    retq
385;
386; AVX2-LABEL: max_gt_v32i8:
387; AVX2:       # %bb.0:
388; AVX2-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
389; AVX2-NEXT:    retq
390;
391; AVX512-LABEL: max_gt_v32i8:
392; AVX512:       # %bb.0:
393; AVX512-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
394; AVX512-NEXT:    retq
395  %1 = icmp sgt <32 x i8> %a, %b
396  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
397  ret <32 x i8> %2
398}
399
400;
401; Signed Maximum (GE)
402;
403
404define <2 x i64> @max_ge_v2i64(<2 x i64> %a, <2 x i64> %b) {
405; SSE2-LABEL: max_ge_v2i64:
406; SSE2:       # %bb.0:
407; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
408; SSE2-NEXT:    movdqa %xmm1, %xmm3
409; SSE2-NEXT:    pxor %xmm2, %xmm3
410; SSE2-NEXT:    pxor %xmm0, %xmm2
411; SSE2-NEXT:    movdqa %xmm2, %xmm4
412; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
413; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
414; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
415; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
416; SSE2-NEXT:    pand %xmm5, %xmm2
417; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
418; SSE2-NEXT:    por %xmm2, %xmm3
419; SSE2-NEXT:    pand %xmm3, %xmm0
420; SSE2-NEXT:    pandn %xmm1, %xmm3
421; SSE2-NEXT:    por %xmm3, %xmm0
422; SSE2-NEXT:    retq
423;
424; SSE41-LABEL: max_ge_v2i64:
425; SSE41:       # %bb.0:
426; SSE41-NEXT:    movdqa %xmm0, %xmm2
427; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
428; SSE41-NEXT:    movdqa %xmm1, %xmm3
429; SSE41-NEXT:    pxor %xmm0, %xmm3
430; SSE41-NEXT:    pxor %xmm2, %xmm0
431; SSE41-NEXT:    movdqa %xmm0, %xmm4
432; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
433; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
434; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
435; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
436; SSE41-NEXT:    pand %xmm5, %xmm0
437; SSE41-NEXT:    por %xmm4, %xmm0
438; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
439; SSE41-NEXT:    movapd %xmm1, %xmm0
440; SSE41-NEXT:    retq
441;
442; SSE42-LABEL: max_ge_v2i64:
443; SSE42:       # %bb.0:
444; SSE42-NEXT:    movdqa %xmm0, %xmm2
445; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
446; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
447; SSE42-NEXT:    movapd %xmm1, %xmm0
448; SSE42-NEXT:    retq
449;
450; AVX1-LABEL: max_ge_v2i64:
451; AVX1:       # %bb.0:
452; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
453; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
454; AVX1-NEXT:    retq
455;
456; AVX2-LABEL: max_ge_v2i64:
457; AVX2:       # %bb.0:
458; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm2
459; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
460; AVX2-NEXT:    retq
461;
462; AVX512-LABEL: max_ge_v2i64:
463; AVX512:       # %bb.0:
464; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
465; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
466; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
467; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
468; AVX512-NEXT:    vzeroupper
469; AVX512-NEXT:    retq
470  %1 = icmp sge <2 x i64> %a, %b
471  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
472  ret <2 x i64> %2
473}
474
475define <4 x i64> @max_ge_v4i64(<4 x i64> %a, <4 x i64> %b) {
476; SSE2-LABEL: max_ge_v4i64:
477; SSE2:       # %bb.0:
478; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
479; SSE2-NEXT:    movdqa %xmm2, %xmm5
480; SSE2-NEXT:    pxor %xmm4, %xmm5
481; SSE2-NEXT:    movdqa %xmm0, %xmm6
482; SSE2-NEXT:    pxor %xmm4, %xmm6
483; SSE2-NEXT:    movdqa %xmm6, %xmm7
484; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
485; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
486; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
487; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
488; SSE2-NEXT:    pand %xmm8, %xmm5
489; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
490; SSE2-NEXT:    por %xmm5, %xmm6
491; SSE2-NEXT:    pand %xmm6, %xmm0
492; SSE2-NEXT:    pandn %xmm2, %xmm6
493; SSE2-NEXT:    por %xmm6, %xmm0
494; SSE2-NEXT:    movdqa %xmm3, %xmm2
495; SSE2-NEXT:    pxor %xmm4, %xmm2
496; SSE2-NEXT:    pxor %xmm1, %xmm4
497; SSE2-NEXT:    movdqa %xmm4, %xmm5
498; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
499; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
500; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
501; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
502; SSE2-NEXT:    pand %xmm6, %xmm2
503; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
504; SSE2-NEXT:    por %xmm2, %xmm4
505; SSE2-NEXT:    pand %xmm4, %xmm1
506; SSE2-NEXT:    pandn %xmm3, %xmm4
507; SSE2-NEXT:    por %xmm4, %xmm1
508; SSE2-NEXT:    retq
509;
510; SSE41-LABEL: max_ge_v4i64:
511; SSE41:       # %bb.0:
512; SSE41-NEXT:    movdqa %xmm0, %xmm4
513; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
514; SSE41-NEXT:    movdqa %xmm2, %xmm6
515; SSE41-NEXT:    pxor %xmm5, %xmm6
516; SSE41-NEXT:    movdqa %xmm0, %xmm7
517; SSE41-NEXT:    pxor %xmm5, %xmm7
518; SSE41-NEXT:    movdqa %xmm7, %xmm0
519; SSE41-NEXT:    pcmpgtd %xmm6, %xmm0
520; SSE41-NEXT:    pshufd {{.*#+}} xmm8 = xmm0[0,0,2,2]
521; SSE41-NEXT:    pcmpeqd %xmm6, %xmm7
522; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
523; SSE41-NEXT:    pand %xmm8, %xmm6
524; SSE41-NEXT:    por %xmm6, %xmm0
525; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
526; SSE41-NEXT:    movdqa %xmm3, %xmm0
527; SSE41-NEXT:    pxor %xmm5, %xmm0
528; SSE41-NEXT:    pxor %xmm1, %xmm5
529; SSE41-NEXT:    movdqa %xmm5, %xmm4
530; SSE41-NEXT:    pcmpgtd %xmm0, %xmm4
531; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
532; SSE41-NEXT:    pcmpeqd %xmm0, %xmm5
533; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
534; SSE41-NEXT:    pand %xmm6, %xmm0
535; SSE41-NEXT:    por %xmm4, %xmm0
536; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
537; SSE41-NEXT:    movapd %xmm2, %xmm0
538; SSE41-NEXT:    movapd %xmm3, %xmm1
539; SSE41-NEXT:    retq
540;
541; SSE42-LABEL: max_ge_v4i64:
542; SSE42:       # %bb.0:
543; SSE42-NEXT:    movdqa %xmm0, %xmm4
544; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
545; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
546; SSE42-NEXT:    movdqa %xmm1, %xmm0
547; SSE42-NEXT:    pcmpgtq %xmm3, %xmm0
548; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
549; SSE42-NEXT:    movapd %xmm2, %xmm0
550; SSE42-NEXT:    movapd %xmm3, %xmm1
551; SSE42-NEXT:    retq
552;
553; AVX1-LABEL: max_ge_v4i64:
554; AVX1:       # %bb.0:
555; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
556; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
557; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
558; AVX1-NEXT:    vpcmpgtq %xmm1, %xmm0, %xmm3
559; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
560; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
561; AVX1-NEXT:    retq
562;
563; AVX2-LABEL: max_ge_v4i64:
564; AVX2:       # %bb.0:
565; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm0, %ymm2
566; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
567; AVX2-NEXT:    retq
568;
569; AVX512-LABEL: max_ge_v4i64:
570; AVX512:       # %bb.0:
571; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
572; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
573; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
574; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
575; AVX512-NEXT:    retq
576  %1 = icmp sge <4 x i64> %a, %b
577  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
578  ret <4 x i64> %2
579}
580
581define <4 x i32> @max_ge_v4i32(<4 x i32> %a, <4 x i32> %b) {
582; SSE2-LABEL: max_ge_v4i32:
583; SSE2:       # %bb.0:
584; SSE2-NEXT:    movdqa %xmm0, %xmm2
585; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
586; SSE2-NEXT:    pand %xmm2, %xmm0
587; SSE2-NEXT:    pandn %xmm1, %xmm2
588; SSE2-NEXT:    por %xmm0, %xmm2
589; SSE2-NEXT:    movdqa %xmm2, %xmm0
590; SSE2-NEXT:    retq
591;
592; SSE41-LABEL: max_ge_v4i32:
593; SSE41:       # %bb.0:
594; SSE41-NEXT:    pmaxsd %xmm1, %xmm0
595; SSE41-NEXT:    retq
596;
597; SSE42-LABEL: max_ge_v4i32:
598; SSE42:       # %bb.0:
599; SSE42-NEXT:    pmaxsd %xmm1, %xmm0
600; SSE42-NEXT:    retq
601;
602; AVX-LABEL: max_ge_v4i32:
603; AVX:       # %bb.0:
604; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
605; AVX-NEXT:    retq
606  %1 = icmp sge <4 x i32> %a, %b
607  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
608  ret <4 x i32> %2
609}
610
611define <8 x i32> @max_ge_v8i32(<8 x i32> %a, <8 x i32> %b) {
612; SSE2-LABEL: max_ge_v8i32:
613; SSE2:       # %bb.0:
614; SSE2-NEXT:    movdqa %xmm0, %xmm4
615; SSE2-NEXT:    pcmpgtd %xmm2, %xmm4
616; SSE2-NEXT:    pand %xmm4, %xmm0
617; SSE2-NEXT:    pandn %xmm2, %xmm4
618; SSE2-NEXT:    por %xmm0, %xmm4
619; SSE2-NEXT:    movdqa %xmm1, %xmm2
620; SSE2-NEXT:    pcmpgtd %xmm3, %xmm2
621; SSE2-NEXT:    pand %xmm2, %xmm1
622; SSE2-NEXT:    pandn %xmm3, %xmm2
623; SSE2-NEXT:    por %xmm1, %xmm2
624; SSE2-NEXT:    movdqa %xmm4, %xmm0
625; SSE2-NEXT:    movdqa %xmm2, %xmm1
626; SSE2-NEXT:    retq
627;
628; SSE41-LABEL: max_ge_v8i32:
629; SSE41:       # %bb.0:
630; SSE41-NEXT:    pmaxsd %xmm2, %xmm0
631; SSE41-NEXT:    pmaxsd %xmm3, %xmm1
632; SSE41-NEXT:    retq
633;
634; SSE42-LABEL: max_ge_v8i32:
635; SSE42:       # %bb.0:
636; SSE42-NEXT:    pmaxsd %xmm2, %xmm0
637; SSE42-NEXT:    pmaxsd %xmm3, %xmm1
638; SSE42-NEXT:    retq
639;
640; AVX1-LABEL: max_ge_v8i32:
641; AVX1:       # %bb.0:
642; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
643; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
644; AVX1-NEXT:    vpmaxsd %xmm2, %xmm3, %xmm2
645; AVX1-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
646; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
647; AVX1-NEXT:    retq
648;
649; AVX2-LABEL: max_ge_v8i32:
650; AVX2:       # %bb.0:
651; AVX2-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
652; AVX2-NEXT:    retq
653;
654; AVX512-LABEL: max_ge_v8i32:
655; AVX512:       # %bb.0:
656; AVX512-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
657; AVX512-NEXT:    retq
658  %1 = icmp sge <8 x i32> %a, %b
659  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
660  ret <8 x i32> %2
661}
662
663define <8 x i16> @max_ge_v8i16(<8 x i16> %a, <8 x i16> %b) {
664; SSE-LABEL: max_ge_v8i16:
665; SSE:       # %bb.0:
666; SSE-NEXT:    pmaxsw %xmm1, %xmm0
667; SSE-NEXT:    retq
668;
669; AVX-LABEL: max_ge_v8i16:
670; AVX:       # %bb.0:
671; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
672; AVX-NEXT:    retq
673  %1 = icmp sge <8 x i16> %a, %b
674  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
675  ret <8 x i16> %2
676}
677
678define <16 x i16> @max_ge_v16i16(<16 x i16> %a, <16 x i16> %b) {
679; SSE-LABEL: max_ge_v16i16:
680; SSE:       # %bb.0:
681; SSE-NEXT:    pmaxsw %xmm2, %xmm0
682; SSE-NEXT:    pmaxsw %xmm3, %xmm1
683; SSE-NEXT:    retq
684;
685; AVX1-LABEL: max_ge_v16i16:
686; AVX1:       # %bb.0:
687; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
688; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
689; AVX1-NEXT:    vpmaxsw %xmm2, %xmm3, %xmm2
690; AVX1-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
691; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
692; AVX1-NEXT:    retq
693;
694; AVX2-LABEL: max_ge_v16i16:
695; AVX2:       # %bb.0:
696; AVX2-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
697; AVX2-NEXT:    retq
698;
699; AVX512-LABEL: max_ge_v16i16:
700; AVX512:       # %bb.0:
701; AVX512-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
702; AVX512-NEXT:    retq
703  %1 = icmp sge <16 x i16> %a, %b
704  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
705  ret <16 x i16> %2
706}
707
708define <16 x i8> @max_ge_v16i8(<16 x i8> %a, <16 x i8> %b) {
709; SSE2-LABEL: max_ge_v16i8:
710; SSE2:       # %bb.0:
711; SSE2-NEXT:    movdqa %xmm0, %xmm2
712; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
713; SSE2-NEXT:    pand %xmm2, %xmm0
714; SSE2-NEXT:    pandn %xmm1, %xmm2
715; SSE2-NEXT:    por %xmm0, %xmm2
716; SSE2-NEXT:    movdqa %xmm2, %xmm0
717; SSE2-NEXT:    retq
718;
719; SSE41-LABEL: max_ge_v16i8:
720; SSE41:       # %bb.0:
721; SSE41-NEXT:    pmaxsb %xmm1, %xmm0
722; SSE41-NEXT:    retq
723;
724; SSE42-LABEL: max_ge_v16i8:
725; SSE42:       # %bb.0:
726; SSE42-NEXT:    pmaxsb %xmm1, %xmm0
727; SSE42-NEXT:    retq
728;
729; AVX-LABEL: max_ge_v16i8:
730; AVX:       # %bb.0:
731; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
732; AVX-NEXT:    retq
733  %1 = icmp sge <16 x i8> %a, %b
734  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
735  ret <16 x i8> %2
736}
737
738define <32 x i8> @max_ge_v32i8(<32 x i8> %a, <32 x i8> %b) {
739; SSE2-LABEL: max_ge_v32i8:
740; SSE2:       # %bb.0:
741; SSE2-NEXT:    movdqa %xmm0, %xmm4
742; SSE2-NEXT:    pcmpgtb %xmm2, %xmm4
743; SSE2-NEXT:    pand %xmm4, %xmm0
744; SSE2-NEXT:    pandn %xmm2, %xmm4
745; SSE2-NEXT:    por %xmm0, %xmm4
746; SSE2-NEXT:    movdqa %xmm1, %xmm2
747; SSE2-NEXT:    pcmpgtb %xmm3, %xmm2
748; SSE2-NEXT:    pand %xmm2, %xmm1
749; SSE2-NEXT:    pandn %xmm3, %xmm2
750; SSE2-NEXT:    por %xmm1, %xmm2
751; SSE2-NEXT:    movdqa %xmm4, %xmm0
752; SSE2-NEXT:    movdqa %xmm2, %xmm1
753; SSE2-NEXT:    retq
754;
755; SSE41-LABEL: max_ge_v32i8:
756; SSE41:       # %bb.0:
757; SSE41-NEXT:    pmaxsb %xmm2, %xmm0
758; SSE41-NEXT:    pmaxsb %xmm3, %xmm1
759; SSE41-NEXT:    retq
760;
761; SSE42-LABEL: max_ge_v32i8:
762; SSE42:       # %bb.0:
763; SSE42-NEXT:    pmaxsb %xmm2, %xmm0
764; SSE42-NEXT:    pmaxsb %xmm3, %xmm1
765; SSE42-NEXT:    retq
766;
767; AVX1-LABEL: max_ge_v32i8:
768; AVX1:       # %bb.0:
769; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
770; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
771; AVX1-NEXT:    vpmaxsb %xmm2, %xmm3, %xmm2
772; AVX1-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
773; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
774; AVX1-NEXT:    retq
775;
776; AVX2-LABEL: max_ge_v32i8:
777; AVX2:       # %bb.0:
778; AVX2-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
779; AVX2-NEXT:    retq
780;
781; AVX512-LABEL: max_ge_v32i8:
782; AVX512:       # %bb.0:
783; AVX512-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
784; AVX512-NEXT:    retq
785  %1 = icmp sge <32 x i8> %a, %b
786  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
787  ret <32 x i8> %2
788}
789
790;
791; Signed Minimum (LT)
792;
793
794define <2 x i64> @min_lt_v2i64(<2 x i64> %a, <2 x i64> %b) {
795; SSE2-LABEL: min_lt_v2i64:
796; SSE2:       # %bb.0:
797; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
798; SSE2-NEXT:    movdqa %xmm0, %xmm3
799; SSE2-NEXT:    pxor %xmm2, %xmm3
800; SSE2-NEXT:    pxor %xmm1, %xmm2
801; SSE2-NEXT:    movdqa %xmm2, %xmm4
802; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
803; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
804; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
805; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
806; SSE2-NEXT:    pand %xmm5, %xmm2
807; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
808; SSE2-NEXT:    por %xmm2, %xmm3
809; SSE2-NEXT:    pand %xmm3, %xmm0
810; SSE2-NEXT:    pandn %xmm1, %xmm3
811; SSE2-NEXT:    por %xmm3, %xmm0
812; SSE2-NEXT:    retq
813;
814; SSE41-LABEL: min_lt_v2i64:
815; SSE41:       # %bb.0:
816; SSE41-NEXT:    movdqa %xmm0, %xmm2
817; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
818; SSE41-NEXT:    movdqa %xmm2, %xmm3
819; SSE41-NEXT:    pxor %xmm0, %xmm3
820; SSE41-NEXT:    pxor %xmm1, %xmm0
821; SSE41-NEXT:    movdqa %xmm0, %xmm4
822; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
823; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
824; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
825; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
826; SSE41-NEXT:    pand %xmm5, %xmm0
827; SSE41-NEXT:    por %xmm4, %xmm0
828; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
829; SSE41-NEXT:    movapd %xmm1, %xmm0
830; SSE41-NEXT:    retq
831;
832; SSE42-LABEL: min_lt_v2i64:
833; SSE42:       # %bb.0:
834; SSE42-NEXT:    movdqa %xmm0, %xmm2
835; SSE42-NEXT:    movdqa %xmm1, %xmm0
836; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
837; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
838; SSE42-NEXT:    movapd %xmm1, %xmm0
839; SSE42-NEXT:    retq
840;
841; AVX1-LABEL: min_lt_v2i64:
842; AVX1:       # %bb.0:
843; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
844; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
845; AVX1-NEXT:    retq
846;
847; AVX2-LABEL: min_lt_v2i64:
848; AVX2:       # %bb.0:
849; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
850; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
851; AVX2-NEXT:    retq
852;
853; AVX512-LABEL: min_lt_v2i64:
854; AVX512:       # %bb.0:
855; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
856; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
857; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
858; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
859; AVX512-NEXT:    vzeroupper
860; AVX512-NEXT:    retq
861  %1 = icmp slt <2 x i64> %a, %b
862  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
863  ret <2 x i64> %2
864}
865
866define <4 x i64> @min_lt_v4i64(<4 x i64> %a, <4 x i64> %b) {
867; SSE2-LABEL: min_lt_v4i64:
868; SSE2:       # %bb.0:
869; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
870; SSE2-NEXT:    movdqa %xmm0, %xmm5
871; SSE2-NEXT:    pxor %xmm4, %xmm5
872; SSE2-NEXT:    movdqa %xmm2, %xmm6
873; SSE2-NEXT:    pxor %xmm4, %xmm6
874; SSE2-NEXT:    movdqa %xmm6, %xmm7
875; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
876; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
877; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
878; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
879; SSE2-NEXT:    pand %xmm8, %xmm5
880; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
881; SSE2-NEXT:    por %xmm5, %xmm6
882; SSE2-NEXT:    pand %xmm6, %xmm0
883; SSE2-NEXT:    pandn %xmm2, %xmm6
884; SSE2-NEXT:    por %xmm6, %xmm0
885; SSE2-NEXT:    movdqa %xmm1, %xmm2
886; SSE2-NEXT:    pxor %xmm4, %xmm2
887; SSE2-NEXT:    pxor %xmm3, %xmm4
888; SSE2-NEXT:    movdqa %xmm4, %xmm5
889; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
890; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
891; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
892; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
893; SSE2-NEXT:    pand %xmm6, %xmm2
894; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
895; SSE2-NEXT:    por %xmm2, %xmm4
896; SSE2-NEXT:    pand %xmm4, %xmm1
897; SSE2-NEXT:    pandn %xmm3, %xmm4
898; SSE2-NEXT:    por %xmm4, %xmm1
899; SSE2-NEXT:    retq
900;
901; SSE41-LABEL: min_lt_v4i64:
902; SSE41:       # %bb.0:
903; SSE41-NEXT:    movdqa %xmm0, %xmm4
904; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
905; SSE41-NEXT:    pxor %xmm5, %xmm0
906; SSE41-NEXT:    movdqa %xmm2, %xmm6
907; SSE41-NEXT:    pxor %xmm5, %xmm6
908; SSE41-NEXT:    movdqa %xmm6, %xmm7
909; SSE41-NEXT:    pcmpgtd %xmm0, %xmm7
910; SSE41-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
911; SSE41-NEXT:    pcmpeqd %xmm0, %xmm6
912; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
913; SSE41-NEXT:    pand %xmm8, %xmm0
914; SSE41-NEXT:    por %xmm7, %xmm0
915; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
916; SSE41-NEXT:    movdqa %xmm1, %xmm0
917; SSE41-NEXT:    pxor %xmm5, %xmm0
918; SSE41-NEXT:    pxor %xmm3, %xmm5
919; SSE41-NEXT:    movdqa %xmm5, %xmm4
920; SSE41-NEXT:    pcmpgtd %xmm0, %xmm4
921; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
922; SSE41-NEXT:    pcmpeqd %xmm0, %xmm5
923; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
924; SSE41-NEXT:    pand %xmm6, %xmm0
925; SSE41-NEXT:    por %xmm4, %xmm0
926; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
927; SSE41-NEXT:    movapd %xmm2, %xmm0
928; SSE41-NEXT:    movapd %xmm3, %xmm1
929; SSE41-NEXT:    retq
930;
931; SSE42-LABEL: min_lt_v4i64:
932; SSE42:       # %bb.0:
933; SSE42-NEXT:    movdqa %xmm0, %xmm4
934; SSE42-NEXT:    movdqa %xmm2, %xmm0
935; SSE42-NEXT:    pcmpgtq %xmm4, %xmm0
936; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
937; SSE42-NEXT:    movdqa %xmm3, %xmm0
938; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
939; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
940; SSE42-NEXT:    movapd %xmm2, %xmm0
941; SSE42-NEXT:    movapd %xmm3, %xmm1
942; SSE42-NEXT:    retq
943;
944; AVX1-LABEL: min_lt_v4i64:
945; AVX1:       # %bb.0:
946; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
947; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
948; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
949; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm3
950; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
951; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
952; AVX1-NEXT:    retq
953;
954; AVX2-LABEL: min_lt_v4i64:
955; AVX2:       # %bb.0:
956; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
957; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
958; AVX2-NEXT:    retq
959;
960; AVX512-LABEL: min_lt_v4i64:
961; AVX512:       # %bb.0:
962; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
963; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
964; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
965; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
966; AVX512-NEXT:    retq
967  %1 = icmp slt <4 x i64> %a, %b
968  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
969  ret <4 x i64> %2
970}
971
972define <4 x i32> @min_lt_v4i32(<4 x i32> %a, <4 x i32> %b) {
973; SSE2-LABEL: min_lt_v4i32:
974; SSE2:       # %bb.0:
975; SSE2-NEXT:    movdqa %xmm1, %xmm2
976; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
977; SSE2-NEXT:    pand %xmm2, %xmm0
978; SSE2-NEXT:    pandn %xmm1, %xmm2
979; SSE2-NEXT:    por %xmm2, %xmm0
980; SSE2-NEXT:    retq
981;
982; SSE41-LABEL: min_lt_v4i32:
983; SSE41:       # %bb.0:
984; SSE41-NEXT:    pminsd %xmm1, %xmm0
985; SSE41-NEXT:    retq
986;
987; SSE42-LABEL: min_lt_v4i32:
988; SSE42:       # %bb.0:
989; SSE42-NEXT:    pminsd %xmm1, %xmm0
990; SSE42-NEXT:    retq
991;
992; AVX-LABEL: min_lt_v4i32:
993; AVX:       # %bb.0:
994; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
995; AVX-NEXT:    retq
996  %1 = icmp slt <4 x i32> %a, %b
997  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
998  ret <4 x i32> %2
999}
1000
1001define <8 x i32> @min_lt_v8i32(<8 x i32> %a, <8 x i32> %b) {
1002; SSE2-LABEL: min_lt_v8i32:
1003; SSE2:       # %bb.0:
1004; SSE2-NEXT:    movdqa %xmm2, %xmm4
1005; SSE2-NEXT:    pcmpgtd %xmm0, %xmm4
1006; SSE2-NEXT:    pand %xmm4, %xmm0
1007; SSE2-NEXT:    pandn %xmm2, %xmm4
1008; SSE2-NEXT:    por %xmm4, %xmm0
1009; SSE2-NEXT:    movdqa %xmm3, %xmm2
1010; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
1011; SSE2-NEXT:    pand %xmm2, %xmm1
1012; SSE2-NEXT:    pandn %xmm3, %xmm2
1013; SSE2-NEXT:    por %xmm2, %xmm1
1014; SSE2-NEXT:    retq
1015;
1016; SSE41-LABEL: min_lt_v8i32:
1017; SSE41:       # %bb.0:
1018; SSE41-NEXT:    pminsd %xmm2, %xmm0
1019; SSE41-NEXT:    pminsd %xmm3, %xmm1
1020; SSE41-NEXT:    retq
1021;
1022; SSE42-LABEL: min_lt_v8i32:
1023; SSE42:       # %bb.0:
1024; SSE42-NEXT:    pminsd %xmm2, %xmm0
1025; SSE42-NEXT:    pminsd %xmm3, %xmm1
1026; SSE42-NEXT:    retq
1027;
1028; AVX1-LABEL: min_lt_v8i32:
1029; AVX1:       # %bb.0:
1030; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1031; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1032; AVX1-NEXT:    vpminsd %xmm2, %xmm3, %xmm2
1033; AVX1-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1034; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1035; AVX1-NEXT:    retq
1036;
1037; AVX2-LABEL: min_lt_v8i32:
1038; AVX2:       # %bb.0:
1039; AVX2-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1040; AVX2-NEXT:    retq
1041;
1042; AVX512-LABEL: min_lt_v8i32:
1043; AVX512:       # %bb.0:
1044; AVX512-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1045; AVX512-NEXT:    retq
1046  %1 = icmp slt <8 x i32> %a, %b
1047  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1048  ret <8 x i32> %2
1049}
1050
1051define <8 x i16> @min_lt_v8i16(<8 x i16> %a, <8 x i16> %b) {
1052; SSE-LABEL: min_lt_v8i16:
1053; SSE:       # %bb.0:
1054; SSE-NEXT:    pminsw %xmm1, %xmm0
1055; SSE-NEXT:    retq
1056;
1057; AVX-LABEL: min_lt_v8i16:
1058; AVX:       # %bb.0:
1059; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1060; AVX-NEXT:    retq
1061  %1 = icmp slt <8 x i16> %a, %b
1062  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1063  ret <8 x i16> %2
1064}
1065
1066define <16 x i16> @min_lt_v16i16(<16 x i16> %a, <16 x i16> %b) {
1067; SSE-LABEL: min_lt_v16i16:
1068; SSE:       # %bb.0:
1069; SSE-NEXT:    pminsw %xmm2, %xmm0
1070; SSE-NEXT:    pminsw %xmm3, %xmm1
1071; SSE-NEXT:    retq
1072;
1073; AVX1-LABEL: min_lt_v16i16:
1074; AVX1:       # %bb.0:
1075; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1076; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1077; AVX1-NEXT:    vpminsw %xmm2, %xmm3, %xmm2
1078; AVX1-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1079; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1080; AVX1-NEXT:    retq
1081;
1082; AVX2-LABEL: min_lt_v16i16:
1083; AVX2:       # %bb.0:
1084; AVX2-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1085; AVX2-NEXT:    retq
1086;
1087; AVX512-LABEL: min_lt_v16i16:
1088; AVX512:       # %bb.0:
1089; AVX512-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1090; AVX512-NEXT:    retq
1091  %1 = icmp slt <16 x i16> %a, %b
1092  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1093  ret <16 x i16> %2
1094}
1095
1096define <16 x i8> @min_lt_v16i8(<16 x i8> %a, <16 x i8> %b) {
1097; SSE2-LABEL: min_lt_v16i8:
1098; SSE2:       # %bb.0:
1099; SSE2-NEXT:    movdqa %xmm1, %xmm2
1100; SSE2-NEXT:    pcmpgtb %xmm0, %xmm2
1101; SSE2-NEXT:    pand %xmm2, %xmm0
1102; SSE2-NEXT:    pandn %xmm1, %xmm2
1103; SSE2-NEXT:    por %xmm2, %xmm0
1104; SSE2-NEXT:    retq
1105;
1106; SSE41-LABEL: min_lt_v16i8:
1107; SSE41:       # %bb.0:
1108; SSE41-NEXT:    pminsb %xmm1, %xmm0
1109; SSE41-NEXT:    retq
1110;
1111; SSE42-LABEL: min_lt_v16i8:
1112; SSE42:       # %bb.0:
1113; SSE42-NEXT:    pminsb %xmm1, %xmm0
1114; SSE42-NEXT:    retq
1115;
1116; AVX-LABEL: min_lt_v16i8:
1117; AVX:       # %bb.0:
1118; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1119; AVX-NEXT:    retq
1120  %1 = icmp slt <16 x i8> %a, %b
1121  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1122  ret <16 x i8> %2
1123}
1124
1125define <32 x i8> @min_lt_v32i8(<32 x i8> %a, <32 x i8> %b) {
1126; SSE2-LABEL: min_lt_v32i8:
1127; SSE2:       # %bb.0:
1128; SSE2-NEXT:    movdqa %xmm2, %xmm4
1129; SSE2-NEXT:    pcmpgtb %xmm0, %xmm4
1130; SSE2-NEXT:    pand %xmm4, %xmm0
1131; SSE2-NEXT:    pandn %xmm2, %xmm4
1132; SSE2-NEXT:    por %xmm4, %xmm0
1133; SSE2-NEXT:    movdqa %xmm3, %xmm2
1134; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
1135; SSE2-NEXT:    pand %xmm2, %xmm1
1136; SSE2-NEXT:    pandn %xmm3, %xmm2
1137; SSE2-NEXT:    por %xmm2, %xmm1
1138; SSE2-NEXT:    retq
1139;
1140; SSE41-LABEL: min_lt_v32i8:
1141; SSE41:       # %bb.0:
1142; SSE41-NEXT:    pminsb %xmm2, %xmm0
1143; SSE41-NEXT:    pminsb %xmm3, %xmm1
1144; SSE41-NEXT:    retq
1145;
1146; SSE42-LABEL: min_lt_v32i8:
1147; SSE42:       # %bb.0:
1148; SSE42-NEXT:    pminsb %xmm2, %xmm0
1149; SSE42-NEXT:    pminsb %xmm3, %xmm1
1150; SSE42-NEXT:    retq
1151;
1152; AVX1-LABEL: min_lt_v32i8:
1153; AVX1:       # %bb.0:
1154; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1155; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1156; AVX1-NEXT:    vpminsb %xmm2, %xmm3, %xmm2
1157; AVX1-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1158; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1159; AVX1-NEXT:    retq
1160;
1161; AVX2-LABEL: min_lt_v32i8:
1162; AVX2:       # %bb.0:
1163; AVX2-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1164; AVX2-NEXT:    retq
1165;
1166; AVX512-LABEL: min_lt_v32i8:
1167; AVX512:       # %bb.0:
1168; AVX512-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1169; AVX512-NEXT:    retq
1170  %1 = icmp slt <32 x i8> %a, %b
1171  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1172  ret <32 x i8> %2
1173}
1174
1175;
1176; Signed Minimum (LE)
1177;
1178
1179define <2 x i64> @min_le_v2i64(<2 x i64> %a, <2 x i64> %b) {
1180; SSE2-LABEL: min_le_v2i64:
1181; SSE2:       # %bb.0:
1182; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
1183; SSE2-NEXT:    movdqa %xmm0, %xmm3
1184; SSE2-NEXT:    pxor %xmm2, %xmm3
1185; SSE2-NEXT:    pxor %xmm1, %xmm2
1186; SSE2-NEXT:    movdqa %xmm2, %xmm4
1187; SSE2-NEXT:    pcmpgtd %xmm3, %xmm4
1188; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
1189; SSE2-NEXT:    pcmpeqd %xmm3, %xmm2
1190; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
1191; SSE2-NEXT:    pand %xmm5, %xmm2
1192; SSE2-NEXT:    pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
1193; SSE2-NEXT:    por %xmm2, %xmm3
1194; SSE2-NEXT:    pand %xmm3, %xmm0
1195; SSE2-NEXT:    pandn %xmm1, %xmm3
1196; SSE2-NEXT:    por %xmm3, %xmm0
1197; SSE2-NEXT:    retq
1198;
1199; SSE41-LABEL: min_le_v2i64:
1200; SSE41:       # %bb.0:
1201; SSE41-NEXT:    movdqa %xmm0, %xmm2
1202; SSE41-NEXT:    movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
1203; SSE41-NEXT:    movdqa %xmm2, %xmm3
1204; SSE41-NEXT:    pxor %xmm0, %xmm3
1205; SSE41-NEXT:    pxor %xmm1, %xmm0
1206; SSE41-NEXT:    movdqa %xmm0, %xmm4
1207; SSE41-NEXT:    pcmpgtd %xmm3, %xmm4
1208; SSE41-NEXT:    pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
1209; SSE41-NEXT:    pcmpeqd %xmm3, %xmm0
1210; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
1211; SSE41-NEXT:    pand %xmm5, %xmm0
1212; SSE41-NEXT:    por %xmm4, %xmm0
1213; SSE41-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
1214; SSE41-NEXT:    movapd %xmm1, %xmm0
1215; SSE41-NEXT:    retq
1216;
1217; SSE42-LABEL: min_le_v2i64:
1218; SSE42:       # %bb.0:
1219; SSE42-NEXT:    movdqa %xmm0, %xmm2
1220; SSE42-NEXT:    movdqa %xmm1, %xmm0
1221; SSE42-NEXT:    pcmpgtq %xmm2, %xmm0
1222; SSE42-NEXT:    blendvpd %xmm0, %xmm2, %xmm1
1223; SSE42-NEXT:    movapd %xmm1, %xmm0
1224; SSE42-NEXT:    retq
1225;
1226; AVX1-LABEL: min_le_v2i64:
1227; AVX1:       # %bb.0:
1228; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
1229; AVX1-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
1230; AVX1-NEXT:    retq
1231;
1232; AVX2-LABEL: min_le_v2i64:
1233; AVX2:       # %bb.0:
1234; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm2
1235; AVX2-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
1236; AVX2-NEXT:    retq
1237;
1238; AVX512-LABEL: min_le_v2i64:
1239; AVX512:       # %bb.0:
1240; AVX512-NEXT:    # kill: def $xmm1 killed $xmm1 def $zmm1
1241; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
1242; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
1243; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 killed $zmm0
1244; AVX512-NEXT:    vzeroupper
1245; AVX512-NEXT:    retq
1246  %1 = icmp sle <2 x i64> %a, %b
1247  %2 = select <2 x i1> %1, <2 x i64> %a, <2 x i64> %b
1248  ret <2 x i64> %2
1249}
1250
1251define <4 x i64> @min_le_v4i64(<4 x i64> %a, <4 x i64> %b) {
1252; SSE2-LABEL: min_le_v4i64:
1253; SSE2:       # %bb.0:
1254; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
1255; SSE2-NEXT:    movdqa %xmm0, %xmm5
1256; SSE2-NEXT:    pxor %xmm4, %xmm5
1257; SSE2-NEXT:    movdqa %xmm2, %xmm6
1258; SSE2-NEXT:    pxor %xmm4, %xmm6
1259; SSE2-NEXT:    movdqa %xmm6, %xmm7
1260; SSE2-NEXT:    pcmpgtd %xmm5, %xmm7
1261; SSE2-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
1262; SSE2-NEXT:    pcmpeqd %xmm5, %xmm6
1263; SSE2-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
1264; SSE2-NEXT:    pand %xmm8, %xmm5
1265; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm7[1,1,3,3]
1266; SSE2-NEXT:    por %xmm5, %xmm6
1267; SSE2-NEXT:    pand %xmm6, %xmm0
1268; SSE2-NEXT:    pandn %xmm2, %xmm6
1269; SSE2-NEXT:    por %xmm6, %xmm0
1270; SSE2-NEXT:    movdqa %xmm1, %xmm2
1271; SSE2-NEXT:    pxor %xmm4, %xmm2
1272; SSE2-NEXT:    pxor %xmm3, %xmm4
1273; SSE2-NEXT:    movdqa %xmm4, %xmm5
1274; SSE2-NEXT:    pcmpgtd %xmm2, %xmm5
1275; SSE2-NEXT:    pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
1276; SSE2-NEXT:    pcmpeqd %xmm2, %xmm4
1277; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3]
1278; SSE2-NEXT:    pand %xmm6, %xmm2
1279; SSE2-NEXT:    pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
1280; SSE2-NEXT:    por %xmm2, %xmm4
1281; SSE2-NEXT:    pand %xmm4, %xmm1
1282; SSE2-NEXT:    pandn %xmm3, %xmm4
1283; SSE2-NEXT:    por %xmm4, %xmm1
1284; SSE2-NEXT:    retq
1285;
1286; SSE41-LABEL: min_le_v4i64:
1287; SSE41:       # %bb.0:
1288; SSE41-NEXT:    movdqa %xmm0, %xmm4
1289; SSE41-NEXT:    movdqa {{.*#+}} xmm5 = [2147483648,2147483648]
1290; SSE41-NEXT:    pxor %xmm5, %xmm0
1291; SSE41-NEXT:    movdqa %xmm2, %xmm6
1292; SSE41-NEXT:    pxor %xmm5, %xmm6
1293; SSE41-NEXT:    movdqa %xmm6, %xmm7
1294; SSE41-NEXT:    pcmpgtd %xmm0, %xmm7
1295; SSE41-NEXT:    pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
1296; SSE41-NEXT:    pcmpeqd %xmm0, %xmm6
1297; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
1298; SSE41-NEXT:    pand %xmm8, %xmm0
1299; SSE41-NEXT:    por %xmm7, %xmm0
1300; SSE41-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
1301; SSE41-NEXT:    movdqa %xmm1, %xmm0
1302; SSE41-NEXT:    pxor %xmm5, %xmm0
1303; SSE41-NEXT:    pxor %xmm3, %xmm5
1304; SSE41-NEXT:    movdqa %xmm5, %xmm4
1305; SSE41-NEXT:    pcmpgtd %xmm0, %xmm4
1306; SSE41-NEXT:    pshufd {{.*#+}} xmm6 = xmm4[0,0,2,2]
1307; SSE41-NEXT:    pcmpeqd %xmm0, %xmm5
1308; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
1309; SSE41-NEXT:    pand %xmm6, %xmm0
1310; SSE41-NEXT:    por %xmm4, %xmm0
1311; SSE41-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
1312; SSE41-NEXT:    movapd %xmm2, %xmm0
1313; SSE41-NEXT:    movapd %xmm3, %xmm1
1314; SSE41-NEXT:    retq
1315;
1316; SSE42-LABEL: min_le_v4i64:
1317; SSE42:       # %bb.0:
1318; SSE42-NEXT:    movdqa %xmm0, %xmm4
1319; SSE42-NEXT:    movdqa %xmm2, %xmm0
1320; SSE42-NEXT:    pcmpgtq %xmm4, %xmm0
1321; SSE42-NEXT:    blendvpd %xmm0, %xmm4, %xmm2
1322; SSE42-NEXT:    movdqa %xmm3, %xmm0
1323; SSE42-NEXT:    pcmpgtq %xmm1, %xmm0
1324; SSE42-NEXT:    blendvpd %xmm0, %xmm1, %xmm3
1325; SSE42-NEXT:    movapd %xmm2, %xmm0
1326; SSE42-NEXT:    movapd %xmm3, %xmm1
1327; SSE42-NEXT:    retq
1328;
1329; AVX1-LABEL: min_le_v4i64:
1330; AVX1:       # %bb.0:
1331; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm2
1332; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm3
1333; AVX1-NEXT:    vpcmpgtq %xmm2, %xmm3, %xmm2
1334; AVX1-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm3
1335; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
1336; AVX1-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1337; AVX1-NEXT:    retq
1338;
1339; AVX2-LABEL: min_le_v4i64:
1340; AVX2:       # %bb.0:
1341; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
1342; AVX2-NEXT:    vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
1343; AVX2-NEXT:    retq
1344;
1345; AVX512-LABEL: min_le_v4i64:
1346; AVX512:       # %bb.0:
1347; AVX512-NEXT:    # kill: def $ymm1 killed $ymm1 def $zmm1
1348; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
1349; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
1350; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
1351; AVX512-NEXT:    retq
1352  %1 = icmp sle <4 x i64> %a, %b
1353  %2 = select <4 x i1> %1, <4 x i64> %a, <4 x i64> %b
1354  ret <4 x i64> %2
1355}
1356
1357define <4 x i32> @min_le_v4i32(<4 x i32> %a, <4 x i32> %b) {
1358; SSE2-LABEL: min_le_v4i32:
1359; SSE2:       # %bb.0:
1360; SSE2-NEXT:    movdqa %xmm1, %xmm2
1361; SSE2-NEXT:    pcmpgtd %xmm0, %xmm2
1362; SSE2-NEXT:    pand %xmm2, %xmm0
1363; SSE2-NEXT:    pandn %xmm1, %xmm2
1364; SSE2-NEXT:    por %xmm2, %xmm0
1365; SSE2-NEXT:    retq
1366;
1367; SSE41-LABEL: min_le_v4i32:
1368; SSE41:       # %bb.0:
1369; SSE41-NEXT:    pminsd %xmm1, %xmm0
1370; SSE41-NEXT:    retq
1371;
1372; SSE42-LABEL: min_le_v4i32:
1373; SSE42:       # %bb.0:
1374; SSE42-NEXT:    pminsd %xmm1, %xmm0
1375; SSE42-NEXT:    retq
1376;
1377; AVX-LABEL: min_le_v4i32:
1378; AVX:       # %bb.0:
1379; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1380; AVX-NEXT:    retq
1381  %1 = icmp sle <4 x i32> %a, %b
1382  %2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
1383  ret <4 x i32> %2
1384}
1385
1386define <8 x i32> @min_le_v8i32(<8 x i32> %a, <8 x i32> %b) {
1387; SSE2-LABEL: min_le_v8i32:
1388; SSE2:       # %bb.0:
1389; SSE2-NEXT:    movdqa %xmm2, %xmm4
1390; SSE2-NEXT:    pcmpgtd %xmm0, %xmm4
1391; SSE2-NEXT:    pand %xmm4, %xmm0
1392; SSE2-NEXT:    pandn %xmm2, %xmm4
1393; SSE2-NEXT:    por %xmm4, %xmm0
1394; SSE2-NEXT:    movdqa %xmm3, %xmm2
1395; SSE2-NEXT:    pcmpgtd %xmm1, %xmm2
1396; SSE2-NEXT:    pand %xmm2, %xmm1
1397; SSE2-NEXT:    pandn %xmm3, %xmm2
1398; SSE2-NEXT:    por %xmm2, %xmm1
1399; SSE2-NEXT:    retq
1400;
1401; SSE41-LABEL: min_le_v8i32:
1402; SSE41:       # %bb.0:
1403; SSE41-NEXT:    pminsd %xmm2, %xmm0
1404; SSE41-NEXT:    pminsd %xmm3, %xmm1
1405; SSE41-NEXT:    retq
1406;
1407; SSE42-LABEL: min_le_v8i32:
1408; SSE42:       # %bb.0:
1409; SSE42-NEXT:    pminsd %xmm2, %xmm0
1410; SSE42-NEXT:    pminsd %xmm3, %xmm1
1411; SSE42-NEXT:    retq
1412;
1413; AVX1-LABEL: min_le_v8i32:
1414; AVX1:       # %bb.0:
1415; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1416; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1417; AVX1-NEXT:    vpminsd %xmm2, %xmm3, %xmm2
1418; AVX1-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
1419; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1420; AVX1-NEXT:    retq
1421;
1422; AVX2-LABEL: min_le_v8i32:
1423; AVX2:       # %bb.0:
1424; AVX2-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1425; AVX2-NEXT:    retq
1426;
1427; AVX512-LABEL: min_le_v8i32:
1428; AVX512:       # %bb.0:
1429; AVX512-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
1430; AVX512-NEXT:    retq
1431  %1 = icmp sle <8 x i32> %a, %b
1432  %2 = select <8 x i1> %1, <8 x i32> %a, <8 x i32> %b
1433  ret <8 x i32> %2
1434}
1435
1436define <8 x i16> @min_le_v8i16(<8 x i16> %a, <8 x i16> %b) {
1437; SSE-LABEL: min_le_v8i16:
1438; SSE:       # %bb.0:
1439; SSE-NEXT:    pminsw %xmm1, %xmm0
1440; SSE-NEXT:    retq
1441;
1442; AVX-LABEL: min_le_v8i16:
1443; AVX:       # %bb.0:
1444; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1445; AVX-NEXT:    retq
1446  %1 = icmp sle <8 x i16> %a, %b
1447  %2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
1448  ret <8 x i16> %2
1449}
1450
1451define <16 x i16> @min_le_v16i16(<16 x i16> %a, <16 x i16> %b) {
1452; SSE-LABEL: min_le_v16i16:
1453; SSE:       # %bb.0:
1454; SSE-NEXT:    pminsw %xmm2, %xmm0
1455; SSE-NEXT:    pminsw %xmm3, %xmm1
1456; SSE-NEXT:    retq
1457;
1458; AVX1-LABEL: min_le_v16i16:
1459; AVX1:       # %bb.0:
1460; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1461; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1462; AVX1-NEXT:    vpminsw %xmm2, %xmm3, %xmm2
1463; AVX1-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
1464; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1465; AVX1-NEXT:    retq
1466;
1467; AVX2-LABEL: min_le_v16i16:
1468; AVX2:       # %bb.0:
1469; AVX2-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1470; AVX2-NEXT:    retq
1471;
1472; AVX512-LABEL: min_le_v16i16:
1473; AVX512:       # %bb.0:
1474; AVX512-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
1475; AVX512-NEXT:    retq
1476  %1 = icmp sle <16 x i16> %a, %b
1477  %2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
1478  ret <16 x i16> %2
1479}
1480
1481define <16 x i8> @min_le_v16i8(<16 x i8> %a, <16 x i8> %b) {
1482; SSE2-LABEL: min_le_v16i8:
1483; SSE2:       # %bb.0:
1484; SSE2-NEXT:    movdqa %xmm1, %xmm2
1485; SSE2-NEXT:    pcmpgtb %xmm0, %xmm2
1486; SSE2-NEXT:    pand %xmm2, %xmm0
1487; SSE2-NEXT:    pandn %xmm1, %xmm2
1488; SSE2-NEXT:    por %xmm2, %xmm0
1489; SSE2-NEXT:    retq
1490;
1491; SSE41-LABEL: min_le_v16i8:
1492; SSE41:       # %bb.0:
1493; SSE41-NEXT:    pminsb %xmm1, %xmm0
1494; SSE41-NEXT:    retq
1495;
1496; SSE42-LABEL: min_le_v16i8:
1497; SSE42:       # %bb.0:
1498; SSE42-NEXT:    pminsb %xmm1, %xmm0
1499; SSE42-NEXT:    retq
1500;
1501; AVX-LABEL: min_le_v16i8:
1502; AVX:       # %bb.0:
1503; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1504; AVX-NEXT:    retq
1505  %1 = icmp sle <16 x i8> %a, %b
1506  %2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
1507  ret <16 x i8> %2
1508}
1509
1510define <32 x i8> @min_le_v32i8(<32 x i8> %a, <32 x i8> %b) {
1511; SSE2-LABEL: min_le_v32i8:
1512; SSE2:       # %bb.0:
1513; SSE2-NEXT:    movdqa %xmm2, %xmm4
1514; SSE2-NEXT:    pcmpgtb %xmm0, %xmm4
1515; SSE2-NEXT:    pand %xmm4, %xmm0
1516; SSE2-NEXT:    pandn %xmm2, %xmm4
1517; SSE2-NEXT:    por %xmm4, %xmm0
1518; SSE2-NEXT:    movdqa %xmm3, %xmm2
1519; SSE2-NEXT:    pcmpgtb %xmm1, %xmm2
1520; SSE2-NEXT:    pand %xmm2, %xmm1
1521; SSE2-NEXT:    pandn %xmm3, %xmm2
1522; SSE2-NEXT:    por %xmm2, %xmm1
1523; SSE2-NEXT:    retq
1524;
1525; SSE41-LABEL: min_le_v32i8:
1526; SSE41:       # %bb.0:
1527; SSE41-NEXT:    pminsb %xmm2, %xmm0
1528; SSE41-NEXT:    pminsb %xmm3, %xmm1
1529; SSE41-NEXT:    retq
1530;
1531; SSE42-LABEL: min_le_v32i8:
1532; SSE42:       # %bb.0:
1533; SSE42-NEXT:    pminsb %xmm2, %xmm0
1534; SSE42-NEXT:    pminsb %xmm3, %xmm1
1535; SSE42-NEXT:    retq
1536;
1537; AVX1-LABEL: min_le_v32i8:
1538; AVX1:       # %bb.0:
1539; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
1540; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm3
1541; AVX1-NEXT:    vpminsb %xmm2, %xmm3, %xmm2
1542; AVX1-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
1543; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
1544; AVX1-NEXT:    retq
1545;
1546; AVX2-LABEL: min_le_v32i8:
1547; AVX2:       # %bb.0:
1548; AVX2-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1549; AVX2-NEXT:    retq
1550;
1551; AVX512-LABEL: min_le_v32i8:
1552; AVX512:       # %bb.0:
1553; AVX512-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
1554; AVX512-NEXT:    retq
1555  %1 = icmp sle <32 x i8> %a, %b
1556  %2 = select <32 x i1> %1, <32 x i8> %a, <32 x i8> %b
1557  ret <32 x i8> %2
1558}
1559
1560;
1561; Constant Folding
1562;
1563
1564define <2 x i64> @max_gt_v2i64c() {
1565; SSE-LABEL: max_gt_v2i64c:
1566; SSE:       # %bb.0:
1567; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1568; SSE-NEXT:    retq
1569;
1570; AVX-LABEL: max_gt_v2i64c:
1571; AVX:       # %bb.0:
1572; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1573; AVX-NEXT:    retq
1574  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1575  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1576  %3 = icmp sgt <2 x i64> %1, %2
1577  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1578  ret <2 x i64> %4
1579}
1580
1581define <4 x i64> @max_gt_v4i64c() {
1582; SSE-LABEL: max_gt_v4i64c:
1583; SSE:       # %bb.0:
1584; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,7]
1585; SSE-NEXT:    pcmpeqd %xmm0, %xmm0
1586; SSE-NEXT:    retq
1587;
1588; AVX-LABEL: max_gt_v4i64c:
1589; AVX:       # %bb.0:
1590; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1591; AVX-NEXT:    retq
1592  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1593  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1594  %3 = icmp sgt <4 x i64> %1, %2
1595  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1596  ret <4 x i64> %4
1597}
1598
1599define <4 x i32> @max_gt_v4i32c() {
1600; SSE-LABEL: max_gt_v4i32c:
1601; SSE:       # %bb.0:
1602; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1603; SSE-NEXT:    retq
1604;
1605; AVX-LABEL: max_gt_v4i32c:
1606; AVX:       # %bb.0:
1607; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1608; AVX-NEXT:    retq
1609  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1610  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1611  %3 = icmp sgt <4 x i32> %1, %2
1612  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1613  ret <4 x i32> %4
1614}
1615
1616define <8 x i32> @max_gt_v8i32c() {
1617; SSE-LABEL: max_gt_v8i32c:
1618; SSE:       # %bb.0:
1619; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1620; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,5,5,7]
1621; SSE-NEXT:    retq
1622;
1623; AVX-LABEL: max_gt_v8i32c:
1624; AVX:       # %bb.0:
1625; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1626; AVX-NEXT:    retq
1627  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1628  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1629  %3 = icmp sgt <8 x i32> %1, %2
1630  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1631  ret <8 x i32> %4
1632}
1633
1634define <8 x i16> @max_gt_v8i16c() {
1635; SSE-LABEL: max_gt_v8i16c:
1636; SSE:       # %bb.0:
1637; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1638; SSE-NEXT:    retq
1639;
1640; AVX-LABEL: max_gt_v8i16c:
1641; AVX:       # %bb.0:
1642; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1643; AVX-NEXT:    retq
1644  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1645  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1646  %3 = icmp sgt <8 x i16> %1, %2
1647  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1648  ret <8 x i16> %4
1649}
1650
1651define <16 x i16> @max_gt_v16i16c() {
1652; SSE-LABEL: max_gt_v16i16c:
1653; SSE:       # %bb.0:
1654; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1655; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1656; SSE-NEXT:    retq
1657;
1658; AVX-LABEL: max_gt_v16i16c:
1659; AVX:       # %bb.0:
1660; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1661; AVX-NEXT:    retq
1662  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1663  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1664  %3 = icmp sgt <16 x i16> %1, %2
1665  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1666  ret <16 x i16> %4
1667}
1668
1669define <16 x i8> @max_gt_v16i8c() {
1670; SSE-LABEL: max_gt_v16i8c:
1671; SSE:       # %bb.0:
1672; SSE-NEXT:    movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1673; SSE-NEXT:    retq
1674;
1675; AVX-LABEL: max_gt_v16i8c:
1676; AVX:       # %bb.0:
1677; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1678; AVX-NEXT:    retq
1679  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1680  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1681  %3 = icmp sgt <16 x i8> %1, %2
1682  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1683  ret <16 x i8> %4
1684}
1685
1686define <2 x i64> @max_ge_v2i64c() {
1687; SSE-LABEL: max_ge_v2i64c:
1688; SSE:       # %bb.0:
1689; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551615,7]
1690; SSE-NEXT:    retq
1691;
1692; AVX-LABEL: max_ge_v2i64c:
1693; AVX:       # %bb.0:
1694; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551615,7]
1695; AVX-NEXT:    retq
1696  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1697  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1698  %3 = icmp sge <2 x i64> %1, %2
1699  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1700  ret <2 x i64> %4
1701}
1702
1703define <4 x i64> @max_ge_v4i64c() {
1704; SSE-LABEL: max_ge_v4i64c:
1705; SSE:       # %bb.0:
1706; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,7]
1707; SSE-NEXT:    pcmpeqd %xmm0, %xmm0
1708; SSE-NEXT:    retq
1709;
1710; AVX-LABEL: max_ge_v4i64c:
1711; AVX:       # %bb.0:
1712; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551615,18446744073709551615,7,7]
1713; AVX-NEXT:    retq
1714  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1715  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1716  %3 = icmp sge <4 x i64> %1, %2
1717  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1718  ret <4 x i64> %4
1719}
1720
1721define <4 x i32> @max_ge_v4i32c() {
1722; SSE-LABEL: max_ge_v4i32c:
1723; SSE:       # %bb.0:
1724; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1725; SSE-NEXT:    retq
1726;
1727; AVX-LABEL: max_ge_v4i32c:
1728; AVX:       # %bb.0:
1729; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,7,7]
1730; AVX-NEXT:    retq
1731  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1732  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1733  %3 = icmp sge <4 x i32> %1, %2
1734  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1735  ret <4 x i32> %4
1736}
1737
1738define <8 x i32> @max_ge_v8i32c() {
1739; SSE-LABEL: max_ge_v8i32c:
1740; SSE:       # %bb.0:
1741; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967295,4294967293,4294967293,4294967295]
1742; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,5,5,7]
1743; SSE-NEXT:    retq
1744;
1745; AVX-LABEL: max_ge_v8i32c:
1746; AVX:       # %bb.0:
1747; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967295,4294967293,4294967293,4294967295,7,5,5,7]
1748; AVX-NEXT:    retq
1749  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1750  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1751  %3 = icmp sge <8 x i32> %1, %2
1752  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1753  ret <8 x i32> %4
1754}
1755
1756define <8 x i16> @max_ge_v8i16c() {
1757; SSE-LABEL: max_ge_v8i16c:
1758; SSE:       # %bb.0:
1759; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1760; SSE-NEXT:    retq
1761;
1762; AVX-LABEL: max_ge_v8i16c:
1763; AVX:       # %bb.0:
1764; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65535,65533,65533,65535,7,5,5,7]
1765; AVX-NEXT:    retq
1766  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1767  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1768  %3 = icmp sge <8 x i16> %1, %2
1769  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1770  ret <8 x i16> %4
1771}
1772
1773define <16 x i16> @max_ge_v16i16c() {
1774; SSE-LABEL: max_ge_v16i16c:
1775; SSE:       # %bb.0:
1776; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65535,65534,65533,65532,65533,65534,65535,0]
1777; SSE-NEXT:    movaps {{.*#+}} xmm1 = [7,6,5,4,5,6,7,8]
1778; SSE-NEXT:    retq
1779;
1780; AVX-LABEL: max_ge_v16i16c:
1781; AVX:       # %bb.0:
1782; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65535,65534,65533,65532,65533,65534,65535,0,7,6,5,4,5,6,7,8]
1783; AVX-NEXT:    retq
1784  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1785  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1786  %3 = icmp sge <16 x i16> %1, %2
1787  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1788  ret <16 x i16> %4
1789}
1790
1791define <16 x i8> @max_ge_v16i8c() {
1792; SSE-LABEL: max_ge_v16i8c:
1793; SSE:       # %bb.0:
1794; SSE-NEXT:    movaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1795; SSE-NEXT:    retq
1796;
1797; AVX-LABEL: max_ge_v16i8c:
1798; AVX:       # %bb.0:
1799; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [255,254,253,252,253,254,255,0,7,6,5,4,5,6,7,8]
1800; AVX-NEXT:    retq
1801  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1802  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1803  %3 = icmp sge <16 x i8> %1, %2
1804  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1805  ret <16 x i8> %4
1806}
1807
1808define <2 x i64> @min_lt_v2i64c() {
1809; SSE-LABEL: min_lt_v2i64c:
1810; SSE:       # %bb.0:
1811; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1812; SSE-NEXT:    retq
1813;
1814; AVX-LABEL: min_lt_v2i64c:
1815; AVX:       # %bb.0:
1816; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1817; AVX-NEXT:    retq
1818  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1819  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1820  %3 = icmp slt <2 x i64> %1, %2
1821  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1822  ret <2 x i64> %4
1823}
1824
1825define <4 x i64> @min_lt_v4i64c() {
1826; SSE-LABEL: min_lt_v4i64c:
1827; SSE:       # %bb.0:
1828; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1829; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,1]
1830; SSE-NEXT:    retq
1831;
1832; AVX-LABEL: min_lt_v4i64c:
1833; AVX:       # %bb.0:
1834; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1835; AVX-NEXT:    retq
1836  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1837  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1838  %3 = icmp slt <4 x i64> %1, %2
1839  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1840  ret <4 x i64> %4
1841}
1842
1843define <4 x i32> @min_lt_v4i32c() {
1844; SSE-LABEL: min_lt_v4i32c:
1845; SSE:       # %bb.0:
1846; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1847; SSE-NEXT:    retq
1848;
1849; AVX-LABEL: min_lt_v4i32c:
1850; AVX:       # %bb.0:
1851; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1852; AVX-NEXT:    retq
1853  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1854  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1855  %3 = icmp slt <4 x i32> %1, %2
1856  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1857  ret <4 x i32> %4
1858}
1859
1860define <8 x i32> @min_lt_v8i32c() {
1861; SSE-LABEL: min_lt_v8i32c:
1862; SSE:       # %bb.0:
1863; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
1864; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,3,3,1]
1865; SSE-NEXT:    retq
1866;
1867; AVX-LABEL: min_lt_v8i32c:
1868; AVX:       # %bb.0:
1869; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
1870; AVX-NEXT:    retq
1871  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1872  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1873  %3 = icmp slt <8 x i32> %1, %2
1874  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1875  ret <8 x i32> %4
1876}
1877
1878define <8 x i16> @min_lt_v8i16c() {
1879; SSE-LABEL: min_lt_v8i16c:
1880; SSE:       # %bb.0:
1881; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1882; SSE-NEXT:    retq
1883;
1884; AVX-LABEL: min_lt_v8i16c:
1885; AVX:       # %bb.0:
1886; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
1887; AVX-NEXT:    retq
1888  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
1889  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
1890  %3 = icmp slt <8 x i16> %1, %2
1891  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
1892  ret <8 x i16> %4
1893}
1894
1895define <16 x i16> @min_lt_v16i16c() {
1896; SSE-LABEL: min_lt_v16i16c:
1897; SSE:       # %bb.0:
1898; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
1899; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
1900; SSE-NEXT:    retq
1901;
1902; AVX-LABEL: min_lt_v16i16c:
1903; AVX:       # %bb.0:
1904; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
1905; AVX-NEXT:    retq
1906  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
1907  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
1908  %3 = icmp slt <16 x i16> %1, %2
1909  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
1910  ret <16 x i16> %4
1911}
1912
1913define <16 x i8> @min_lt_v16i8c() {
1914; SSE-LABEL: min_lt_v16i8c:
1915; SSE:       # %bb.0:
1916; SSE-NEXT:    movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1917; SSE-NEXT:    retq
1918;
1919; AVX-LABEL: min_lt_v16i8c:
1920; AVX:       # %bb.0:
1921; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
1922; AVX-NEXT:    retq
1923  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
1924  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
1925  %3 = icmp slt <16 x i8> %1, %2
1926  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
1927  ret <16 x i8> %4
1928}
1929
1930define <2 x i64> @min_le_v2i64c() {
1931; SSE-LABEL: min_le_v2i64c:
1932; SSE:       # %bb.0:
1933; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,1]
1934; SSE-NEXT:    retq
1935;
1936; AVX-LABEL: min_le_v2i64c:
1937; AVX:       # %bb.0:
1938; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [18446744073709551609,1]
1939; AVX-NEXT:    retq
1940  %1 = insertelement <2 x i64> <i64 -7, i64 7>, i64 -7, i32 0
1941  %2 = insertelement <2 x i64> <i64 -1, i64 1>, i64 -1, i32 0
1942  %3 = icmp sle <2 x i64> %1, %2
1943  %4 = select <2 x i1> %3, <2 x i64> %1, <2 x i64> %2
1944  ret <2 x i64> %4
1945}
1946
1947define <4 x i64> @min_le_v4i64c() {
1948; SSE-LABEL: min_le_v4i64c:
1949; SSE:       # %bb.0:
1950; SSE-NEXT:    movaps {{.*#+}} xmm0 = [18446744073709551609,18446744073709551609]
1951; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,1]
1952; SSE-NEXT:    retq
1953;
1954; AVX-LABEL: min_le_v4i64c:
1955; AVX:       # %bb.0:
1956; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [18446744073709551609,18446744073709551609,1,1]
1957; AVX-NEXT:    retq
1958  %1 = insertelement <4 x i64> <i64 -7, i64 -1, i64 1, i64 7>, i64 -7, i32 0
1959  %2 = insertelement <4 x i64> <i64 -1, i64 -7, i64 7, i64 1>, i64 -1, i32 0
1960  %3 = icmp sle <4 x i64> %1, %2
1961  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
1962  ret <4 x i64> %4
1963}
1964
1965define <4 x i32> @min_le_v4i32c() {
1966; SSE-LABEL: min_le_v4i32c:
1967; SSE:       # %bb.0:
1968; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1969; SSE-NEXT:    retq
1970;
1971; AVX-LABEL: min_le_v4i32c:
1972; AVX:       # %bb.0:
1973; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967289,4294967289,1,1]
1974; AVX-NEXT:    retq
1975  %1 = insertelement <4 x i32> <i32 -7, i32 -1, i32 1, i32 7>, i32 -7, i32 0
1976  %2 = insertelement <4 x i32> <i32 -1, i32 -7, i32 7, i32 1>, i32 -1, i32 0
1977  %3 = icmp sle <4 x i32> %1, %2
1978  %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2
1979  ret <4 x i32> %4
1980}
1981
1982define <8 x i32> @min_le_v8i32c() {
1983; SSE-LABEL: min_le_v8i32c:
1984; SSE:       # %bb.0:
1985; SSE-NEXT:    movaps {{.*#+}} xmm0 = [4294967289,4294967291,4294967291,4294967289]
1986; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,3,3,1]
1987; SSE-NEXT:    retq
1988;
1989; AVX-LABEL: min_le_v8i32c:
1990; AVX:       # %bb.0:
1991; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [4294967289,4294967291,4294967291,4294967289,1,3,3,1]
1992; AVX-NEXT:    retq
1993  %1 = insertelement <8 x i32> <i32 -7, i32 -5, i32 -3, i32 -1, i32 1, i32 3, i32 5, i32 7>, i32 -7, i32 0
1994  %2 = insertelement <8 x i32> <i32 -1, i32 -3, i32 -5, i32 -7, i32 7, i32 5, i32 3, i32 1>, i32 -1, i32 0
1995  %3 = icmp sle <8 x i32> %1, %2
1996  %4 = select <8 x i1> %3, <8 x i32> %1, <8 x i32> %2
1997  ret <8 x i32> %4
1998}
1999
2000define <8 x i16> @min_le_v8i16c() {
2001; SSE-LABEL: min_le_v8i16c:
2002; SSE:       # %bb.0:
2003; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
2004; SSE-NEXT:    retq
2005;
2006; AVX-LABEL: min_le_v8i16c:
2007; AVX:       # %bb.0:
2008; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [65529,65531,65531,65529,1,3,3,1]
2009; AVX-NEXT:    retq
2010  %1 = insertelement <8 x i16> <i16 -7, i16 -5, i16 -3, i16 -1, i16 1, i16 3, i16 5, i16 7>, i16 -7, i32 0
2011  %2 = insertelement <8 x i16> <i16 -1, i16 -3, i16 -5, i16 -7, i16 7, i16 5, i16 3, i16 1>, i16 -1, i32 0
2012  %3 = icmp sle <8 x i16> %1, %2
2013  %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
2014  ret <8 x i16> %4
2015}
2016
2017define <16 x i16> @min_le_v16i16c() {
2018; SSE-LABEL: min_le_v16i16c:
2019; SSE:       # %bb.0:
2020; SSE-NEXT:    movaps {{.*#+}} xmm0 = [65529,65530,65531,65532,65531,65530,65529,0]
2021; SSE-NEXT:    movaps {{.*#+}} xmm1 = [1,2,3,4,3,2,1,0]
2022; SSE-NEXT:    retq
2023;
2024; AVX-LABEL: min_le_v16i16c:
2025; AVX:       # %bb.0:
2026; AVX-NEXT:    vmovaps {{.*#+}} ymm0 = [65529,65530,65531,65532,65531,65530,65529,0,1,2,3,4,3,2,1,0]
2027; AVX-NEXT:    retq
2028  %1 = insertelement <16 x i16> <i16 -7, i16 -6, i16 -5, i16 -4, i16 -3, i16 -2, i16 -1, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, i16 -7, i32 0
2029  %2 = insertelement <16 x i16> <i16 -1, i16 -2, i16 -3, i16 -4, i16 -5, i16 -6, i16 -7, i16 0, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 -1, i32 0
2030  %3 = icmp sle <16 x i16> %1, %2
2031  %4 = select <16 x i1> %3, <16 x i16> %1, <16 x i16> %2
2032  ret <16 x i16> %4
2033}
2034
2035define <16 x i8> @min_le_v16i8c() {
2036; SSE-LABEL: min_le_v16i8c:
2037; SSE:       # %bb.0:
2038; SSE-NEXT:    movaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2039; SSE-NEXT:    retq
2040;
2041; AVX-LABEL: min_le_v16i8c:
2042; AVX:       # %bb.0:
2043; AVX-NEXT:    vmovaps {{.*#+}} xmm0 = [249,250,251,252,251,250,249,0,1,2,3,4,3,2,1,0]
2044; AVX-NEXT:    retq
2045  %1 = insertelement <16 x i8> <i8 -7, i8 -6, i8 -5, i8 -4, i8 -3, i8 -2, i8 -1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, i8 -7, i32 0
2046  %2 = insertelement <16 x i8> <i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 0, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, i8 -1, i32 0
2047  %3 = icmp sle <16 x i8> %1, %2
2048  %4 = select <16 x i1> %3, <16 x i8> %1, <16 x i8> %2
2049  ret <16 x i8> %4
2050}
2051