1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
3
4; These are actually tests of ValueTracking, and so may have test coverage in InstCombine or other
5; IR opt passes, but ValueTracking also affects the backend via SelectionDAGBuilder::visitSelect().
6
7define <4 x i32> @smin_vec1(<4 x i32> %x) {
8; CHECK-LABEL: smin_vec1:
9; CHECK:       # BB#0:
10; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
11; CHECK-NEXT:    vpxor %xmm1, %xmm0, %xmm0
12; CHECK-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
13; CHECK-NEXT:    retq
14;
15  %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
16  %cmp = icmp sgt <4 x i32> %x, zeroinitializer
17  %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
18  ret <4 x i32> %sel
19}
20
21define <4 x i32> @smin_vec2(<4 x i32> %x) {
22; CHECK-LABEL: smin_vec2:
23; CHECK:       # BB#0:
24; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
25; CHECK-NEXT:    vpxor %xmm1, %xmm0, %xmm0
26; CHECK-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
27; CHECK-NEXT:    retq
28;
29  %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
30  %cmp = icmp slt <4 x i32> %x, zeroinitializer
31  %sel = select <4 x i1> %cmp, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %not_x
32  ret <4 x i32> %sel
33}
34
35; Z = X -nsw Y
36; (X >s Y) ? 0 : Z ==> (Z >s 0) ? 0 : Z ==> SMIN(Z, 0)
37define <4 x i32> @smin_vec3(<4 x i32> %x, <4 x i32> %y) {
38; CHECK-LABEL: smin_vec3:
39; CHECK:       # BB#0:
40; CHECK-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
41; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
42; CHECK-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
43; CHECK-NEXT:    retq
44;
45  %sub = sub nsw <4 x i32> %x, %y
46  %cmp = icmp sgt <4 x i32> %x, %y
47  %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub
48  ret <4 x i32> %sel
49}
50
51; Z = X -nsw Y
52; (X <s Y) ? Z : 0 ==> (Z <s 0) ? Z : 0 ==> SMIN(Z, 0)
53define <4 x i32> @smin_vec4(<4 x i32> %x, <4 x i32> %y) {
54; CHECK-LABEL: smin_vec4:
55; CHECK:       # BB#0:
56; CHECK-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
57; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
58; CHECK-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
59; CHECK-NEXT:    retq
60;
61  %sub = sub nsw <4 x i32> %x, %y
62  %cmp = icmp slt <4 x i32> %x, %y
63  %sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer
64  ret <4 x i32> %sel
65}
66
67define <4 x i32> @smax_vec1(<4 x i32> %x) {
68; CHECK-LABEL: smax_vec1:
69; CHECK:       # BB#0:
70; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
71; CHECK-NEXT:    vpxor %xmm1, %xmm0, %xmm0
72; CHECK-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
73; CHECK-NEXT:    retq
74;
75  %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
76  %cmp = icmp slt <4 x i32> %x, zeroinitializer
77  %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
78  ret <4 x i32> %sel
79}
80
81define <4 x i32> @smax_vec2(<4 x i32> %x) {
82; CHECK-LABEL: smax_vec2:
83; CHECK:       # BB#0:
84; CHECK-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
85; CHECK-NEXT:    vpxor %xmm1, %xmm0, %xmm0
86; CHECK-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
87; CHECK-NEXT:    retq
88;
89  %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
90  %cmp = icmp sgt <4 x i32> %x, zeroinitializer
91  %sel = select <4 x i1> %cmp, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %not_x
92  ret <4 x i32> %sel
93}
94
95; Z = X -nsw Y
96; (X <s Y) ? 0 : Z ==> (Z <s 0) ? 0 : Z ==> SMAX(Z, 0)
97define <4 x i32> @smax_vec3(<4 x i32> %x, <4 x i32> %y) {
98; CHECK-LABEL: smax_vec3:
99; CHECK:       # BB#0:
100; CHECK-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
101; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
102; CHECK-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
103; CHECK-NEXT:    retq
104;
105  %sub = sub nsw <4 x i32> %x, %y
106  %cmp = icmp slt <4 x i32> %x, %y
107  %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub
108  ret <4 x i32> %sel
109}
110
111; Z = X -nsw Y
112; (X >s Y) ? Z : 0 ==> (Z >s 0) ? Z : 0 ==> SMAX(Z, 0)
113define <4 x i32> @smax_vec4(<4 x i32> %x, <4 x i32> %y) {
114; CHECK-LABEL: smax_vec4:
115; CHECK:       # BB#0:
116; CHECK-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
117; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
118; CHECK-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
119; CHECK-NEXT:    retq
120;
121  %sub = sub nsw <4 x i32> %x, %y
122  %cmp = icmp sgt <4 x i32> %x, %y
123  %sel = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> zeroinitializer
124  ret <4 x i32> %sel
125}
126
127define <4 x i32> @umax_vec1(<4 x i32> %x) {
128; CHECK-LABEL: umax_vec1:
129; CHECK:       # BB#0:
130; CHECK-NEXT:    vpmaxud {{.*}}(%rip), %xmm0, %xmm0
131; CHECK-NEXT:    retq
132;
133  %cmp = icmp slt <4 x i32> %x, zeroinitializer
134  %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
135  ret <4 x i32> %sel
136}
137
138define <4 x i32> @umax_vec2(<4 x i32> %x) {
139; CHECK-LABEL: umax_vec2:
140; CHECK:       # BB#0:
141; CHECK-NEXT:    vpmaxud {{.*}}(%rip), %xmm0, %xmm0
142; CHECK-NEXT:    retq
143;
144  %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
145  %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>, <4 x i32> %x
146  ret <4 x i32> %sel
147}
148
149define <4 x i32> @umin_vec1(<4 x i32> %x) {
150; CHECK-LABEL: umin_vec1:
151; CHECK:       # BB#0:
152; CHECK-NEXT:    vpminud {{.*}}(%rip), %xmm0, %xmm0
153; CHECK-NEXT:    retq
154;
155  %cmp = icmp slt <4 x i32> %x, zeroinitializer
156  %sel = select <4 x i1> %cmp, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %x
157  ret <4 x i32> %sel
158}
159
160define <4 x i32> @umin_vec2(<4 x i32> %x) {
161; CHECK-LABEL: umin_vec2:
162; CHECK:       # BB#0:
163; CHECK-NEXT:    vpminud {{.*}}(%rip), %xmm0, %xmm0
164; CHECK-NEXT:    retq
165;
166  %cmp = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
167  %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
168  ret <4 x i32> %sel
169}
170
171