1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE41 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX,VEX,AVX1 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX,VEX,AVX2 6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=ALL,AVX,AVX512,AVX512F 7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX,AVX512,AVX512VL 8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=ALL,AVX,AVX512,AVX512DQ 9; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX,AVX512,AVX512VLDQ 10; 11; 32-bit tests to make sure we're not doing anything stupid. 12; RUN: llc < %s -mtriple=i686-unknown-unknown 13; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse 14; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 15; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 16 17; 18; Signed Integer to Double 19; 20 21define <2 x double> @sitofp_2i64_to_2f64(<2 x i64> %a) { 22; SSE2-LABEL: sitofp_2i64_to_2f64: 23; SSE2: # %bb.0: 24; SSE2-NEXT: movq %xmm0, %rax 25; SSE2-NEXT: cvtsi2sdq %rax, %xmm1 26; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 27; SSE2-NEXT: movq %xmm0, %rax 28; SSE2-NEXT: xorps %xmm0, %xmm0 29; SSE2-NEXT: cvtsi2sdq %rax, %xmm0 30; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] 31; SSE2-NEXT: movaps %xmm1, %xmm0 32; SSE2-NEXT: retq 33; 34; SSE41-LABEL: sitofp_2i64_to_2f64: 35; SSE41: # %bb.0: 36; SSE41-NEXT: pextrq $1, %xmm0, %rax 37; SSE41-NEXT: cvtsi2sdq %rax, %xmm1 38; SSE41-NEXT: movq %xmm0, %rax 39; SSE41-NEXT: xorps %xmm0, %xmm0 40; SSE41-NEXT: cvtsi2sdq %rax, %xmm0 41; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 42; SSE41-NEXT: retq 43; 44; VEX-LABEL: sitofp_2i64_to_2f64: 45; VEX: # %bb.0: 46; VEX-NEXT: vpextrq $1, %xmm0, %rax 47; VEX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1 48; VEX-NEXT: vmovq %xmm0, %rax 49; VEX-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0 50; VEX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 51; VEX-NEXT: retq 52; 53; AVX512F-LABEL: sitofp_2i64_to_2f64: 54; AVX512F: # %bb.0: 55; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 56; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1 57; AVX512F-NEXT: vmovq %xmm0, %rax 58; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0 59; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 60; AVX512F-NEXT: retq 61; 62; AVX512VL-LABEL: sitofp_2i64_to_2f64: 63; AVX512VL: # %bb.0: 64; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 65; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1 66; AVX512VL-NEXT: vmovq %xmm0, %rax 67; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0 68; AVX512VL-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 69; AVX512VL-NEXT: retq 70; 71; AVX512DQ-LABEL: sitofp_2i64_to_2f64: 72; AVX512DQ: # %bb.0: 73; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 74; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 75; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 76; AVX512DQ-NEXT: vzeroupper 77; AVX512DQ-NEXT: retq 78; 79; AVX512VLDQ-LABEL: sitofp_2i64_to_2f64: 80; AVX512VLDQ: # %bb.0: 81; AVX512VLDQ-NEXT: vcvtqq2pd %xmm0, %xmm0 82; AVX512VLDQ-NEXT: retq 83 %cvt = sitofp <2 x i64> %a to <2 x double> 84 ret <2 x double> %cvt 85} 86 87define <2 x double> @sitofp_2i32_to_2f64(<4 x i32> %a) { 88; SSE-LABEL: sitofp_2i32_to_2f64: 89; SSE: # %bb.0: 90; SSE-NEXT: cvtdq2pd %xmm0, %xmm0 91; SSE-NEXT: retq 92; 93; AVX-LABEL: sitofp_2i32_to_2f64: 94; AVX: # %bb.0: 95; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 96; AVX-NEXT: retq 97 %shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 98 %cvt = sitofp <2 x i32> %shuf to <2 x double> 99 ret <2 x double> %cvt 100} 101 102define <2 x double> @sitofp_4i32_to_2f64(<4 x i32> %a) { 103; SSE-LABEL: sitofp_4i32_to_2f64: 104; SSE: # %bb.0: 105; SSE-NEXT: cvtdq2pd %xmm0, %xmm0 106; SSE-NEXT: retq 107; 108; AVX-LABEL: sitofp_4i32_to_2f64: 109; AVX: # %bb.0: 110; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 111; AVX-NEXT: retq 112 %cvt = sitofp <4 x i32> %a to <4 x double> 113 %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1> 114 ret <2 x double> %shuf 115} 116 117define <2 x double> @sitofp_2i16_to_2f64(<8 x i16> %a) { 118; SSE2-LABEL: sitofp_2i16_to_2f64: 119; SSE2: # %bb.0: 120; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 121; SSE2-NEXT: psrad $16, %xmm0 122; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 123; SSE2-NEXT: retq 124; 125; SSE41-LABEL: sitofp_2i16_to_2f64: 126; SSE41: # %bb.0: 127; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 128; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 129; SSE41-NEXT: retq 130; 131; AVX-LABEL: sitofp_2i16_to_2f64: 132; AVX: # %bb.0: 133; AVX-NEXT: vpmovsxwd %xmm0, %xmm0 134; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 135; AVX-NEXT: retq 136 %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1> 137 %cvt = sitofp <2 x i16> %shuf to <2 x double> 138 ret <2 x double> %cvt 139} 140 141define <2 x double> @sitofp_8i16_to_2f64(<8 x i16> %a) { 142; SSE2-LABEL: sitofp_8i16_to_2f64: 143; SSE2: # %bb.0: 144; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 145; SSE2-NEXT: psrad $16, %xmm0 146; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 147; SSE2-NEXT: retq 148; 149; SSE41-LABEL: sitofp_8i16_to_2f64: 150; SSE41: # %bb.0: 151; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 152; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 153; SSE41-NEXT: retq 154; 155; VEX-LABEL: sitofp_8i16_to_2f64: 156; VEX: # %bb.0: 157; VEX-NEXT: vpmovsxwd %xmm0, %xmm0 158; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0 159; VEX-NEXT: retq 160; 161; AVX512-LABEL: sitofp_8i16_to_2f64: 162; AVX512: # %bb.0: 163; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0 164; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 165; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 166; AVX512-NEXT: vzeroupper 167; AVX512-NEXT: retq 168 %cvt = sitofp <8 x i16> %a to <8 x double> 169 %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1> 170 ret <2 x double> %shuf 171} 172 173define <2 x double> @sitofp_2i8_to_2f64(<16 x i8> %a) { 174; SSE2-LABEL: sitofp_2i8_to_2f64: 175; SSE2: # %bb.0: 176; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 177; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 178; SSE2-NEXT: psrad $24, %xmm0 179; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 180; SSE2-NEXT: retq 181; 182; SSE41-LABEL: sitofp_2i8_to_2f64: 183; SSE41: # %bb.0: 184; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 185; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 186; SSE41-NEXT: retq 187; 188; AVX-LABEL: sitofp_2i8_to_2f64: 189; AVX: # %bb.0: 190; AVX-NEXT: vpmovsxbd %xmm0, %xmm0 191; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 192; AVX-NEXT: retq 193 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1> 194 %cvt = sitofp <2 x i8> %shuf to <2 x double> 195 ret <2 x double> %cvt 196} 197 198define <2 x double> @sitofp_16i8_to_2f64(<16 x i8> %a) { 199; SSE2-LABEL: sitofp_16i8_to_2f64: 200; SSE2: # %bb.0: 201; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 202; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 203; SSE2-NEXT: psrad $24, %xmm0 204; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 205; SSE2-NEXT: retq 206; 207; SSE41-LABEL: sitofp_16i8_to_2f64: 208; SSE41: # %bb.0: 209; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 210; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 211; SSE41-NEXT: retq 212; 213; VEX-LABEL: sitofp_16i8_to_2f64: 214; VEX: # %bb.0: 215; VEX-NEXT: vpmovsxbd %xmm0, %xmm0 216; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0 217; VEX-NEXT: retq 218; 219; AVX512-LABEL: sitofp_16i8_to_2f64: 220; AVX512: # %bb.0: 221; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 222; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 223; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 224; AVX512-NEXT: vzeroupper 225; AVX512-NEXT: retq 226 %cvt = sitofp <16 x i8> %a to <16 x double> 227 %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1> 228 ret <2 x double> %shuf 229} 230 231define <4 x double> @sitofp_4i64_to_4f64(<4 x i64> %a) { 232; SSE2-LABEL: sitofp_4i64_to_4f64: 233; SSE2: # %bb.0: 234; SSE2-NEXT: movq %xmm0, %rax 235; SSE2-NEXT: cvtsi2sdq %rax, %xmm2 236; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 237; SSE2-NEXT: movq %xmm0, %rax 238; SSE2-NEXT: xorps %xmm0, %xmm0 239; SSE2-NEXT: cvtsi2sdq %rax, %xmm0 240; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0] 241; SSE2-NEXT: movq %xmm1, %rax 242; SSE2-NEXT: cvtsi2sdq %rax, %xmm3 243; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1] 244; SSE2-NEXT: movq %xmm0, %rax 245; SSE2-NEXT: xorps %xmm0, %xmm0 246; SSE2-NEXT: cvtsi2sdq %rax, %xmm0 247; SSE2-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0] 248; SSE2-NEXT: movaps %xmm2, %xmm0 249; SSE2-NEXT: movaps %xmm3, %xmm1 250; SSE2-NEXT: retq 251; 252; SSE41-LABEL: sitofp_4i64_to_4f64: 253; SSE41: # %bb.0: 254; SSE41-NEXT: pextrq $1, %xmm0, %rax 255; SSE41-NEXT: cvtsi2sdq %rax, %xmm2 256; SSE41-NEXT: movq %xmm0, %rax 257; SSE41-NEXT: xorps %xmm0, %xmm0 258; SSE41-NEXT: cvtsi2sdq %rax, %xmm0 259; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 260; SSE41-NEXT: pextrq $1, %xmm1, %rax 261; SSE41-NEXT: xorps %xmm2, %xmm2 262; SSE41-NEXT: cvtsi2sdq %rax, %xmm2 263; SSE41-NEXT: movq %xmm1, %rax 264; SSE41-NEXT: xorps %xmm1, %xmm1 265; SSE41-NEXT: cvtsi2sdq %rax, %xmm1 266; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 267; SSE41-NEXT: retq 268; 269; AVX1-LABEL: sitofp_4i64_to_4f64: 270; AVX1: # %bb.0: 271; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 272; AVX1-NEXT: vpextrq $1, %xmm1, %rax 273; AVX1-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 274; AVX1-NEXT: vmovq %xmm1, %rax 275; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1 276; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 277; AVX1-NEXT: vpextrq $1, %xmm0, %rax 278; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2 279; AVX1-NEXT: vmovq %xmm0, %rax 280; AVX1-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0 281; AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 282; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 283; AVX1-NEXT: retq 284; 285; AVX2-LABEL: sitofp_4i64_to_4f64: 286; AVX2: # %bb.0: 287; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 288; AVX2-NEXT: vpextrq $1, %xmm1, %rax 289; AVX2-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 290; AVX2-NEXT: vmovq %xmm1, %rax 291; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1 292; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 293; AVX2-NEXT: vpextrq $1, %xmm0, %rax 294; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2 295; AVX2-NEXT: vmovq %xmm0, %rax 296; AVX2-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0 297; AVX2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 298; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 299; AVX2-NEXT: retq 300; 301; AVX512F-LABEL: sitofp_4i64_to_4f64: 302; AVX512F: # %bb.0: 303; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1 304; AVX512F-NEXT: vpextrq $1, %xmm1, %rax 305; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 306; AVX512F-NEXT: vmovq %xmm1, %rax 307; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1 308; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 309; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 310; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2 311; AVX512F-NEXT: vmovq %xmm0, %rax 312; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0 313; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 314; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 315; AVX512F-NEXT: retq 316; 317; AVX512VL-LABEL: sitofp_4i64_to_4f64: 318; AVX512VL: # %bb.0: 319; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1 320; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax 321; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 322; AVX512VL-NEXT: vmovq %xmm1, %rax 323; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1 324; AVX512VL-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 325; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 326; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2 327; AVX512VL-NEXT: vmovq %xmm0, %rax 328; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0 329; AVX512VL-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 330; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 331; AVX512VL-NEXT: retq 332; 333; AVX512DQ-LABEL: sitofp_4i64_to_4f64: 334; AVX512DQ: # %bb.0: 335; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 336; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 337; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 338; AVX512DQ-NEXT: retq 339; 340; AVX512VLDQ-LABEL: sitofp_4i64_to_4f64: 341; AVX512VLDQ: # %bb.0: 342; AVX512VLDQ-NEXT: vcvtqq2pd %ymm0, %ymm0 343; AVX512VLDQ-NEXT: retq 344 %cvt = sitofp <4 x i64> %a to <4 x double> 345 ret <4 x double> %cvt 346} 347 348define <4 x double> @sitofp_4i32_to_4f64(<4 x i32> %a) { 349; SSE-LABEL: sitofp_4i32_to_4f64: 350; SSE: # %bb.0: 351; SSE-NEXT: cvtdq2pd %xmm0, %xmm2 352; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 353; SSE-NEXT: cvtdq2pd %xmm0, %xmm1 354; SSE-NEXT: movaps %xmm2, %xmm0 355; SSE-NEXT: retq 356; 357; AVX-LABEL: sitofp_4i32_to_4f64: 358; AVX: # %bb.0: 359; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 360; AVX-NEXT: retq 361 %cvt = sitofp <4 x i32> %a to <4 x double> 362 ret <4 x double> %cvt 363} 364 365define <4 x double> @sitofp_4i16_to_4f64(<8 x i16> %a) { 366; SSE2-LABEL: sitofp_4i16_to_4f64: 367; SSE2: # %bb.0: 368; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 369; SSE2-NEXT: psrad $16, %xmm1 370; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 371; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 372; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 373; SSE2-NEXT: retq 374; 375; SSE41-LABEL: sitofp_4i16_to_4f64: 376; SSE41: # %bb.0: 377; SSE41-NEXT: pmovsxwd %xmm0, %xmm1 378; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 379; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 380; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 381; SSE41-NEXT: retq 382; 383; AVX-LABEL: sitofp_4i16_to_4f64: 384; AVX: # %bb.0: 385; AVX-NEXT: vpmovsxwd %xmm0, %xmm0 386; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 387; AVX-NEXT: retq 388 %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 389 %cvt = sitofp <4 x i16> %shuf to <4 x double> 390 ret <4 x double> %cvt 391} 392 393define <4 x double> @sitofp_8i16_to_4f64(<8 x i16> %a) { 394; SSE2-LABEL: sitofp_8i16_to_4f64: 395; SSE2: # %bb.0: 396; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 397; SSE2-NEXT: psrad $16, %xmm1 398; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 399; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 400; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 401; SSE2-NEXT: retq 402; 403; SSE41-LABEL: sitofp_8i16_to_4f64: 404; SSE41: # %bb.0: 405; SSE41-NEXT: pmovsxwd %xmm0, %xmm1 406; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 407; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 408; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 409; SSE41-NEXT: retq 410; 411; VEX-LABEL: sitofp_8i16_to_4f64: 412; VEX: # %bb.0: 413; VEX-NEXT: vpmovsxwd %xmm0, %xmm0 414; VEX-NEXT: vcvtdq2pd %xmm0, %ymm0 415; VEX-NEXT: retq 416; 417; AVX512-LABEL: sitofp_8i16_to_4f64: 418; AVX512: # %bb.0: 419; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0 420; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 421; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 422; AVX512-NEXT: retq 423 %cvt = sitofp <8 x i16> %a to <8 x double> 424 %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 425 ret <4 x double> %shuf 426} 427 428define <4 x double> @sitofp_4i8_to_4f64(<16 x i8> %a) { 429; SSE2-LABEL: sitofp_4i8_to_4f64: 430; SSE2: # %bb.0: 431; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 432; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 433; SSE2-NEXT: psrad $24, %xmm1 434; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 435; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 436; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 437; SSE2-NEXT: retq 438; 439; SSE41-LABEL: sitofp_4i8_to_4f64: 440; SSE41: # %bb.0: 441; SSE41-NEXT: pmovsxbd %xmm0, %xmm1 442; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 443; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 444; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 445; SSE41-NEXT: retq 446; 447; AVX-LABEL: sitofp_4i8_to_4f64: 448; AVX: # %bb.0: 449; AVX-NEXT: vpmovsxbd %xmm0, %xmm0 450; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 451; AVX-NEXT: retq 452 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 453 %cvt = sitofp <4 x i8> %shuf to <4 x double> 454 ret <4 x double> %cvt 455} 456 457define <4 x double> @sitofp_16i8_to_4f64(<16 x i8> %a) { 458; SSE2-LABEL: sitofp_16i8_to_4f64: 459; SSE2: # %bb.0: 460; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 461; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 462; SSE2-NEXT: psrad $24, %xmm1 463; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 464; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 465; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 466; SSE2-NEXT: retq 467; 468; SSE41-LABEL: sitofp_16i8_to_4f64: 469; SSE41: # %bb.0: 470; SSE41-NEXT: pmovsxbd %xmm0, %xmm1 471; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 472; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 473; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 474; SSE41-NEXT: retq 475; 476; VEX-LABEL: sitofp_16i8_to_4f64: 477; VEX: # %bb.0: 478; VEX-NEXT: vpmovsxbd %xmm0, %xmm0 479; VEX-NEXT: vcvtdq2pd %xmm0, %ymm0 480; VEX-NEXT: retq 481; 482; AVX512-LABEL: sitofp_16i8_to_4f64: 483; AVX512: # %bb.0: 484; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 485; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 486; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 487; AVX512-NEXT: retq 488 %cvt = sitofp <16 x i8> %a to <16 x double> 489 %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 490 ret <4 x double> %shuf 491} 492 493; 494; Unsigned Integer to Double 495; 496 497define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) { 498; SSE2-LABEL: uitofp_2i64_to_2f64: 499; SSE2: # %bb.0: 500; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295] 501; SSE2-NEXT: pand %xmm0, %xmm1 502; SSE2-NEXT: por {{.*}}(%rip), %xmm1 503; SSE2-NEXT: psrlq $32, %xmm0 504; SSE2-NEXT: por {{.*}}(%rip), %xmm0 505; SSE2-NEXT: subpd {{.*}}(%rip), %xmm0 506; SSE2-NEXT: addpd %xmm1, %xmm0 507; SSE2-NEXT: retq 508; 509; SSE41-LABEL: uitofp_2i64_to_2f64: 510; SSE41: # %bb.0: 511; SSE41-NEXT: pxor %xmm1, %xmm1 512; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 513; SSE41-NEXT: por {{.*}}(%rip), %xmm1 514; SSE41-NEXT: psrlq $32, %xmm0 515; SSE41-NEXT: por {{.*}}(%rip), %xmm0 516; SSE41-NEXT: subpd {{.*}}(%rip), %xmm0 517; SSE41-NEXT: addpd %xmm1, %xmm0 518; SSE41-NEXT: retq 519; 520; AVX1-LABEL: uitofp_2i64_to_2f64: 521; AVX1: # %bb.0: 522; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 523; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 524; AVX1-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 525; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0 526; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 527; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 528; AVX1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 529; AVX1-NEXT: retq 530; 531; AVX2-LABEL: uitofp_2i64_to_2f64: 532; AVX2: # %bb.0: 533; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 534; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 535; AVX2-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 536; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0 537; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 538; AVX2-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 539; AVX2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 540; AVX2-NEXT: retq 541; 542; AVX512F-LABEL: uitofp_2i64_to_2f64: 543; AVX512F: # %bb.0: 544; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 545; AVX512F-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 546; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 547; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm0 548; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 549; AVX512F-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 550; AVX512F-NEXT: vaddpd %xmm0, %xmm1, %xmm0 551; AVX512F-NEXT: retq 552; 553; AVX512VL-LABEL: uitofp_2i64_to_2f64: 554; AVX512VL: # %bb.0: 555; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1 556; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 557; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0 558; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 559; AVX512VL-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 560; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0 561; AVX512VL-NEXT: retq 562; 563; AVX512DQ-LABEL: uitofp_2i64_to_2f64: 564; AVX512DQ: # %bb.0: 565; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 566; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 567; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 568; AVX512DQ-NEXT: vzeroupper 569; AVX512DQ-NEXT: retq 570; 571; AVX512VLDQ-LABEL: uitofp_2i64_to_2f64: 572; AVX512VLDQ: # %bb.0: 573; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm0, %xmm0 574; AVX512VLDQ-NEXT: retq 575 %cvt = uitofp <2 x i64> %a to <2 x double> 576 ret <2 x double> %cvt 577} 578 579define <2 x double> @uitofp_2i32_to_2f64(<4 x i32> %a) { 580; SSE2-LABEL: uitofp_2i32_to_2f64: 581; SSE2: # %bb.0: 582; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0] 583; SSE2-NEXT: pand %xmm0, %xmm1 584; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 585; SSE2-NEXT: psrld $16, %xmm0 586; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 587; SSE2-NEXT: mulpd {{.*}}(%rip), %xmm0 588; SSE2-NEXT: addpd %xmm1, %xmm0 589; SSE2-NEXT: retq 590; 591; SSE41-LABEL: uitofp_2i32_to_2f64: 592; SSE41: # %bb.0: 593; SSE41-NEXT: pxor %xmm1, %xmm1 594; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7] 595; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 596; SSE41-NEXT: psrld $16, %xmm0 597; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 598; SSE41-NEXT: mulpd {{.*}}(%rip), %xmm0 599; SSE41-NEXT: addpd %xmm1, %xmm0 600; SSE41-NEXT: retq 601; 602; VEX-LABEL: uitofp_2i32_to_2f64: 603; VEX: # %bb.0: 604; VEX-NEXT: vpxor %xmm1, %xmm1, %xmm1 605; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7] 606; VEX-NEXT: vcvtdq2pd %xmm1, %xmm1 607; VEX-NEXT: vpsrld $16, %xmm0, %xmm0 608; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0 609; VEX-NEXT: vmulpd {{.*}}(%rip), %xmm0, %xmm0 610; VEX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 611; VEX-NEXT: retq 612; 613; AVX512F-LABEL: uitofp_2i32_to_2f64: 614; AVX512F: # %bb.0: 615; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 616; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 617; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 618; AVX512F-NEXT: vzeroupper 619; AVX512F-NEXT: retq 620; 621; AVX512VL-LABEL: uitofp_2i32_to_2f64: 622; AVX512VL: # %bb.0: 623; AVX512VL-NEXT: vcvtudq2pd %xmm0, %xmm0 624; AVX512VL-NEXT: retq 625; 626; AVX512DQ-LABEL: uitofp_2i32_to_2f64: 627; AVX512DQ: # %bb.0: 628; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 629; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 630; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 631; AVX512DQ-NEXT: vzeroupper 632; AVX512DQ-NEXT: retq 633; 634; AVX512VLDQ-LABEL: uitofp_2i32_to_2f64: 635; AVX512VLDQ: # %bb.0: 636; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %xmm0 637; AVX512VLDQ-NEXT: retq 638 %shuf = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1> 639 %cvt = uitofp <2 x i32> %shuf to <2 x double> 640 ret <2 x double> %cvt 641} 642 643define <2 x double> @uitofp_4i32_to_2f64(<4 x i32> %a) { 644; SSE2-LABEL: uitofp_4i32_to_2f64: 645; SSE2: # %bb.0: 646; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0] 647; SSE2-NEXT: pand %xmm0, %xmm1 648; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 649; SSE2-NEXT: psrld $16, %xmm0 650; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 651; SSE2-NEXT: mulpd {{.*}}(%rip), %xmm0 652; SSE2-NEXT: addpd %xmm1, %xmm0 653; SSE2-NEXT: retq 654; 655; SSE41-LABEL: uitofp_4i32_to_2f64: 656; SSE41: # %bb.0: 657; SSE41-NEXT: pxor %xmm1, %xmm1 658; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7] 659; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 660; SSE41-NEXT: psrld $16, %xmm0 661; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 662; SSE41-NEXT: mulpd {{.*}}(%rip), %xmm0 663; SSE41-NEXT: addpd %xmm1, %xmm0 664; SSE41-NEXT: retq 665; 666; VEX-LABEL: uitofp_4i32_to_2f64: 667; VEX: # %bb.0: 668; VEX-NEXT: vpxor %xmm1, %xmm1, %xmm1 669; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 670; VEX-NEXT: vpsrld $16, %xmm0, %xmm0 671; VEX-NEXT: vcvtdq2pd %xmm1, %xmm1 672; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0 673; VEX-NEXT: vmulpd {{.*}}(%rip), %xmm0, %xmm0 674; VEX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 675; VEX-NEXT: retq 676; 677; AVX512F-LABEL: uitofp_4i32_to_2f64: 678; AVX512F: # %bb.0: 679; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 680; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 681; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 682; AVX512F-NEXT: vzeroupper 683; AVX512F-NEXT: retq 684; 685; AVX512VL-LABEL: uitofp_4i32_to_2f64: 686; AVX512VL: # %bb.0: 687; AVX512VL-NEXT: vcvtudq2pd %xmm0, %xmm0 688; AVX512VL-NEXT: retq 689; 690; AVX512DQ-LABEL: uitofp_4i32_to_2f64: 691; AVX512DQ: # %bb.0: 692; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 693; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 694; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 695; AVX512DQ-NEXT: vzeroupper 696; AVX512DQ-NEXT: retq 697; 698; AVX512VLDQ-LABEL: uitofp_4i32_to_2f64: 699; AVX512VLDQ: # %bb.0: 700; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %xmm0 701; AVX512VLDQ-NEXT: retq 702 %cvt = uitofp <4 x i32> %a to <4 x double> 703 %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1> 704 ret <2 x double> %shuf 705} 706 707define <2 x double> @uitofp_2i16_to_2f64(<8 x i16> %a) { 708; SSE2-LABEL: uitofp_2i16_to_2f64: 709; SSE2: # %bb.0: 710; SSE2-NEXT: pxor %xmm1, %xmm1 711; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 712; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 713; SSE2-NEXT: retq 714; 715; SSE41-LABEL: uitofp_2i16_to_2f64: 716; SSE41: # %bb.0: 717; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 718; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 719; SSE41-NEXT: retq 720; 721; AVX-LABEL: uitofp_2i16_to_2f64: 722; AVX: # %bb.0: 723; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 724; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 725; AVX-NEXT: retq 726 %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1> 727 %cvt = uitofp <2 x i16> %shuf to <2 x double> 728 ret <2 x double> %cvt 729} 730 731define <2 x double> @uitofp_8i16_to_2f64(<8 x i16> %a) { 732; SSE2-LABEL: uitofp_8i16_to_2f64: 733; SSE2: # %bb.0: 734; SSE2-NEXT: pxor %xmm1, %xmm1 735; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 736; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 737; SSE2-NEXT: retq 738; 739; SSE41-LABEL: uitofp_8i16_to_2f64: 740; SSE41: # %bb.0: 741; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 742; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 743; SSE41-NEXT: retq 744; 745; VEX-LABEL: uitofp_8i16_to_2f64: 746; VEX: # %bb.0: 747; VEX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 748; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0 749; VEX-NEXT: retq 750; 751; AVX512-LABEL: uitofp_8i16_to_2f64: 752; AVX512: # %bb.0: 753; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 754; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 755; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 756; AVX512-NEXT: vzeroupper 757; AVX512-NEXT: retq 758 %cvt = uitofp <8 x i16> %a to <8 x double> 759 %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1> 760 ret <2 x double> %shuf 761} 762 763define <2 x double> @uitofp_2i8_to_2f64(<16 x i8> %a) { 764; SSE2-LABEL: uitofp_2i8_to_2f64: 765; SSE2: # %bb.0: 766; SSE2-NEXT: pxor %xmm1, %xmm1 767; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 768; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 769; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 770; SSE2-NEXT: retq 771; 772; SSE41-LABEL: uitofp_2i8_to_2f64: 773; SSE41: # %bb.0: 774; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 775; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 776; SSE41-NEXT: retq 777; 778; AVX-LABEL: uitofp_2i8_to_2f64: 779; AVX: # %bb.0: 780; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 781; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 782; AVX-NEXT: retq 783 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1> 784 %cvt = uitofp <2 x i8> %shuf to <2 x double> 785 ret <2 x double> %cvt 786} 787 788define <2 x double> @uitofp_16i8_to_2f64(<16 x i8> %a) { 789; SSE2-LABEL: uitofp_16i8_to_2f64: 790; SSE2: # %bb.0: 791; SSE2-NEXT: pxor %xmm1, %xmm1 792; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 793; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 794; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 795; SSE2-NEXT: retq 796; 797; SSE41-LABEL: uitofp_16i8_to_2f64: 798; SSE41: # %bb.0: 799; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 800; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 801; SSE41-NEXT: retq 802; 803; VEX-LABEL: uitofp_16i8_to_2f64: 804; VEX: # %bb.0: 805; VEX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 806; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0 807; VEX-NEXT: retq 808; 809; AVX512-LABEL: uitofp_16i8_to_2f64: 810; AVX512: # %bb.0: 811; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero 812; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 813; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 814; AVX512-NEXT: vzeroupper 815; AVX512-NEXT: retq 816 %cvt = uitofp <16 x i8> %a to <16 x double> 817 %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1> 818 ret <2 x double> %shuf 819} 820 821define <4 x double> @uitofp_4i64_to_4f64(<4 x i64> %a) { 822; SSE2-LABEL: uitofp_4i64_to_4f64: 823; SSE2: # %bb.0: 824; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295] 825; SSE2-NEXT: movdqa %xmm0, %xmm3 826; SSE2-NEXT: pand %xmm2, %xmm3 827; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200] 828; SSE2-NEXT: por %xmm4, %xmm3 829; SSE2-NEXT: psrlq $32, %xmm0 830; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072] 831; SSE2-NEXT: por %xmm5, %xmm0 832; SSE2-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25] 833; SSE2-NEXT: subpd %xmm6, %xmm0 834; SSE2-NEXT: addpd %xmm3, %xmm0 835; SSE2-NEXT: pand %xmm1, %xmm2 836; SSE2-NEXT: por %xmm4, %xmm2 837; SSE2-NEXT: psrlq $32, %xmm1 838; SSE2-NEXT: por %xmm5, %xmm1 839; SSE2-NEXT: subpd %xmm6, %xmm1 840; SSE2-NEXT: addpd %xmm2, %xmm1 841; SSE2-NEXT: retq 842; 843; SSE41-LABEL: uitofp_4i64_to_4f64: 844; SSE41: # %bb.0: 845; SSE41-NEXT: pxor %xmm2, %xmm2 846; SSE41-NEXT: movdqa %xmm0, %xmm3 847; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] 848; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200] 849; SSE41-NEXT: por %xmm4, %xmm3 850; SSE41-NEXT: psrlq $32, %xmm0 851; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072] 852; SSE41-NEXT: por %xmm5, %xmm0 853; SSE41-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25] 854; SSE41-NEXT: subpd %xmm6, %xmm0 855; SSE41-NEXT: addpd %xmm3, %xmm0 856; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] 857; SSE41-NEXT: por %xmm4, %xmm2 858; SSE41-NEXT: psrlq $32, %xmm1 859; SSE41-NEXT: por %xmm5, %xmm1 860; SSE41-NEXT: subpd %xmm6, %xmm1 861; SSE41-NEXT: addpd %xmm2, %xmm1 862; SSE41-NEXT: retq 863; 864; AVX1-LABEL: uitofp_4i64_to_4f64: 865; AVX1: # %bb.0: 866; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 867; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 868; AVX1-NEXT: vorps {{.*}}(%rip), %ymm1, %ymm1 869; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm2 870; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 871; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0 872; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 873; AVX1-NEXT: vorpd {{.*}}(%rip), %ymm0, %ymm0 874; AVX1-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0 875; AVX1-NEXT: vaddpd %ymm0, %ymm1, %ymm0 876; AVX1-NEXT: retq 877; 878; AVX2-LABEL: uitofp_4i64_to_4f64: 879; AVX2: # %bb.0: 880; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 881; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 882; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200] 883; AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1 884; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm0 885; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4985484787499139072,4985484787499139072,4985484787499139072,4985484787499139072] 886; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0 887; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25] 888; AVX2-NEXT: vsubpd %ymm2, %ymm0, %ymm0 889; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0 890; AVX2-NEXT: retq 891; 892; AVX512F-LABEL: uitofp_4i64_to_4f64: 893; AVX512F: # %bb.0: 894; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 895; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 896; AVX512F-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200] 897; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1 898; AVX512F-NEXT: vpsrlq $32, %ymm0, %ymm0 899; AVX512F-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4985484787499139072,4985484787499139072,4985484787499139072,4985484787499139072] 900; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 901; AVX512F-NEXT: vbroadcastsd {{.*#+}} ymm2 = [1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25] 902; AVX512F-NEXT: vsubpd %ymm2, %ymm0, %ymm0 903; AVX512F-NEXT: vaddpd %ymm0, %ymm1, %ymm0 904; AVX512F-NEXT: retq 905; 906; AVX512VL-LABEL: uitofp_4i64_to_4f64: 907; AVX512VL: # %bb.0: 908; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm0, %ymm1 909; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm1, %ymm1 910; AVX512VL-NEXT: vpsrlq $32, %ymm0, %ymm0 911; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm0, %ymm0 912; AVX512VL-NEXT: vsubpd {{.*}}(%rip){1to4}, %ymm0, %ymm0 913; AVX512VL-NEXT: vaddpd %ymm0, %ymm1, %ymm0 914; AVX512VL-NEXT: retq 915; 916; AVX512DQ-LABEL: uitofp_4i64_to_4f64: 917; AVX512DQ: # %bb.0: 918; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 919; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 920; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 921; AVX512DQ-NEXT: retq 922; 923; AVX512VLDQ-LABEL: uitofp_4i64_to_4f64: 924; AVX512VLDQ: # %bb.0: 925; AVX512VLDQ-NEXT: vcvtuqq2pd %ymm0, %ymm0 926; AVX512VLDQ-NEXT: retq 927 %cvt = uitofp <4 x i64> %a to <4 x double> 928 ret <4 x double> %cvt 929} 930 931define <4 x double> @uitofp_4i32_to_4f64(<4 x i32> %a) { 932; SSE2-LABEL: uitofp_4i32_to_4f64: 933; SSE2: # %bb.0: 934; SSE2-NEXT: movdqa %xmm0, %xmm1 935; SSE2-NEXT: psrld $16, %xmm1 936; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 937; SSE2-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4] 938; SSE2-NEXT: mulpd %xmm2, %xmm1 939; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65535,0,65535,0,0,0,0,0] 940; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1] 941; SSE2-NEXT: pand %xmm3, %xmm0 942; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 943; SSE2-NEXT: addpd %xmm1, %xmm0 944; SSE2-NEXT: movdqa %xmm4, %xmm1 945; SSE2-NEXT: psrld $16, %xmm1 946; SSE2-NEXT: cvtdq2pd %xmm1, %xmm5 947; SSE2-NEXT: mulpd %xmm2, %xmm5 948; SSE2-NEXT: pand %xmm3, %xmm4 949; SSE2-NEXT: cvtdq2pd %xmm4, %xmm1 950; SSE2-NEXT: addpd %xmm5, %xmm1 951; SSE2-NEXT: retq 952; 953; SSE41-LABEL: uitofp_4i32_to_4f64: 954; SSE41: # %bb.0: 955; SSE41-NEXT: movdqa %xmm0, %xmm1 956; SSE41-NEXT: psrld $16, %xmm1 957; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 958; SSE41-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4] 959; SSE41-NEXT: mulpd %xmm2, %xmm1 960; SSE41-NEXT: pxor %xmm3, %xmm3 961; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1] 962; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4,5,6,7] 963; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 964; SSE41-NEXT: addpd %xmm1, %xmm0 965; SSE41-NEXT: movdqa %xmm4, %xmm1 966; SSE41-NEXT: psrld $16, %xmm1 967; SSE41-NEXT: cvtdq2pd %xmm1, %xmm5 968; SSE41-NEXT: mulpd %xmm2, %xmm5 969; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm3[1],xmm4[2],xmm3[3],xmm4[4,5,6,7] 970; SSE41-NEXT: cvtdq2pd %xmm4, %xmm1 971; SSE41-NEXT: addpd %xmm5, %xmm1 972; SSE41-NEXT: retq 973; 974; AVX1-LABEL: uitofp_4i32_to_4f64: 975; AVX1: # %bb.0: 976; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 977; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 978; AVX1-NEXT: vcvtdq2pd %xmm1, %ymm1 979; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0 980; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 981; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0 982; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0 983; AVX1-NEXT: retq 984; 985; AVX2-LABEL: uitofp_4i32_to_4f64: 986; AVX2: # %bb.0: 987; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1 988; AVX2-NEXT: vcvtdq2pd %xmm1, %ymm1 989; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4] 990; AVX2-NEXT: vmulpd %ymm2, %ymm1, %ymm1 991; AVX2-NEXT: vxorpd %xmm2, %xmm2, %xmm2 992; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] 993; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 994; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0 995; AVX2-NEXT: retq 996; 997; AVX512F-LABEL: uitofp_4i32_to_4f64: 998; AVX512F: # %bb.0: 999; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 1000; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 1001; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 1002; AVX512F-NEXT: retq 1003; 1004; AVX512VL-LABEL: uitofp_4i32_to_4f64: 1005; AVX512VL: # %bb.0: 1006; AVX512VL-NEXT: vcvtudq2pd %xmm0, %ymm0 1007; AVX512VL-NEXT: retq 1008; 1009; AVX512DQ-LABEL: uitofp_4i32_to_4f64: 1010; AVX512DQ: # %bb.0: 1011; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 1012; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 1013; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 1014; AVX512DQ-NEXT: retq 1015; 1016; AVX512VLDQ-LABEL: uitofp_4i32_to_4f64: 1017; AVX512VLDQ: # %bb.0: 1018; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %ymm0 1019; AVX512VLDQ-NEXT: retq 1020 %cvt = uitofp <4 x i32> %a to <4 x double> 1021 ret <4 x double> %cvt 1022} 1023 1024define <4 x double> @uitofp_4i16_to_4f64(<8 x i16> %a) { 1025; SSE2-LABEL: uitofp_4i16_to_4f64: 1026; SSE2: # %bb.0: 1027; SSE2-NEXT: pxor %xmm1, %xmm1 1028; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 1029; SSE2-NEXT: cvtdq2pd %xmm0, %xmm2 1030; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1031; SSE2-NEXT: cvtdq2pd %xmm0, %xmm1 1032; SSE2-NEXT: movaps %xmm2, %xmm0 1033; SSE2-NEXT: retq 1034; 1035; SSE41-LABEL: uitofp_4i16_to_4f64: 1036; SSE41: # %bb.0: 1037; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 1038; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 1039; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 1040; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 1041; SSE41-NEXT: retq 1042; 1043; AVX-LABEL: uitofp_4i16_to_4f64: 1044; AVX: # %bb.0: 1045; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 1046; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 1047; AVX-NEXT: retq 1048 %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1049 %cvt = uitofp <4 x i16> %shuf to <4 x double> 1050 ret <4 x double> %cvt 1051} 1052 1053define <4 x double> @uitofp_8i16_to_4f64(<8 x i16> %a) { 1054; SSE2-LABEL: uitofp_8i16_to_4f64: 1055; SSE2: # %bb.0: 1056; SSE2-NEXT: pxor %xmm1, %xmm1 1057; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 1058; SSE2-NEXT: cvtdq2pd %xmm0, %xmm2 1059; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1060; SSE2-NEXT: cvtdq2pd %xmm0, %xmm1 1061; SSE2-NEXT: movaps %xmm2, %xmm0 1062; SSE2-NEXT: retq 1063; 1064; SSE41-LABEL: uitofp_8i16_to_4f64: 1065; SSE41: # %bb.0: 1066; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 1067; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 1068; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 1069; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 1070; SSE41-NEXT: retq 1071; 1072; VEX-LABEL: uitofp_8i16_to_4f64: 1073; VEX: # %bb.0: 1074; VEX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 1075; VEX-NEXT: vcvtdq2pd %xmm0, %ymm0 1076; VEX-NEXT: retq 1077; 1078; AVX512-LABEL: uitofp_8i16_to_4f64: 1079; AVX512: # %bb.0: 1080; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 1081; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 1082; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 1083; AVX512-NEXT: retq 1084 %cvt = uitofp <8 x i16> %a to <8 x double> 1085 %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1086 ret <4 x double> %shuf 1087} 1088 1089define <4 x double> @uitofp_4i8_to_4f64(<16 x i8> %a) { 1090; SSE2-LABEL: uitofp_4i8_to_4f64: 1091; SSE2: # %bb.0: 1092; SSE2-NEXT: pxor %xmm1, %xmm1 1093; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 1094; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 1095; SSE2-NEXT: cvtdq2pd %xmm0, %xmm2 1096; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1097; SSE2-NEXT: cvtdq2pd %xmm0, %xmm1 1098; SSE2-NEXT: movaps %xmm2, %xmm0 1099; SSE2-NEXT: retq 1100; 1101; SSE41-LABEL: uitofp_4i8_to_4f64: 1102; SSE41: # %bb.0: 1103; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 1104; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 1105; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 1106; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 1107; SSE41-NEXT: retq 1108; 1109; AVX-LABEL: uitofp_4i8_to_4f64: 1110; AVX: # %bb.0: 1111; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 1112; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 1113; AVX-NEXT: retq 1114 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1115 %cvt = uitofp <4 x i8> %shuf to <4 x double> 1116 ret <4 x double> %cvt 1117} 1118 1119define <4 x double> @uitofp_16i8_to_4f64(<16 x i8> %a) { 1120; SSE2-LABEL: uitofp_16i8_to_4f64: 1121; SSE2: # %bb.0: 1122; SSE2-NEXT: pxor %xmm1, %xmm1 1123; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 1124; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 1125; SSE2-NEXT: cvtdq2pd %xmm0, %xmm2 1126; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1127; SSE2-NEXT: cvtdq2pd %xmm0, %xmm1 1128; SSE2-NEXT: movaps %xmm2, %xmm0 1129; SSE2-NEXT: retq 1130; 1131; SSE41-LABEL: uitofp_16i8_to_4f64: 1132; SSE41: # %bb.0: 1133; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 1134; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 1135; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 1136; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 1137; SSE41-NEXT: retq 1138; 1139; VEX-LABEL: uitofp_16i8_to_4f64: 1140; VEX: # %bb.0: 1141; VEX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 1142; VEX-NEXT: vcvtdq2pd %xmm0, %ymm0 1143; VEX-NEXT: retq 1144; 1145; AVX512-LABEL: uitofp_16i8_to_4f64: 1146; AVX512: # %bb.0: 1147; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero 1148; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 1149; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 1150; AVX512-NEXT: retq 1151 %cvt = uitofp <16 x i8> %a to <16 x double> 1152 %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1153 ret <4 x double> %shuf 1154} 1155 1156; 1157; Signed Integer to Float 1158; 1159 1160define <4 x float> @sitofp_2i64_to_4f32(<2 x i64> %a) { 1161; SSE2-LABEL: sitofp_2i64_to_4f32: 1162; SSE2: # %bb.0: 1163; SSE2-NEXT: movq %xmm0, %rax 1164; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1165; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1166; SSE2-NEXT: movq %xmm0, %rax 1167; SSE2-NEXT: xorps %xmm0, %xmm0 1168; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 1169; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 1170; SSE2-NEXT: movaps %xmm1, %xmm0 1171; SSE2-NEXT: retq 1172; 1173; SSE41-LABEL: sitofp_2i64_to_4f32: 1174; SSE41: # %bb.0: 1175; SSE41-NEXT: pextrq $1, %xmm0, %rax 1176; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 1177; SSE41-NEXT: movq %xmm0, %rax 1178; SSE41-NEXT: xorps %xmm0, %xmm0 1179; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 1180; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1181; SSE41-NEXT: retq 1182; 1183; VEX-LABEL: sitofp_2i64_to_4f32: 1184; VEX: # %bb.0: 1185; VEX-NEXT: vpextrq $1, %xmm0, %rax 1186; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1187; VEX-NEXT: vmovq %xmm0, %rax 1188; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1189; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1190; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 1191; VEX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1192; VEX-NEXT: retq 1193; 1194; AVX512F-LABEL: sitofp_2i64_to_4f32: 1195; AVX512F: # %bb.0: 1196; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 1197; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1198; AVX512F-NEXT: vmovq %xmm0, %rax 1199; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1200; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1201; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 1202; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1203; AVX512F-NEXT: retq 1204; 1205; AVX512VL-LABEL: sitofp_2i64_to_4f32: 1206; AVX512VL: # %bb.0: 1207; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 1208; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1209; AVX512VL-NEXT: vmovq %xmm0, %rax 1210; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1211; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1212; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 1213; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1214; AVX512VL-NEXT: retq 1215; 1216; AVX512DQ-LABEL: sitofp_2i64_to_4f32: 1217; AVX512DQ: # %bb.0: 1218; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 1219; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 1220; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1221; AVX512DQ-NEXT: vzeroupper 1222; AVX512DQ-NEXT: retq 1223; 1224; AVX512VLDQ-LABEL: sitofp_2i64_to_4f32: 1225; AVX512VLDQ: # %bb.0: 1226; AVX512VLDQ-NEXT: vcvtqq2ps %xmm0, %xmm0 1227; AVX512VLDQ-NEXT: retq 1228 %cvt = sitofp <2 x i64> %a to <2 x float> 1229 %ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 1230 ret <4 x float> %ext 1231} 1232 1233define <4 x float> @sitofp_2i64_to_4f32_zero(<2 x i64> %a) { 1234; SSE2-LABEL: sitofp_2i64_to_4f32_zero: 1235; SSE2: # %bb.0: 1236; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] 1237; SSE2-NEXT: movq %xmm1, %rax 1238; SSE2-NEXT: xorps %xmm1, %xmm1 1239; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1240; SSE2-NEXT: movq %xmm0, %rax 1241; SSE2-NEXT: xorps %xmm0, %xmm0 1242; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 1243; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 1244; SSE2-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero 1245; SSE2-NEXT: retq 1246; 1247; SSE41-LABEL: sitofp_2i64_to_4f32_zero: 1248; SSE41: # %bb.0: 1249; SSE41-NEXT: movq %xmm0, %rax 1250; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 1251; SSE41-NEXT: pextrq $1, %xmm0, %rax 1252; SSE41-NEXT: xorps %xmm0, %xmm0 1253; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 1254; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[0],zero,zero 1255; SSE41-NEXT: movaps %xmm1, %xmm0 1256; SSE41-NEXT: retq 1257; 1258; VEX-LABEL: sitofp_2i64_to_4f32_zero: 1259; VEX: # %bb.0: 1260; VEX-NEXT: vmovq %xmm0, %rax 1261; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1262; VEX-NEXT: vpextrq $1, %xmm0, %rax 1263; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1264; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero 1265; VEX-NEXT: retq 1266; 1267; AVX512F-LABEL: sitofp_2i64_to_4f32_zero: 1268; AVX512F: # %bb.0: 1269; AVX512F-NEXT: vmovq %xmm0, %rax 1270; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1271; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 1272; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1273; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero 1274; AVX512F-NEXT: retq 1275; 1276; AVX512VL-LABEL: sitofp_2i64_to_4f32_zero: 1277; AVX512VL: # %bb.0: 1278; AVX512VL-NEXT: vmovq %xmm0, %rax 1279; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1280; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 1281; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1282; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 1283; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero 1284; AVX512VL-NEXT: retq 1285; 1286; AVX512DQ-LABEL: sitofp_2i64_to_4f32_zero: 1287; AVX512DQ: # %bb.0: 1288; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 1289; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 1290; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero 1291; AVX512DQ-NEXT: vzeroupper 1292; AVX512DQ-NEXT: retq 1293; 1294; AVX512VLDQ-LABEL: sitofp_2i64_to_4f32_zero: 1295; AVX512VLDQ: # %bb.0: 1296; AVX512VLDQ-NEXT: vcvtqq2ps %xmm0, %xmm0 1297; AVX512VLDQ-NEXT: retq 1298 %cvt = sitofp <2 x i64> %a to <2 x float> 1299 %ext = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1300 ret <4 x float> %ext 1301} 1302 1303define <4 x float> @sitofp_4i64_to_4f32_undef(<2 x i64> %a) { 1304; SSE2-LABEL: sitofp_4i64_to_4f32_undef: 1305; SSE2: # %bb.0: 1306; SSE2-NEXT: movq %xmm0, %rax 1307; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1308; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1309; SSE2-NEXT: movq %xmm0, %rax 1310; SSE2-NEXT: xorps %xmm0, %xmm0 1311; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 1312; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 1313; SSE2-NEXT: xorps %xmm0, %xmm0 1314; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 1315; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,0] 1316; SSE2-NEXT: movaps %xmm1, %xmm0 1317; SSE2-NEXT: retq 1318; 1319; SSE41-LABEL: sitofp_4i64_to_4f32_undef: 1320; SSE41: # %bb.0: 1321; SSE41-NEXT: pextrq $1, %xmm0, %rax 1322; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 1323; SSE41-NEXT: movq %xmm0, %rax 1324; SSE41-NEXT: xorps %xmm0, %xmm0 1325; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 1326; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1327; SSE41-NEXT: xorps %xmm1, %xmm1 1328; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 1329; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1330; SSE41-NEXT: retq 1331; 1332; VEX-LABEL: sitofp_4i64_to_4f32_undef: 1333; VEX: # %bb.0: 1334; VEX-NEXT: vpextrq $1, %xmm0, %rax 1335; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1336; VEX-NEXT: vmovq %xmm0, %rax 1337; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1338; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1339; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 1340; VEX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1341; VEX-NEXT: retq 1342; 1343; AVX512F-LABEL: sitofp_4i64_to_4f32_undef: 1344; AVX512F: # %bb.0: 1345; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 1346; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1347; AVX512F-NEXT: vmovq %xmm0, %rax 1348; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1349; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1350; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 1351; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1352; AVX512F-NEXT: retq 1353; 1354; AVX512VL-LABEL: sitofp_4i64_to_4f32_undef: 1355; AVX512VL: # %bb.0: 1356; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 1357; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1358; AVX512VL-NEXT: vmovq %xmm0, %rax 1359; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1360; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1361; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 1362; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1363; AVX512VL-NEXT: retq 1364; 1365; AVX512DQ-LABEL: sitofp_4i64_to_4f32_undef: 1366; AVX512DQ: # %bb.0: 1367; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 1368; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 1369; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1370; AVX512DQ-NEXT: vzeroupper 1371; AVX512DQ-NEXT: retq 1372; 1373; AVX512VLDQ-LABEL: sitofp_4i64_to_4f32_undef: 1374; AVX512VLDQ: # %bb.0: 1375; AVX512VLDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 1376; AVX512VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0 1377; AVX512VLDQ-NEXT: vzeroupper 1378; AVX512VLDQ-NEXT: retq 1379 %ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 1380 %cvt = sitofp <4 x i64> %ext to <4 x float> 1381 ret <4 x float> %cvt 1382} 1383 1384define <4 x float> @sitofp_4i32_to_4f32(<4 x i32> %a) { 1385; SSE-LABEL: sitofp_4i32_to_4f32: 1386; SSE: # %bb.0: 1387; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 1388; SSE-NEXT: retq 1389; 1390; AVX-LABEL: sitofp_4i32_to_4f32: 1391; AVX: # %bb.0: 1392; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 1393; AVX-NEXT: retq 1394 %cvt = sitofp <4 x i32> %a to <4 x float> 1395 ret <4 x float> %cvt 1396} 1397 1398define <4 x float> @sitofp_4i16_to_4f32(<8 x i16> %a) { 1399; SSE2-LABEL: sitofp_4i16_to_4f32: 1400; SSE2: # %bb.0: 1401; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 1402; SSE2-NEXT: psrad $16, %xmm0 1403; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 1404; SSE2-NEXT: retq 1405; 1406; SSE41-LABEL: sitofp_4i16_to_4f32: 1407; SSE41: # %bb.0: 1408; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 1409; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 1410; SSE41-NEXT: retq 1411; 1412; AVX-LABEL: sitofp_4i16_to_4f32: 1413; AVX: # %bb.0: 1414; AVX-NEXT: vpmovsxwd %xmm0, %xmm0 1415; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 1416; AVX-NEXT: retq 1417 %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1418 %cvt = sitofp <4 x i16> %shuf to <4 x float> 1419 ret <4 x float> %cvt 1420} 1421 1422define <4 x float> @sitofp_8i16_to_4f32(<8 x i16> %a) { 1423; SSE2-LABEL: sitofp_8i16_to_4f32: 1424; SSE2: # %bb.0: 1425; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 1426; SSE2-NEXT: psrad $16, %xmm0 1427; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 1428; SSE2-NEXT: retq 1429; 1430; SSE41-LABEL: sitofp_8i16_to_4f32: 1431; SSE41: # %bb.0: 1432; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 1433; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 1434; SSE41-NEXT: retq 1435; 1436; AVX1-LABEL: sitofp_8i16_to_4f32: 1437; AVX1: # %bb.0: 1438; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 1439; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1440; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 1441; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 1442; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 1443; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1444; AVX1-NEXT: vzeroupper 1445; AVX1-NEXT: retq 1446; 1447; AVX2-LABEL: sitofp_8i16_to_4f32: 1448; AVX2: # %bb.0: 1449; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 1450; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 1451; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1452; AVX2-NEXT: vzeroupper 1453; AVX2-NEXT: retq 1454; 1455; AVX512-LABEL: sitofp_8i16_to_4f32: 1456; AVX512: # %bb.0: 1457; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0 1458; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 1459; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1460; AVX512-NEXT: vzeroupper 1461; AVX512-NEXT: retq 1462 %cvt = sitofp <8 x i16> %a to <8 x float> 1463 %shuf = shufflevector <8 x float> %cvt, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1464 ret <4 x float> %shuf 1465} 1466 1467define <4 x float> @sitofp_4i8_to_4f32(<16 x i8> %a) { 1468; SSE2-LABEL: sitofp_4i8_to_4f32: 1469; SSE2: # %bb.0: 1470; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 1471; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 1472; SSE2-NEXT: psrad $24, %xmm0 1473; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 1474; SSE2-NEXT: retq 1475; 1476; SSE41-LABEL: sitofp_4i8_to_4f32: 1477; SSE41: # %bb.0: 1478; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 1479; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 1480; SSE41-NEXT: retq 1481; 1482; AVX-LABEL: sitofp_4i8_to_4f32: 1483; AVX: # %bb.0: 1484; AVX-NEXT: vpmovsxbd %xmm0, %xmm0 1485; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 1486; AVX-NEXT: retq 1487 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1488 %cvt = sitofp <4 x i8> %shuf to <4 x float> 1489 ret <4 x float> %cvt 1490} 1491 1492define <4 x float> @sitofp_16i8_to_4f32(<16 x i8> %a) { 1493; SSE2-LABEL: sitofp_16i8_to_4f32: 1494; SSE2: # %bb.0: 1495; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 1496; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 1497; SSE2-NEXT: psrad $24, %xmm0 1498; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 1499; SSE2-NEXT: retq 1500; 1501; SSE41-LABEL: sitofp_16i8_to_4f32: 1502; SSE41: # %bb.0: 1503; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 1504; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 1505; SSE41-NEXT: retq 1506; 1507; AVX1-LABEL: sitofp_16i8_to_4f32: 1508; AVX1: # %bb.0: 1509; AVX1-NEXT: vpmovsxbd %xmm0, %xmm1 1510; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 1511; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0 1512; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 1513; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 1514; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1515; AVX1-NEXT: vzeroupper 1516; AVX1-NEXT: retq 1517; 1518; AVX2-LABEL: sitofp_16i8_to_4f32: 1519; AVX2: # %bb.0: 1520; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0 1521; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 1522; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1523; AVX2-NEXT: vzeroupper 1524; AVX2-NEXT: retq 1525; 1526; AVX512-LABEL: sitofp_16i8_to_4f32: 1527; AVX512: # %bb.0: 1528; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 1529; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 1530; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 1531; AVX512-NEXT: vzeroupper 1532; AVX512-NEXT: retq 1533 %cvt = sitofp <16 x i8> %a to <16 x float> 1534 %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1535 ret <4 x float> %shuf 1536} 1537 1538define <4 x float> @sitofp_4i64_to_4f32(<4 x i64> %a) { 1539; SSE2-LABEL: sitofp_4i64_to_4f32: 1540; SSE2: # %bb.0: 1541; SSE2-NEXT: movq %xmm1, %rax 1542; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 1543; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 1544; SSE2-NEXT: movq %xmm1, %rax 1545; SSE2-NEXT: xorps %xmm1, %xmm1 1546; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1547; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] 1548; SSE2-NEXT: movq %xmm0, %rax 1549; SSE2-NEXT: xorps %xmm1, %xmm1 1550; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1551; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1552; SSE2-NEXT: movq %xmm0, %rax 1553; SSE2-NEXT: xorps %xmm0, %xmm0 1554; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 1555; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 1556; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 1557; SSE2-NEXT: movaps %xmm1, %xmm0 1558; SSE2-NEXT: retq 1559; 1560; SSE41-LABEL: sitofp_4i64_to_4f32: 1561; SSE41: # %bb.0: 1562; SSE41-NEXT: pextrq $1, %xmm0, %rax 1563; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 1564; SSE41-NEXT: movq %xmm0, %rax 1565; SSE41-NEXT: xorps %xmm0, %xmm0 1566; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 1567; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 1568; SSE41-NEXT: movq %xmm1, %rax 1569; SSE41-NEXT: xorps %xmm2, %xmm2 1570; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 1571; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 1572; SSE41-NEXT: pextrq $1, %xmm1, %rax 1573; SSE41-NEXT: xorps %xmm1, %xmm1 1574; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 1575; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 1576; SSE41-NEXT: retq 1577; 1578; AVX1-LABEL: sitofp_4i64_to_4f32: 1579; AVX1: # %bb.0: 1580; AVX1-NEXT: vpextrq $1, %xmm0, %rax 1581; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1582; AVX1-NEXT: vmovq %xmm0, %rax 1583; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 1584; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 1585; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 1586; AVX1-NEXT: vmovq %xmm0, %rax 1587; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 1588; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 1589; AVX1-NEXT: vpextrq $1, %xmm0, %rax 1590; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 1591; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 1592; AVX1-NEXT: vzeroupper 1593; AVX1-NEXT: retq 1594; 1595; AVX2-LABEL: sitofp_4i64_to_4f32: 1596; AVX2: # %bb.0: 1597; AVX2-NEXT: vpextrq $1, %xmm0, %rax 1598; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1599; AVX2-NEXT: vmovq %xmm0, %rax 1600; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 1601; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 1602; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 1603; AVX2-NEXT: vmovq %xmm0, %rax 1604; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 1605; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 1606; AVX2-NEXT: vpextrq $1, %xmm0, %rax 1607; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 1608; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 1609; AVX2-NEXT: vzeroupper 1610; AVX2-NEXT: retq 1611; 1612; AVX512F-LABEL: sitofp_4i64_to_4f32: 1613; AVX512F: # %bb.0: 1614; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 1615; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1616; AVX512F-NEXT: vmovq %xmm0, %rax 1617; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 1618; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 1619; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 1620; AVX512F-NEXT: vmovq %xmm0, %rax 1621; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 1622; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 1623; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 1624; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 1625; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 1626; AVX512F-NEXT: vzeroupper 1627; AVX512F-NEXT: retq 1628; 1629; AVX512VL-LABEL: sitofp_4i64_to_4f32: 1630; AVX512VL: # %bb.0: 1631; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 1632; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1633; AVX512VL-NEXT: vmovq %xmm0, %rax 1634; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 1635; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 1636; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm0 1637; AVX512VL-NEXT: vmovq %xmm0, %rax 1638; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 1639; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 1640; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 1641; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 1642; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 1643; AVX512VL-NEXT: vzeroupper 1644; AVX512VL-NEXT: retq 1645; 1646; AVX512DQ-LABEL: sitofp_4i64_to_4f32: 1647; AVX512DQ: # %bb.0: 1648; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 1649; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 1650; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1651; AVX512DQ-NEXT: vzeroupper 1652; AVX512DQ-NEXT: retq 1653; 1654; AVX512VLDQ-LABEL: sitofp_4i64_to_4f32: 1655; AVX512VLDQ: # %bb.0: 1656; AVX512VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0 1657; AVX512VLDQ-NEXT: vzeroupper 1658; AVX512VLDQ-NEXT: retq 1659 %cvt = sitofp <4 x i64> %a to <4 x float> 1660 ret <4 x float> %cvt 1661} 1662 1663define <8 x float> @sitofp_8i32_to_8f32(<8 x i32> %a) { 1664; SSE-LABEL: sitofp_8i32_to_8f32: 1665; SSE: # %bb.0: 1666; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 1667; SSE-NEXT: cvtdq2ps %xmm1, %xmm1 1668; SSE-NEXT: retq 1669; 1670; AVX-LABEL: sitofp_8i32_to_8f32: 1671; AVX: # %bb.0: 1672; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0 1673; AVX-NEXT: retq 1674 %cvt = sitofp <8 x i32> %a to <8 x float> 1675 ret <8 x float> %cvt 1676} 1677 1678define <8 x float> @sitofp_8i16_to_8f32(<8 x i16> %a) { 1679; SSE2-LABEL: sitofp_8i16_to_8f32: 1680; SSE2: # %bb.0: 1681; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 1682; SSE2-NEXT: psrad $16, %xmm1 1683; SSE2-NEXT: cvtdq2ps %xmm1, %xmm2 1684; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7] 1685; SSE2-NEXT: psrad $16, %xmm0 1686; SSE2-NEXT: cvtdq2ps %xmm0, %xmm1 1687; SSE2-NEXT: movaps %xmm2, %xmm0 1688; SSE2-NEXT: retq 1689; 1690; SSE41-LABEL: sitofp_8i16_to_8f32: 1691; SSE41: # %bb.0: 1692; SSE41-NEXT: pmovsxwd %xmm0, %xmm1 1693; SSE41-NEXT: cvtdq2ps %xmm1, %xmm2 1694; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1695; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 1696; SSE41-NEXT: cvtdq2ps %xmm0, %xmm1 1697; SSE41-NEXT: movaps %xmm2, %xmm0 1698; SSE41-NEXT: retq 1699; 1700; AVX1-LABEL: sitofp_8i16_to_8f32: 1701; AVX1: # %bb.0: 1702; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 1703; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 1704; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 1705; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 1706; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 1707; AVX1-NEXT: retq 1708; 1709; AVX2-LABEL: sitofp_8i16_to_8f32: 1710; AVX2: # %bb.0: 1711; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 1712; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 1713; AVX2-NEXT: retq 1714; 1715; AVX512-LABEL: sitofp_8i16_to_8f32: 1716; AVX512: # %bb.0: 1717; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0 1718; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 1719; AVX512-NEXT: retq 1720 %cvt = sitofp <8 x i16> %a to <8 x float> 1721 ret <8 x float> %cvt 1722} 1723 1724define <8 x float> @sitofp_8i8_to_8f32(<16 x i8> %a) { 1725; SSE2-LABEL: sitofp_8i8_to_8f32: 1726; SSE2: # %bb.0: 1727; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 1728; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 1729; SSE2-NEXT: psrad $24, %xmm1 1730; SSE2-NEXT: cvtdq2ps %xmm1, %xmm2 1731; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7] 1732; SSE2-NEXT: psrad $24, %xmm0 1733; SSE2-NEXT: cvtdq2ps %xmm0, %xmm1 1734; SSE2-NEXT: movaps %xmm2, %xmm0 1735; SSE2-NEXT: retq 1736; 1737; SSE41-LABEL: sitofp_8i8_to_8f32: 1738; SSE41: # %bb.0: 1739; SSE41-NEXT: pmovsxbd %xmm0, %xmm1 1740; SSE41-NEXT: cvtdq2ps %xmm1, %xmm2 1741; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 1742; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 1743; SSE41-NEXT: cvtdq2ps %xmm0, %xmm1 1744; SSE41-NEXT: movaps %xmm2, %xmm0 1745; SSE41-NEXT: retq 1746; 1747; AVX1-LABEL: sitofp_8i8_to_8f32: 1748; AVX1: # %bb.0: 1749; AVX1-NEXT: vpmovsxbd %xmm0, %xmm1 1750; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 1751; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0 1752; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 1753; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 1754; AVX1-NEXT: retq 1755; 1756; AVX2-LABEL: sitofp_8i8_to_8f32: 1757; AVX2: # %bb.0: 1758; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0 1759; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 1760; AVX2-NEXT: retq 1761; 1762; AVX512-LABEL: sitofp_8i8_to_8f32: 1763; AVX512: # %bb.0: 1764; AVX512-NEXT: vpmovsxbd %xmm0, %ymm0 1765; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 1766; AVX512-NEXT: retq 1767 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 1768 %cvt = sitofp <8 x i8> %shuf to <8 x float> 1769 ret <8 x float> %cvt 1770} 1771 1772define <8 x float> @sitofp_16i8_to_8f32(<16 x i8> %a) { 1773; SSE2-LABEL: sitofp_16i8_to_8f32: 1774; SSE2: # %bb.0: 1775; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 1776; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 1777; SSE2-NEXT: psrad $24, %xmm1 1778; SSE2-NEXT: cvtdq2ps %xmm1, %xmm2 1779; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7] 1780; SSE2-NEXT: psrad $24, %xmm0 1781; SSE2-NEXT: cvtdq2ps %xmm0, %xmm1 1782; SSE2-NEXT: movaps %xmm2, %xmm0 1783; SSE2-NEXT: retq 1784; 1785; SSE41-LABEL: sitofp_16i8_to_8f32: 1786; SSE41: # %bb.0: 1787; SSE41-NEXT: pmovsxbd %xmm0, %xmm1 1788; SSE41-NEXT: cvtdq2ps %xmm1, %xmm2 1789; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 1790; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 1791; SSE41-NEXT: cvtdq2ps %xmm0, %xmm1 1792; SSE41-NEXT: movaps %xmm2, %xmm0 1793; SSE41-NEXT: retq 1794; 1795; AVX1-LABEL: sitofp_16i8_to_8f32: 1796; AVX1: # %bb.0: 1797; AVX1-NEXT: vpmovsxbd %xmm0, %xmm1 1798; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 1799; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0 1800; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 1801; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 1802; AVX1-NEXT: retq 1803; 1804; AVX2-LABEL: sitofp_16i8_to_8f32: 1805; AVX2: # %bb.0: 1806; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0 1807; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 1808; AVX2-NEXT: retq 1809; 1810; AVX512-LABEL: sitofp_16i8_to_8f32: 1811; AVX512: # %bb.0: 1812; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 1813; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 1814; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 1815; AVX512-NEXT: retq 1816 %cvt = sitofp <16 x i8> %a to <16 x float> 1817 %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 1818 ret <8 x float> %shuf 1819} 1820 1821; 1822; Unsigned Integer to Float 1823; 1824 1825define <4 x float> @uitofp_2i64_to_4f32(<2 x i64> %a) { 1826; SSE2-LABEL: uitofp_2i64_to_4f32: 1827; SSE2: # %bb.0: 1828; SSE2-NEXT: movdqa %xmm0, %xmm1 1829; SSE2-NEXT: movq %xmm0, %rax 1830; SSE2-NEXT: testq %rax, %rax 1831; SSE2-NEXT: js .LBB39_1 1832; SSE2-NEXT: # %bb.2: 1833; SSE2-NEXT: xorps %xmm0, %xmm0 1834; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 1835; SSE2-NEXT: jmp .LBB39_3 1836; SSE2-NEXT: .LBB39_1: 1837; SSE2-NEXT: movq %rax, %rcx 1838; SSE2-NEXT: shrq %rcx 1839; SSE2-NEXT: andl $1, %eax 1840; SSE2-NEXT: orq %rcx, %rax 1841; SSE2-NEXT: xorps %xmm0, %xmm0 1842; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 1843; SSE2-NEXT: addss %xmm0, %xmm0 1844; SSE2-NEXT: .LBB39_3: 1845; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 1846; SSE2-NEXT: movq %xmm1, %rax 1847; SSE2-NEXT: testq %rax, %rax 1848; SSE2-NEXT: js .LBB39_4 1849; SSE2-NEXT: # %bb.5: 1850; SSE2-NEXT: xorps %xmm1, %xmm1 1851; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1852; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 1853; SSE2-NEXT: retq 1854; SSE2-NEXT: .LBB39_4: 1855; SSE2-NEXT: movq %rax, %rcx 1856; SSE2-NEXT: shrq %rcx 1857; SSE2-NEXT: andl $1, %eax 1858; SSE2-NEXT: orq %rcx, %rax 1859; SSE2-NEXT: xorps %xmm1, %xmm1 1860; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1861; SSE2-NEXT: addss %xmm1, %xmm1 1862; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 1863; SSE2-NEXT: retq 1864; 1865; SSE41-LABEL: uitofp_2i64_to_4f32: 1866; SSE41: # %bb.0: 1867; SSE41-NEXT: pextrq $1, %xmm0, %rax 1868; SSE41-NEXT: testq %rax, %rax 1869; SSE41-NEXT: js .LBB39_1 1870; SSE41-NEXT: # %bb.2: 1871; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 1872; SSE41-NEXT: jmp .LBB39_3 1873; SSE41-NEXT: .LBB39_1: 1874; SSE41-NEXT: movq %rax, %rcx 1875; SSE41-NEXT: shrq %rcx 1876; SSE41-NEXT: andl $1, %eax 1877; SSE41-NEXT: orq %rcx, %rax 1878; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 1879; SSE41-NEXT: addss %xmm1, %xmm1 1880; SSE41-NEXT: .LBB39_3: 1881; SSE41-NEXT: movq %xmm0, %rax 1882; SSE41-NEXT: testq %rax, %rax 1883; SSE41-NEXT: js .LBB39_4 1884; SSE41-NEXT: # %bb.5: 1885; SSE41-NEXT: xorps %xmm0, %xmm0 1886; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 1887; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1888; SSE41-NEXT: retq 1889; SSE41-NEXT: .LBB39_4: 1890; SSE41-NEXT: movq %rax, %rcx 1891; SSE41-NEXT: shrq %rcx 1892; SSE41-NEXT: andl $1, %eax 1893; SSE41-NEXT: orq %rcx, %rax 1894; SSE41-NEXT: xorps %xmm0, %xmm0 1895; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 1896; SSE41-NEXT: addss %xmm0, %xmm0 1897; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1898; SSE41-NEXT: retq 1899; 1900; VEX-LABEL: uitofp_2i64_to_4f32: 1901; VEX: # %bb.0: 1902; VEX-NEXT: vpextrq $1, %xmm0, %rax 1903; VEX-NEXT: testq %rax, %rax 1904; VEX-NEXT: js .LBB39_1 1905; VEX-NEXT: # %bb.2: 1906; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1907; VEX-NEXT: jmp .LBB39_3 1908; VEX-NEXT: .LBB39_1: 1909; VEX-NEXT: movq %rax, %rcx 1910; VEX-NEXT: shrq %rcx 1911; VEX-NEXT: andl $1, %eax 1912; VEX-NEXT: orq %rcx, %rax 1913; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 1914; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1 1915; VEX-NEXT: .LBB39_3: 1916; VEX-NEXT: vmovq %xmm0, %rax 1917; VEX-NEXT: testq %rax, %rax 1918; VEX-NEXT: js .LBB39_4 1919; VEX-NEXT: # %bb.5: 1920; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1921; VEX-NEXT: jmp .LBB39_6 1922; VEX-NEXT: .LBB39_4: 1923; VEX-NEXT: movq %rax, %rcx 1924; VEX-NEXT: shrq %rcx 1925; VEX-NEXT: andl $1, %eax 1926; VEX-NEXT: orq %rcx, %rax 1927; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 1928; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0 1929; VEX-NEXT: .LBB39_6: 1930; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1931; VEX-NEXT: testq %rax, %rax 1932; VEX-NEXT: vxorps %xmm1, %xmm1, %xmm1 1933; VEX-NEXT: js .LBB39_8 1934; VEX-NEXT: # %bb.7: 1935; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 1936; VEX-NEXT: .LBB39_8: 1937; VEX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1938; VEX-NEXT: retq 1939; 1940; AVX512F-LABEL: uitofp_2i64_to_4f32: 1941; AVX512F: # %bb.0: 1942; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 1943; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 1944; AVX512F-NEXT: vmovq %xmm0, %rax 1945; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0 1946; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1947; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1 1948; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1949; AVX512F-NEXT: retq 1950; 1951; AVX512VL-LABEL: uitofp_2i64_to_4f32: 1952; AVX512VL: # %bb.0: 1953; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 1954; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 1955; AVX512VL-NEXT: vmovq %xmm0, %rax 1956; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0 1957; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 1958; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1 1959; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 1960; AVX512VL-NEXT: retq 1961; 1962; AVX512DQ-LABEL: uitofp_2i64_to_4f32: 1963; AVX512DQ: # %bb.0: 1964; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 1965; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 1966; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 1967; AVX512DQ-NEXT: vzeroupper 1968; AVX512DQ-NEXT: retq 1969; 1970; AVX512VLDQ-LABEL: uitofp_2i64_to_4f32: 1971; AVX512VLDQ: # %bb.0: 1972; AVX512VLDQ-NEXT: vcvtuqq2ps %xmm0, %xmm0 1973; AVX512VLDQ-NEXT: retq 1974 %cvt = uitofp <2 x i64> %a to <2 x float> 1975 %ext = shufflevector <2 x float> %cvt, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 1976 ret <4 x float> %ext 1977} 1978 1979define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) { 1980; SSE2-LABEL: uitofp_2i64_to_2f32: 1981; SSE2: # %bb.0: 1982; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] 1983; SSE2-NEXT: movq %xmm1, %rax 1984; SSE2-NEXT: testq %rax, %rax 1985; SSE2-NEXT: js .LBB40_1 1986; SSE2-NEXT: # %bb.2: 1987; SSE2-NEXT: xorps %xmm1, %xmm1 1988; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1989; SSE2-NEXT: jmp .LBB40_3 1990; SSE2-NEXT: .LBB40_1: 1991; SSE2-NEXT: movq %rax, %rcx 1992; SSE2-NEXT: shrq %rcx 1993; SSE2-NEXT: andl $1, %eax 1994; SSE2-NEXT: orq %rcx, %rax 1995; SSE2-NEXT: xorps %xmm1, %xmm1 1996; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 1997; SSE2-NEXT: addss %xmm1, %xmm1 1998; SSE2-NEXT: .LBB40_3: 1999; SSE2-NEXT: movq %xmm0, %rax 2000; SSE2-NEXT: testq %rax, %rax 2001; SSE2-NEXT: js .LBB40_4 2002; SSE2-NEXT: # %bb.5: 2003; SSE2-NEXT: xorps %xmm0, %xmm0 2004; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 2005; SSE2-NEXT: jmp .LBB40_6 2006; SSE2-NEXT: .LBB40_4: 2007; SSE2-NEXT: movq %rax, %rcx 2008; SSE2-NEXT: shrq %rcx 2009; SSE2-NEXT: andl $1, %eax 2010; SSE2-NEXT: orq %rcx, %rax 2011; SSE2-NEXT: xorps %xmm0, %xmm0 2012; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 2013; SSE2-NEXT: addss %xmm0, %xmm0 2014; SSE2-NEXT: .LBB40_6: 2015; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 2016; SSE2-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero 2017; SSE2-NEXT: retq 2018; 2019; SSE41-LABEL: uitofp_2i64_to_2f32: 2020; SSE41: # %bb.0: 2021; SSE41-NEXT: movdqa %xmm0, %xmm1 2022; SSE41-NEXT: movq %xmm0, %rax 2023; SSE41-NEXT: testq %rax, %rax 2024; SSE41-NEXT: js .LBB40_1 2025; SSE41-NEXT: # %bb.2: 2026; SSE41-NEXT: xorps %xmm0, %xmm0 2027; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 2028; SSE41-NEXT: jmp .LBB40_3 2029; SSE41-NEXT: .LBB40_1: 2030; SSE41-NEXT: movq %rax, %rcx 2031; SSE41-NEXT: shrq %rcx 2032; SSE41-NEXT: andl $1, %eax 2033; SSE41-NEXT: orq %rcx, %rax 2034; SSE41-NEXT: xorps %xmm0, %xmm0 2035; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 2036; SSE41-NEXT: addss %xmm0, %xmm0 2037; SSE41-NEXT: .LBB40_3: 2038; SSE41-NEXT: pextrq $1, %xmm1, %rax 2039; SSE41-NEXT: testq %rax, %rax 2040; SSE41-NEXT: js .LBB40_4 2041; SSE41-NEXT: # %bb.5: 2042; SSE41-NEXT: xorps %xmm1, %xmm1 2043; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 2044; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero 2045; SSE41-NEXT: retq 2046; SSE41-NEXT: .LBB40_4: 2047; SSE41-NEXT: movq %rax, %rcx 2048; SSE41-NEXT: shrq %rcx 2049; SSE41-NEXT: andl $1, %eax 2050; SSE41-NEXT: orq %rcx, %rax 2051; SSE41-NEXT: xorps %xmm1, %xmm1 2052; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 2053; SSE41-NEXT: addss %xmm1, %xmm1 2054; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero 2055; SSE41-NEXT: retq 2056; 2057; VEX-LABEL: uitofp_2i64_to_2f32: 2058; VEX: # %bb.0: 2059; VEX-NEXT: vmovq %xmm0, %rax 2060; VEX-NEXT: testq %rax, %rax 2061; VEX-NEXT: js .LBB40_1 2062; VEX-NEXT: # %bb.2: 2063; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2064; VEX-NEXT: jmp .LBB40_3 2065; VEX-NEXT: .LBB40_1: 2066; VEX-NEXT: movq %rax, %rcx 2067; VEX-NEXT: shrq %rcx 2068; VEX-NEXT: andl $1, %eax 2069; VEX-NEXT: orq %rcx, %rax 2070; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2071; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1 2072; VEX-NEXT: .LBB40_3: 2073; VEX-NEXT: vpextrq $1, %xmm0, %rax 2074; VEX-NEXT: testq %rax, %rax 2075; VEX-NEXT: js .LBB40_4 2076; VEX-NEXT: # %bb.5: 2077; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 2078; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero 2079; VEX-NEXT: retq 2080; VEX-NEXT: .LBB40_4: 2081; VEX-NEXT: movq %rax, %rcx 2082; VEX-NEXT: shrq %rcx 2083; VEX-NEXT: andl $1, %eax 2084; VEX-NEXT: orq %rcx, %rax 2085; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 2086; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0 2087; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero 2088; VEX-NEXT: retq 2089; 2090; AVX512F-LABEL: uitofp_2i64_to_2f32: 2091; AVX512F: # %bb.0: 2092; AVX512F-NEXT: vmovq %xmm0, %rax 2093; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 2094; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 2095; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0 2096; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero 2097; AVX512F-NEXT: retq 2098; 2099; AVX512VL-LABEL: uitofp_2i64_to_2f32: 2100; AVX512VL: # %bb.0: 2101; AVX512VL-NEXT: vmovq %xmm0, %rax 2102; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 2103; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 2104; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0 2105; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 2106; AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero 2107; AVX512VL-NEXT: retq 2108; 2109; AVX512DQ-LABEL: uitofp_2i64_to_2f32: 2110; AVX512DQ: # %bb.0: 2111; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 2112; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 2113; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero 2114; AVX512DQ-NEXT: vzeroupper 2115; AVX512DQ-NEXT: retq 2116; 2117; AVX512VLDQ-LABEL: uitofp_2i64_to_2f32: 2118; AVX512VLDQ: # %bb.0: 2119; AVX512VLDQ-NEXT: vcvtuqq2ps %xmm0, %xmm0 2120; AVX512VLDQ-NEXT: retq 2121 %cvt = uitofp <2 x i64> %a to <2 x float> 2122 %ext = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2123 ret <4 x float> %ext 2124} 2125 2126define <4 x float> @uitofp_4i64_to_4f32_undef(<2 x i64> %a) { 2127; SSE2-LABEL: uitofp_4i64_to_4f32_undef: 2128; SSE2: # %bb.0: 2129; SSE2-NEXT: movdqa %xmm0, %xmm1 2130; SSE2-NEXT: movq %xmm0, %rax 2131; SSE2-NEXT: testq %rax, %rax 2132; SSE2-NEXT: js .LBB41_1 2133; SSE2-NEXT: # %bb.2: 2134; SSE2-NEXT: xorps %xmm0, %xmm0 2135; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 2136; SSE2-NEXT: jmp .LBB41_3 2137; SSE2-NEXT: .LBB41_1: 2138; SSE2-NEXT: movq %rax, %rcx 2139; SSE2-NEXT: shrq %rcx 2140; SSE2-NEXT: andl $1, %eax 2141; SSE2-NEXT: orq %rcx, %rax 2142; SSE2-NEXT: xorps %xmm0, %xmm0 2143; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 2144; SSE2-NEXT: addss %xmm0, %xmm0 2145; SSE2-NEXT: .LBB41_3: 2146; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 2147; SSE2-NEXT: movq %xmm1, %rax 2148; SSE2-NEXT: testq %rax, %rax 2149; SSE2-NEXT: js .LBB41_4 2150; SSE2-NEXT: # %bb.5: 2151; SSE2-NEXT: xorps %xmm1, %xmm1 2152; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 2153; SSE2-NEXT: jmp .LBB41_6 2154; SSE2-NEXT: .LBB41_4: 2155; SSE2-NEXT: movq %rax, %rcx 2156; SSE2-NEXT: shrq %rcx 2157; SSE2-NEXT: andl $1, %eax 2158; SSE2-NEXT: orq %rcx, %rax 2159; SSE2-NEXT: xorps %xmm1, %xmm1 2160; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 2161; SSE2-NEXT: addss %xmm1, %xmm1 2162; SSE2-NEXT: .LBB41_6: 2163; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 2164; SSE2-NEXT: testq %rax, %rax 2165; SSE2-NEXT: xorps %xmm1, %xmm1 2166; SSE2-NEXT: js .LBB41_8 2167; SSE2-NEXT: # %bb.7: 2168; SSE2-NEXT: xorps %xmm1, %xmm1 2169; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 2170; SSE2-NEXT: .LBB41_8: 2171; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 2172; SSE2-NEXT: retq 2173; 2174; SSE41-LABEL: uitofp_4i64_to_4f32_undef: 2175; SSE41: # %bb.0: 2176; SSE41-NEXT: pextrq $1, %xmm0, %rax 2177; SSE41-NEXT: testq %rax, %rax 2178; SSE41-NEXT: js .LBB41_1 2179; SSE41-NEXT: # %bb.2: 2180; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 2181; SSE41-NEXT: jmp .LBB41_3 2182; SSE41-NEXT: .LBB41_1: 2183; SSE41-NEXT: movq %rax, %rcx 2184; SSE41-NEXT: shrq %rcx 2185; SSE41-NEXT: andl $1, %eax 2186; SSE41-NEXT: orq %rcx, %rax 2187; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 2188; SSE41-NEXT: addss %xmm1, %xmm1 2189; SSE41-NEXT: .LBB41_3: 2190; SSE41-NEXT: movq %xmm0, %rax 2191; SSE41-NEXT: testq %rax, %rax 2192; SSE41-NEXT: js .LBB41_4 2193; SSE41-NEXT: # %bb.5: 2194; SSE41-NEXT: xorps %xmm0, %xmm0 2195; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 2196; SSE41-NEXT: jmp .LBB41_6 2197; SSE41-NEXT: .LBB41_4: 2198; SSE41-NEXT: movq %rax, %rcx 2199; SSE41-NEXT: shrq %rcx 2200; SSE41-NEXT: andl $1, %eax 2201; SSE41-NEXT: orq %rcx, %rax 2202; SSE41-NEXT: xorps %xmm0, %xmm0 2203; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 2204; SSE41-NEXT: addss %xmm0, %xmm0 2205; SSE41-NEXT: .LBB41_6: 2206; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 2207; SSE41-NEXT: testq %rax, %rax 2208; SSE41-NEXT: xorps %xmm1, %xmm1 2209; SSE41-NEXT: js .LBB41_8 2210; SSE41-NEXT: # %bb.7: 2211; SSE41-NEXT: xorps %xmm1, %xmm1 2212; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 2213; SSE41-NEXT: .LBB41_8: 2214; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 2215; SSE41-NEXT: retq 2216; 2217; VEX-LABEL: uitofp_4i64_to_4f32_undef: 2218; VEX: # %bb.0: 2219; VEX-NEXT: vpextrq $1, %xmm0, %rax 2220; VEX-NEXT: testq %rax, %rax 2221; VEX-NEXT: js .LBB41_1 2222; VEX-NEXT: # %bb.2: 2223; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2224; VEX-NEXT: jmp .LBB41_3 2225; VEX-NEXT: .LBB41_1: 2226; VEX-NEXT: movq %rax, %rcx 2227; VEX-NEXT: shrq %rcx 2228; VEX-NEXT: andl $1, %eax 2229; VEX-NEXT: orq %rcx, %rax 2230; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2231; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1 2232; VEX-NEXT: .LBB41_3: 2233; VEX-NEXT: vmovq %xmm0, %rax 2234; VEX-NEXT: testq %rax, %rax 2235; VEX-NEXT: js .LBB41_4 2236; VEX-NEXT: # %bb.5: 2237; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 2238; VEX-NEXT: jmp .LBB41_6 2239; VEX-NEXT: .LBB41_4: 2240; VEX-NEXT: movq %rax, %rcx 2241; VEX-NEXT: shrq %rcx 2242; VEX-NEXT: andl $1, %eax 2243; VEX-NEXT: orq %rcx, %rax 2244; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm0 2245; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0 2246; VEX-NEXT: .LBB41_6: 2247; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 2248; VEX-NEXT: testq %rax, %rax 2249; VEX-NEXT: vxorps %xmm1, %xmm1, %xmm1 2250; VEX-NEXT: js .LBB41_8 2251; VEX-NEXT: # %bb.7: 2252; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm1 2253; VEX-NEXT: .LBB41_8: 2254; VEX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 2255; VEX-NEXT: retq 2256; 2257; AVX512F-LABEL: uitofp_4i64_to_4f32_undef: 2258; AVX512F: # %bb.0: 2259; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 2260; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 2261; AVX512F-NEXT: vmovq %xmm0, %rax 2262; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0 2263; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 2264; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1 2265; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 2266; AVX512F-NEXT: retq 2267; 2268; AVX512VL-LABEL: uitofp_4i64_to_4f32_undef: 2269; AVX512VL: # %bb.0: 2270; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 2271; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 2272; AVX512VL-NEXT: vmovq %xmm0, %rax 2273; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm0 2274; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 2275; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm1 2276; AVX512VL-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0] 2277; AVX512VL-NEXT: retq 2278; 2279; AVX512DQ-LABEL: uitofp_4i64_to_4f32_undef: 2280; AVX512DQ: # %bb.0: 2281; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 2282; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 2283; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 2284; AVX512DQ-NEXT: vzeroupper 2285; AVX512DQ-NEXT: retq 2286; 2287; AVX512VLDQ-LABEL: uitofp_4i64_to_4f32_undef: 2288; AVX512VLDQ: # %bb.0: 2289; AVX512VLDQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 2290; AVX512VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0 2291; AVX512VLDQ-NEXT: vzeroupper 2292; AVX512VLDQ-NEXT: retq 2293 %ext = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> 2294 %cvt = uitofp <4 x i64> %ext to <4 x float> 2295 ret <4 x float> %cvt 2296} 2297 2298define <4 x float> @uitofp_4i32_to_4f32(<4 x i32> %a) { 2299; SSE2-LABEL: uitofp_4i32_to_4f32: 2300; SSE2: # %bb.0: 2301; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] 2302; SSE2-NEXT: pand %xmm0, %xmm1 2303; SSE2-NEXT: por {{.*}}(%rip), %xmm1 2304; SSE2-NEXT: psrld $16, %xmm0 2305; SSE2-NEXT: por {{.*}}(%rip), %xmm0 2306; SSE2-NEXT: addps {{.*}}(%rip), %xmm0 2307; SSE2-NEXT: addps %xmm1, %xmm0 2308; SSE2-NEXT: retq 2309; 2310; SSE41-LABEL: uitofp_4i32_to_4f32: 2311; SSE41: # %bb.0: 2312; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200] 2313; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 2314; SSE41-NEXT: psrld $16, %xmm0 2315; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 2316; SSE41-NEXT: addps {{.*}}(%rip), %xmm0 2317; SSE41-NEXT: addps %xmm1, %xmm0 2318; SSE41-NEXT: retq 2319; 2320; AVX1-LABEL: uitofp_4i32_to_4f32: 2321; AVX1: # %bb.0: 2322; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 2323; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0 2324; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 2325; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0 2326; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0 2327; AVX1-NEXT: retq 2328; 2329; AVX2-LABEL: uitofp_4i32_to_4f32: 2330; AVX2: # %bb.0: 2331; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200] 2332; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 2333; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0 2334; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1392508928,1392508928,1392508928,1392508928] 2335; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] 2336; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 2337; AVX2-NEXT: vaddps %xmm2, %xmm0, %xmm0 2338; AVX2-NEXT: vaddps %xmm0, %xmm1, %xmm0 2339; AVX2-NEXT: retq 2340; 2341; AVX512F-LABEL: uitofp_4i32_to_4f32: 2342; AVX512F: # %bb.0: 2343; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 2344; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 2345; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 2346; AVX512F-NEXT: vzeroupper 2347; AVX512F-NEXT: retq 2348; 2349; AVX512VL-LABEL: uitofp_4i32_to_4f32: 2350; AVX512VL: # %bb.0: 2351; AVX512VL-NEXT: vcvtudq2ps %xmm0, %xmm0 2352; AVX512VL-NEXT: retq 2353; 2354; AVX512DQ-LABEL: uitofp_4i32_to_4f32: 2355; AVX512DQ: # %bb.0: 2356; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 2357; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 2358; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 2359; AVX512DQ-NEXT: vzeroupper 2360; AVX512DQ-NEXT: retq 2361; 2362; AVX512VLDQ-LABEL: uitofp_4i32_to_4f32: 2363; AVX512VLDQ: # %bb.0: 2364; AVX512VLDQ-NEXT: vcvtudq2ps %xmm0, %xmm0 2365; AVX512VLDQ-NEXT: retq 2366 %cvt = uitofp <4 x i32> %a to <4 x float> 2367 ret <4 x float> %cvt 2368} 2369 2370define <4 x float> @uitofp_4i16_to_4f32(<8 x i16> %a) { 2371; SSE2-LABEL: uitofp_4i16_to_4f32: 2372; SSE2: # %bb.0: 2373; SSE2-NEXT: pxor %xmm1, %xmm1 2374; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 2375; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 2376; SSE2-NEXT: retq 2377; 2378; SSE41-LABEL: uitofp_4i16_to_4f32: 2379; SSE41: # %bb.0: 2380; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 2381; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 2382; SSE41-NEXT: retq 2383; 2384; AVX-LABEL: uitofp_4i16_to_4f32: 2385; AVX: # %bb.0: 2386; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 2387; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 2388; AVX-NEXT: retq 2389 %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2390 %cvt = uitofp <4 x i16> %shuf to <4 x float> 2391 ret <4 x float> %cvt 2392} 2393 2394define <4 x float> @uitofp_8i16_to_4f32(<8 x i16> %a) { 2395; SSE2-LABEL: uitofp_8i16_to_4f32: 2396; SSE2: # %bb.0: 2397; SSE2-NEXT: pxor %xmm1, %xmm1 2398; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 2399; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 2400; SSE2-NEXT: retq 2401; 2402; SSE41-LABEL: uitofp_8i16_to_4f32: 2403; SSE41: # %bb.0: 2404; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 2405; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 2406; SSE41-NEXT: retq 2407; 2408; AVX1-LABEL: uitofp_8i16_to_4f32: 2409; AVX1: # %bb.0: 2410; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 2411; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2412; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 2413; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 2414; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 2415; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 2416; AVX1-NEXT: vzeroupper 2417; AVX1-NEXT: retq 2418; 2419; AVX2-LABEL: uitofp_8i16_to_4f32: 2420; AVX2: # %bb.0: 2421; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 2422; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 2423; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 2424; AVX2-NEXT: vzeroupper 2425; AVX2-NEXT: retq 2426; 2427; AVX512-LABEL: uitofp_8i16_to_4f32: 2428; AVX512: # %bb.0: 2429; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 2430; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 2431; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 2432; AVX512-NEXT: vzeroupper 2433; AVX512-NEXT: retq 2434 %cvt = uitofp <8 x i16> %a to <8 x float> 2435 %shuf = shufflevector <8 x float> %cvt, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2436 ret <4 x float> %shuf 2437} 2438 2439define <4 x float> @uitofp_4i8_to_4f32(<16 x i8> %a) { 2440; SSE2-LABEL: uitofp_4i8_to_4f32: 2441; SSE2: # %bb.0: 2442; SSE2-NEXT: pxor %xmm1, %xmm1 2443; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2444; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 2445; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 2446; SSE2-NEXT: retq 2447; 2448; SSE41-LABEL: uitofp_4i8_to_4f32: 2449; SSE41: # %bb.0: 2450; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2451; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 2452; SSE41-NEXT: retq 2453; 2454; AVX-LABEL: uitofp_4i8_to_4f32: 2455; AVX: # %bb.0: 2456; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2457; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 2458; AVX-NEXT: retq 2459 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2460 %cvt = uitofp <4 x i8> %shuf to <4 x float> 2461 ret <4 x float> %cvt 2462} 2463 2464define <4 x float> @uitofp_16i8_to_4f32(<16 x i8> %a) { 2465; SSE2-LABEL: uitofp_16i8_to_4f32: 2466; SSE2: # %bb.0: 2467; SSE2-NEXT: pxor %xmm1, %xmm1 2468; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2469; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 2470; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 2471; SSE2-NEXT: retq 2472; 2473; SSE41-LABEL: uitofp_16i8_to_4f32: 2474; SSE41: # %bb.0: 2475; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2476; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 2477; SSE41-NEXT: retq 2478; 2479; AVX1-LABEL: uitofp_16i8_to_4f32: 2480; AVX1: # %bb.0: 2481; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2482; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 2483; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2484; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 2485; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 2486; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 2487; AVX1-NEXT: vzeroupper 2488; AVX1-NEXT: retq 2489; 2490; AVX2-LABEL: uitofp_16i8_to_4f32: 2491; AVX2: # %bb.0: 2492; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero 2493; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 2494; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 2495; AVX2-NEXT: vzeroupper 2496; AVX2-NEXT: retq 2497; 2498; AVX512-LABEL: uitofp_16i8_to_4f32: 2499; AVX512: # %bb.0: 2500; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero 2501; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 2502; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 2503; AVX512-NEXT: vzeroupper 2504; AVX512-NEXT: retq 2505 %cvt = uitofp <16 x i8> %a to <16 x float> 2506 %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2507 ret <4 x float> %shuf 2508} 2509 2510define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) { 2511; SSE2-LABEL: uitofp_4i64_to_4f32: 2512; SSE2: # %bb.0: 2513; SSE2-NEXT: movq %xmm1, %rax 2514; SSE2-NEXT: testq %rax, %rax 2515; SSE2-NEXT: js .LBB47_1 2516; SSE2-NEXT: # %bb.2: 2517; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 2518; SSE2-NEXT: jmp .LBB47_3 2519; SSE2-NEXT: .LBB47_1: 2520; SSE2-NEXT: movq %rax, %rcx 2521; SSE2-NEXT: shrq %rcx 2522; SSE2-NEXT: andl $1, %eax 2523; SSE2-NEXT: orq %rcx, %rax 2524; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 2525; SSE2-NEXT: addss %xmm2, %xmm2 2526; SSE2-NEXT: .LBB47_3: 2527; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 2528; SSE2-NEXT: movq %xmm1, %rax 2529; SSE2-NEXT: testq %rax, %rax 2530; SSE2-NEXT: js .LBB47_4 2531; SSE2-NEXT: # %bb.5: 2532; SSE2-NEXT: cvtsi2ssq %rax, %xmm3 2533; SSE2-NEXT: jmp .LBB47_6 2534; SSE2-NEXT: .LBB47_4: 2535; SSE2-NEXT: movq %rax, %rcx 2536; SSE2-NEXT: shrq %rcx 2537; SSE2-NEXT: andl $1, %eax 2538; SSE2-NEXT: orq %rcx, %rax 2539; SSE2-NEXT: cvtsi2ssq %rax, %xmm3 2540; SSE2-NEXT: addss %xmm3, %xmm3 2541; SSE2-NEXT: .LBB47_6: 2542; SSE2-NEXT: movq %xmm0, %rax 2543; SSE2-NEXT: testq %rax, %rax 2544; SSE2-NEXT: js .LBB47_7 2545; SSE2-NEXT: # %bb.8: 2546; SSE2-NEXT: xorps %xmm1, %xmm1 2547; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 2548; SSE2-NEXT: jmp .LBB47_9 2549; SSE2-NEXT: .LBB47_7: 2550; SSE2-NEXT: movq %rax, %rcx 2551; SSE2-NEXT: shrq %rcx 2552; SSE2-NEXT: andl $1, %eax 2553; SSE2-NEXT: orq %rcx, %rax 2554; SSE2-NEXT: xorps %xmm1, %xmm1 2555; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 2556; SSE2-NEXT: addss %xmm1, %xmm1 2557; SSE2-NEXT: .LBB47_9: 2558; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] 2559; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 2560; SSE2-NEXT: movq %xmm0, %rax 2561; SSE2-NEXT: testq %rax, %rax 2562; SSE2-NEXT: js .LBB47_10 2563; SSE2-NEXT: # %bb.11: 2564; SSE2-NEXT: xorps %xmm0, %xmm0 2565; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 2566; SSE2-NEXT: jmp .LBB47_12 2567; SSE2-NEXT: .LBB47_10: 2568; SSE2-NEXT: movq %rax, %rcx 2569; SSE2-NEXT: shrq %rcx 2570; SSE2-NEXT: andl $1, %eax 2571; SSE2-NEXT: orq %rcx, %rax 2572; SSE2-NEXT: xorps %xmm0, %xmm0 2573; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 2574; SSE2-NEXT: addss %xmm0, %xmm0 2575; SSE2-NEXT: .LBB47_12: 2576; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 2577; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 2578; SSE2-NEXT: movaps %xmm1, %xmm0 2579; SSE2-NEXT: retq 2580; 2581; SSE41-LABEL: uitofp_4i64_to_4f32: 2582; SSE41: # %bb.0: 2583; SSE41-NEXT: pextrq $1, %xmm0, %rax 2584; SSE41-NEXT: testq %rax, %rax 2585; SSE41-NEXT: js .LBB47_1 2586; SSE41-NEXT: # %bb.2: 2587; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 2588; SSE41-NEXT: jmp .LBB47_3 2589; SSE41-NEXT: .LBB47_1: 2590; SSE41-NEXT: movq %rax, %rcx 2591; SSE41-NEXT: shrq %rcx 2592; SSE41-NEXT: andl $1, %eax 2593; SSE41-NEXT: orq %rcx, %rax 2594; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 2595; SSE41-NEXT: addss %xmm2, %xmm2 2596; SSE41-NEXT: .LBB47_3: 2597; SSE41-NEXT: movq %xmm0, %rax 2598; SSE41-NEXT: testq %rax, %rax 2599; SSE41-NEXT: js .LBB47_4 2600; SSE41-NEXT: # %bb.5: 2601; SSE41-NEXT: xorps %xmm0, %xmm0 2602; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 2603; SSE41-NEXT: jmp .LBB47_6 2604; SSE41-NEXT: .LBB47_4: 2605; SSE41-NEXT: movq %rax, %rcx 2606; SSE41-NEXT: shrq %rcx 2607; SSE41-NEXT: andl $1, %eax 2608; SSE41-NEXT: orq %rcx, %rax 2609; SSE41-NEXT: xorps %xmm0, %xmm0 2610; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 2611; SSE41-NEXT: addss %xmm0, %xmm0 2612; SSE41-NEXT: .LBB47_6: 2613; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 2614; SSE41-NEXT: movq %xmm1, %rax 2615; SSE41-NEXT: testq %rax, %rax 2616; SSE41-NEXT: js .LBB47_7 2617; SSE41-NEXT: # %bb.8: 2618; SSE41-NEXT: xorps %xmm2, %xmm2 2619; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 2620; SSE41-NEXT: jmp .LBB47_9 2621; SSE41-NEXT: .LBB47_7: 2622; SSE41-NEXT: movq %rax, %rcx 2623; SSE41-NEXT: shrq %rcx 2624; SSE41-NEXT: andl $1, %eax 2625; SSE41-NEXT: orq %rcx, %rax 2626; SSE41-NEXT: xorps %xmm2, %xmm2 2627; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 2628; SSE41-NEXT: addss %xmm2, %xmm2 2629; SSE41-NEXT: .LBB47_9: 2630; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 2631; SSE41-NEXT: pextrq $1, %xmm1, %rax 2632; SSE41-NEXT: testq %rax, %rax 2633; SSE41-NEXT: js .LBB47_10 2634; SSE41-NEXT: # %bb.11: 2635; SSE41-NEXT: xorps %xmm1, %xmm1 2636; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 2637; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 2638; SSE41-NEXT: retq 2639; SSE41-NEXT: .LBB47_10: 2640; SSE41-NEXT: movq %rax, %rcx 2641; SSE41-NEXT: shrq %rcx 2642; SSE41-NEXT: andl $1, %eax 2643; SSE41-NEXT: orq %rcx, %rax 2644; SSE41-NEXT: xorps %xmm1, %xmm1 2645; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 2646; SSE41-NEXT: addss %xmm1, %xmm1 2647; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 2648; SSE41-NEXT: retq 2649; 2650; AVX1-LABEL: uitofp_4i64_to_4f32: 2651; AVX1: # %bb.0: 2652; AVX1-NEXT: vpextrq $1, %xmm0, %rax 2653; AVX1-NEXT: testq %rax, %rax 2654; AVX1-NEXT: js .LBB47_1 2655; AVX1-NEXT: # %bb.2: 2656; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2657; AVX1-NEXT: jmp .LBB47_3 2658; AVX1-NEXT: .LBB47_1: 2659; AVX1-NEXT: movq %rax, %rcx 2660; AVX1-NEXT: shrq %rcx 2661; AVX1-NEXT: andl $1, %eax 2662; AVX1-NEXT: orq %rcx, %rax 2663; AVX1-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2664; AVX1-NEXT: vaddss %xmm1, %xmm1, %xmm1 2665; AVX1-NEXT: .LBB47_3: 2666; AVX1-NEXT: vmovq %xmm0, %rax 2667; AVX1-NEXT: testq %rax, %rax 2668; AVX1-NEXT: js .LBB47_4 2669; AVX1-NEXT: # %bb.5: 2670; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 2671; AVX1-NEXT: jmp .LBB47_6 2672; AVX1-NEXT: .LBB47_4: 2673; AVX1-NEXT: movq %rax, %rcx 2674; AVX1-NEXT: shrq %rcx 2675; AVX1-NEXT: andl $1, %eax 2676; AVX1-NEXT: orq %rcx, %rax 2677; AVX1-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 2678; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 2679; AVX1-NEXT: .LBB47_6: 2680; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 2681; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 2682; AVX1-NEXT: vmovq %xmm0, %rax 2683; AVX1-NEXT: testq %rax, %rax 2684; AVX1-NEXT: js .LBB47_7 2685; AVX1-NEXT: # %bb.8: 2686; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 2687; AVX1-NEXT: jmp .LBB47_9 2688; AVX1-NEXT: .LBB47_7: 2689; AVX1-NEXT: movq %rax, %rcx 2690; AVX1-NEXT: shrq %rcx 2691; AVX1-NEXT: andl $1, %eax 2692; AVX1-NEXT: orq %rcx, %rax 2693; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 2694; AVX1-NEXT: vaddss %xmm2, %xmm2, %xmm2 2695; AVX1-NEXT: .LBB47_9: 2696; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 2697; AVX1-NEXT: vpextrq $1, %xmm0, %rax 2698; AVX1-NEXT: testq %rax, %rax 2699; AVX1-NEXT: js .LBB47_10 2700; AVX1-NEXT: # %bb.11: 2701; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 2702; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 2703; AVX1-NEXT: vzeroupper 2704; AVX1-NEXT: retq 2705; AVX1-NEXT: .LBB47_10: 2706; AVX1-NEXT: movq %rax, %rcx 2707; AVX1-NEXT: shrq %rcx 2708; AVX1-NEXT: andl $1, %eax 2709; AVX1-NEXT: orq %rcx, %rax 2710; AVX1-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 2711; AVX1-NEXT: vaddss %xmm0, %xmm0, %xmm0 2712; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 2713; AVX1-NEXT: vzeroupper 2714; AVX1-NEXT: retq 2715; 2716; AVX2-LABEL: uitofp_4i64_to_4f32: 2717; AVX2: # %bb.0: 2718; AVX2-NEXT: vpextrq $1, %xmm0, %rax 2719; AVX2-NEXT: testq %rax, %rax 2720; AVX2-NEXT: js .LBB47_1 2721; AVX2-NEXT: # %bb.2: 2722; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2723; AVX2-NEXT: jmp .LBB47_3 2724; AVX2-NEXT: .LBB47_1: 2725; AVX2-NEXT: movq %rax, %rcx 2726; AVX2-NEXT: shrq %rcx 2727; AVX2-NEXT: andl $1, %eax 2728; AVX2-NEXT: orq %rcx, %rax 2729; AVX2-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 2730; AVX2-NEXT: vaddss %xmm1, %xmm1, %xmm1 2731; AVX2-NEXT: .LBB47_3: 2732; AVX2-NEXT: vmovq %xmm0, %rax 2733; AVX2-NEXT: testq %rax, %rax 2734; AVX2-NEXT: js .LBB47_4 2735; AVX2-NEXT: # %bb.5: 2736; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 2737; AVX2-NEXT: jmp .LBB47_6 2738; AVX2-NEXT: .LBB47_4: 2739; AVX2-NEXT: movq %rax, %rcx 2740; AVX2-NEXT: shrq %rcx 2741; AVX2-NEXT: andl $1, %eax 2742; AVX2-NEXT: orq %rcx, %rax 2743; AVX2-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 2744; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 2745; AVX2-NEXT: .LBB47_6: 2746; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 2747; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 2748; AVX2-NEXT: vmovq %xmm0, %rax 2749; AVX2-NEXT: testq %rax, %rax 2750; AVX2-NEXT: js .LBB47_7 2751; AVX2-NEXT: # %bb.8: 2752; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 2753; AVX2-NEXT: jmp .LBB47_9 2754; AVX2-NEXT: .LBB47_7: 2755; AVX2-NEXT: movq %rax, %rcx 2756; AVX2-NEXT: shrq %rcx 2757; AVX2-NEXT: andl $1, %eax 2758; AVX2-NEXT: orq %rcx, %rax 2759; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 2760; AVX2-NEXT: vaddss %xmm2, %xmm2, %xmm2 2761; AVX2-NEXT: .LBB47_9: 2762; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 2763; AVX2-NEXT: vpextrq $1, %xmm0, %rax 2764; AVX2-NEXT: testq %rax, %rax 2765; AVX2-NEXT: js .LBB47_10 2766; AVX2-NEXT: # %bb.11: 2767; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 2768; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 2769; AVX2-NEXT: vzeroupper 2770; AVX2-NEXT: retq 2771; AVX2-NEXT: .LBB47_10: 2772; AVX2-NEXT: movq %rax, %rcx 2773; AVX2-NEXT: shrq %rcx 2774; AVX2-NEXT: andl $1, %eax 2775; AVX2-NEXT: orq %rcx, %rax 2776; AVX2-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 2777; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0 2778; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 2779; AVX2-NEXT: vzeroupper 2780; AVX2-NEXT: retq 2781; 2782; AVX512F-LABEL: uitofp_4i64_to_4f32: 2783; AVX512F: # %bb.0: 2784; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 2785; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 2786; AVX512F-NEXT: vmovq %xmm0, %rax 2787; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2 2788; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 2789; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 2790; AVX512F-NEXT: vmovq %xmm0, %rax 2791; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2 2792; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 2793; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 2794; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0 2795; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 2796; AVX512F-NEXT: vzeroupper 2797; AVX512F-NEXT: retq 2798; 2799; AVX512VL-LABEL: uitofp_4i64_to_4f32: 2800; AVX512VL: # %bb.0: 2801; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 2802; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm1, %xmm1 2803; AVX512VL-NEXT: vmovq %xmm0, %rax 2804; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2 2805; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 2806; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm0 2807; AVX512VL-NEXT: vmovq %xmm0, %rax 2808; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2 2809; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 2810; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 2811; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0 2812; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 2813; AVX512VL-NEXT: vzeroupper 2814; AVX512VL-NEXT: retq 2815; 2816; AVX512DQ-LABEL: uitofp_4i64_to_4f32: 2817; AVX512DQ: # %bb.0: 2818; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 2819; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 2820; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 2821; AVX512DQ-NEXT: vzeroupper 2822; AVX512DQ-NEXT: retq 2823; 2824; AVX512VLDQ-LABEL: uitofp_4i64_to_4f32: 2825; AVX512VLDQ: # %bb.0: 2826; AVX512VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0 2827; AVX512VLDQ-NEXT: vzeroupper 2828; AVX512VLDQ-NEXT: retq 2829 %cvt = uitofp <4 x i64> %a to <4 x float> 2830 ret <4 x float> %cvt 2831} 2832 2833define <8 x float> @uitofp_8i32_to_8f32(<8 x i32> %a) { 2834; SSE2-LABEL: uitofp_8i32_to_8f32: 2835; SSE2: # %bb.0: 2836; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535] 2837; SSE2-NEXT: movdqa %xmm0, %xmm3 2838; SSE2-NEXT: pand %xmm2, %xmm3 2839; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1258291200,1258291200,1258291200,1258291200] 2840; SSE2-NEXT: por %xmm4, %xmm3 2841; SSE2-NEXT: psrld $16, %xmm0 2842; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1392508928,1392508928,1392508928,1392508928] 2843; SSE2-NEXT: por %xmm5, %xmm0 2844; SSE2-NEXT: movaps {{.*#+}} xmm6 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 2845; SSE2-NEXT: addps %xmm6, %xmm0 2846; SSE2-NEXT: addps %xmm3, %xmm0 2847; SSE2-NEXT: pand %xmm1, %xmm2 2848; SSE2-NEXT: por %xmm4, %xmm2 2849; SSE2-NEXT: psrld $16, %xmm1 2850; SSE2-NEXT: por %xmm5, %xmm1 2851; SSE2-NEXT: addps %xmm6, %xmm1 2852; SSE2-NEXT: addps %xmm2, %xmm1 2853; SSE2-NEXT: retq 2854; 2855; SSE41-LABEL: uitofp_8i32_to_8f32: 2856; SSE41: # %bb.0: 2857; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [1258291200,1258291200,1258291200,1258291200] 2858; SSE41-NEXT: movdqa %xmm0, %xmm3 2859; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm2[1],xmm3[2],xmm2[3],xmm3[4],xmm2[5],xmm3[6],xmm2[7] 2860; SSE41-NEXT: psrld $16, %xmm0 2861; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [1392508928,1392508928,1392508928,1392508928] 2862; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm4[1],xmm0[2],xmm4[3],xmm0[4],xmm4[5],xmm0[6],xmm4[7] 2863; SSE41-NEXT: movaps {{.*#+}} xmm5 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 2864; SSE41-NEXT: addps %xmm5, %xmm0 2865; SSE41-NEXT: addps %xmm3, %xmm0 2866; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7] 2867; SSE41-NEXT: psrld $16, %xmm1 2868; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],xmm4[1],xmm1[2],xmm4[3],xmm1[4],xmm4[5],xmm1[6],xmm4[7] 2869; SSE41-NEXT: addps %xmm5, %xmm1 2870; SSE41-NEXT: addps %xmm2, %xmm1 2871; SSE41-NEXT: retq 2872; 2873; AVX1-LABEL: uitofp_8i32_to_8f32: 2874; AVX1: # %bb.0: 2875; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1 2876; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 2877; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2 2878; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 2879; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 2880; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1 2881; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 2882; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 2883; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0 2884; AVX1-NEXT: retq 2885; 2886; AVX2-LABEL: uitofp_8i32_to_8f32: 2887; AVX2: # %bb.0: 2888; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] 2889; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] 2890; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 2891; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] 2892; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] 2893; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 2894; AVX2-NEXT: vaddps %ymm2, %ymm0, %ymm0 2895; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0 2896; AVX2-NEXT: retq 2897; 2898; AVX512F-LABEL: uitofp_8i32_to_8f32: 2899; AVX512F: # %bb.0: 2900; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 2901; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 2902; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 2903; AVX512F-NEXT: retq 2904; 2905; AVX512VL-LABEL: uitofp_8i32_to_8f32: 2906; AVX512VL: # %bb.0: 2907; AVX512VL-NEXT: vcvtudq2ps %ymm0, %ymm0 2908; AVX512VL-NEXT: retq 2909; 2910; AVX512DQ-LABEL: uitofp_8i32_to_8f32: 2911; AVX512DQ: # %bb.0: 2912; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 2913; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 2914; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 2915; AVX512DQ-NEXT: retq 2916; 2917; AVX512VLDQ-LABEL: uitofp_8i32_to_8f32: 2918; AVX512VLDQ: # %bb.0: 2919; AVX512VLDQ-NEXT: vcvtudq2ps %ymm0, %ymm0 2920; AVX512VLDQ-NEXT: retq 2921 %cvt = uitofp <8 x i32> %a to <8 x float> 2922 ret <8 x float> %cvt 2923} 2924 2925define <8 x float> @uitofp_8i16_to_8f32(<8 x i16> %a) { 2926; SSE2-LABEL: uitofp_8i16_to_8f32: 2927; SSE2: # %bb.0: 2928; SSE2-NEXT: pxor %xmm1, %xmm1 2929; SSE2-NEXT: movdqa %xmm0, %xmm2 2930; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 2931; SSE2-NEXT: cvtdq2ps %xmm2, %xmm2 2932; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2933; SSE2-NEXT: cvtdq2ps %xmm0, %xmm1 2934; SSE2-NEXT: movaps %xmm2, %xmm0 2935; SSE2-NEXT: retq 2936; 2937; SSE41-LABEL: uitofp_8i16_to_8f32: 2938; SSE41: # %bb.0: 2939; SSE41-NEXT: pxor %xmm1, %xmm1 2940; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 2941; SSE41-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2942; SSE41-NEXT: cvtdq2ps %xmm0, %xmm1 2943; SSE41-NEXT: cvtdq2ps %xmm2, %xmm0 2944; SSE41-NEXT: retq 2945; 2946; AVX1-LABEL: uitofp_8i16_to_8f32: 2947; AVX1: # %bb.0: 2948; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 2949; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2950; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 2951; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 2952; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 2953; AVX1-NEXT: retq 2954; 2955; AVX2-LABEL: uitofp_8i16_to_8f32: 2956; AVX2: # %bb.0: 2957; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 2958; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 2959; AVX2-NEXT: retq 2960; 2961; AVX512-LABEL: uitofp_8i16_to_8f32: 2962; AVX512: # %bb.0: 2963; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero 2964; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 2965; AVX512-NEXT: retq 2966 %cvt = uitofp <8 x i16> %a to <8 x float> 2967 ret <8 x float> %cvt 2968} 2969 2970define <8 x float> @uitofp_8i8_to_8f32(<16 x i8> %a) { 2971; SSE2-LABEL: uitofp_8i8_to_8f32: 2972; SSE2: # %bb.0: 2973; SSE2-NEXT: pxor %xmm1, %xmm1 2974; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2975; SSE2-NEXT: movdqa %xmm0, %xmm2 2976; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 2977; SSE2-NEXT: cvtdq2ps %xmm2, %xmm2 2978; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 2979; SSE2-NEXT: cvtdq2ps %xmm0, %xmm1 2980; SSE2-NEXT: movaps %xmm2, %xmm0 2981; SSE2-NEXT: retq 2982; 2983; SSE41-LABEL: uitofp_8i8_to_8f32: 2984; SSE41: # %bb.0: 2985; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2986; SSE41-NEXT: cvtdq2ps %xmm1, %xmm2 2987; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 2988; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2989; SSE41-NEXT: cvtdq2ps %xmm0, %xmm1 2990; SSE41-NEXT: movaps %xmm2, %xmm0 2991; SSE41-NEXT: retq 2992; 2993; AVX1-LABEL: uitofp_8i8_to_8f32: 2994; AVX1: # %bb.0: 2995; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2996; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 2997; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 2998; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 2999; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 3000; AVX1-NEXT: retq 3001; 3002; AVX2-LABEL: uitofp_8i8_to_8f32: 3003; AVX2: # %bb.0: 3004; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero 3005; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 3006; AVX2-NEXT: retq 3007; 3008; AVX512-LABEL: uitofp_8i8_to_8f32: 3009; AVX512: # %bb.0: 3010; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero 3011; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 3012; AVX512-NEXT: retq 3013 %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 3014 %cvt = uitofp <8 x i8> %shuf to <8 x float> 3015 ret <8 x float> %cvt 3016} 3017 3018define <8 x float> @uitofp_16i8_to_8f32(<16 x i8> %a) { 3019; SSE2-LABEL: uitofp_16i8_to_8f32: 3020; SSE2: # %bb.0: 3021; SSE2-NEXT: pxor %xmm1, %xmm1 3022; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 3023; SSE2-NEXT: movdqa %xmm0, %xmm2 3024; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 3025; SSE2-NEXT: cvtdq2ps %xmm2, %xmm2 3026; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 3027; SSE2-NEXT: cvtdq2ps %xmm0, %xmm1 3028; SSE2-NEXT: movaps %xmm2, %xmm0 3029; SSE2-NEXT: retq 3030; 3031; SSE41-LABEL: uitofp_16i8_to_8f32: 3032; SSE41: # %bb.0: 3033; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 3034; SSE41-NEXT: cvtdq2ps %xmm1, %xmm2 3035; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 3036; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 3037; SSE41-NEXT: cvtdq2ps %xmm0, %xmm1 3038; SSE41-NEXT: movaps %xmm2, %xmm0 3039; SSE41-NEXT: retq 3040; 3041; AVX1-LABEL: uitofp_16i8_to_8f32: 3042; AVX1: # %bb.0: 3043; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 3044; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 3045; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 3046; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 3047; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 3048; AVX1-NEXT: retq 3049; 3050; AVX2-LABEL: uitofp_16i8_to_8f32: 3051; AVX2: # %bb.0: 3052; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero 3053; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 3054; AVX2-NEXT: retq 3055; 3056; AVX512-LABEL: uitofp_16i8_to_8f32: 3057; AVX512: # %bb.0: 3058; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero 3059; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 3060; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 3061; AVX512-NEXT: retq 3062 %cvt = uitofp <16 x i8> %a to <16 x float> 3063 %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 3064 ret <8 x float> %shuf 3065} 3066 3067; 3068; Load Signed Integer to Double 3069; 3070 3071define <2 x double> @sitofp_load_2i64_to_2f64(<2 x i64> *%a) { 3072; SSE2-LABEL: sitofp_load_2i64_to_2f64: 3073; SSE2: # %bb.0: 3074; SSE2-NEXT: movdqa (%rdi), %xmm1 3075; SSE2-NEXT: movq %xmm1, %rax 3076; SSE2-NEXT: cvtsi2sdq %rax, %xmm0 3077; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3078; SSE2-NEXT: movq %xmm1, %rax 3079; SSE2-NEXT: xorps %xmm1, %xmm1 3080; SSE2-NEXT: cvtsi2sdq %rax, %xmm1 3081; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 3082; SSE2-NEXT: retq 3083; 3084; SSE41-LABEL: sitofp_load_2i64_to_2f64: 3085; SSE41: # %bb.0: 3086; SSE41-NEXT: movdqa (%rdi), %xmm0 3087; SSE41-NEXT: pextrq $1, %xmm0, %rax 3088; SSE41-NEXT: cvtsi2sdq %rax, %xmm1 3089; SSE41-NEXT: movq %xmm0, %rax 3090; SSE41-NEXT: xorps %xmm0, %xmm0 3091; SSE41-NEXT: cvtsi2sdq %rax, %xmm0 3092; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 3093; SSE41-NEXT: retq 3094; 3095; VEX-LABEL: sitofp_load_2i64_to_2f64: 3096; VEX: # %bb.0: 3097; VEX-NEXT: vmovdqa (%rdi), %xmm0 3098; VEX-NEXT: vpextrq $1, %xmm0, %rax 3099; VEX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1 3100; VEX-NEXT: vmovq %xmm0, %rax 3101; VEX-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0 3102; VEX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 3103; VEX-NEXT: retq 3104; 3105; AVX512F-LABEL: sitofp_load_2i64_to_2f64: 3106; AVX512F: # %bb.0: 3107; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 3108; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 3109; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1 3110; AVX512F-NEXT: vmovq %xmm0, %rax 3111; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0 3112; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 3113; AVX512F-NEXT: retq 3114; 3115; AVX512VL-LABEL: sitofp_load_2i64_to_2f64: 3116; AVX512VL: # %bb.0: 3117; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 3118; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 3119; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm1 3120; AVX512VL-NEXT: vmovq %xmm0, %rax 3121; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm0 3122; AVX512VL-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 3123; AVX512VL-NEXT: retq 3124; 3125; AVX512DQ-LABEL: sitofp_load_2i64_to_2f64: 3126; AVX512DQ: # %bb.0: 3127; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 3128; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 3129; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 3130; AVX512DQ-NEXT: vzeroupper 3131; AVX512DQ-NEXT: retq 3132; 3133; AVX512VLDQ-LABEL: sitofp_load_2i64_to_2f64: 3134; AVX512VLDQ: # %bb.0: 3135; AVX512VLDQ-NEXT: vcvtqq2pd (%rdi), %xmm0 3136; AVX512VLDQ-NEXT: retq 3137 %ld = load <2 x i64>, <2 x i64> *%a 3138 %cvt = sitofp <2 x i64> %ld to <2 x double> 3139 ret <2 x double> %cvt 3140} 3141 3142define <2 x double> @sitofp_load_2i32_to_2f64(<2 x i32> *%a) { 3143; SSE-LABEL: sitofp_load_2i32_to_2f64: 3144; SSE: # %bb.0: 3145; SSE-NEXT: cvtdq2pd (%rdi), %xmm0 3146; SSE-NEXT: retq 3147; 3148; AVX-LABEL: sitofp_load_2i32_to_2f64: 3149; AVX: # %bb.0: 3150; AVX-NEXT: vcvtdq2pd (%rdi), %xmm0 3151; AVX-NEXT: retq 3152 %ld = load <2 x i32>, <2 x i32> *%a 3153 %cvt = sitofp <2 x i32> %ld to <2 x double> 3154 ret <2 x double> %cvt 3155} 3156 3157define <2 x double> @sitofp_load_2i16_to_2f64(<2 x i16> *%a) { 3158; SSE2-LABEL: sitofp_load_2i16_to_2f64: 3159; SSE2: # %bb.0: 3160; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 3161; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7] 3162; SSE2-NEXT: psrad $16, %xmm0 3163; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 3164; SSE2-NEXT: retq 3165; 3166; SSE41-LABEL: sitofp_load_2i16_to_2f64: 3167; SSE41: # %bb.0: 3168; SSE41-NEXT: pmovsxwq (%rdi), %xmm0 3169; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] 3170; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 3171; SSE41-NEXT: retq 3172; 3173; AVX-LABEL: sitofp_load_2i16_to_2f64: 3174; AVX: # %bb.0: 3175; AVX-NEXT: vpmovsxwq (%rdi), %xmm0 3176; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] 3177; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 3178; AVX-NEXT: retq 3179 %ld = load <2 x i16>, <2 x i16> *%a 3180 %cvt = sitofp <2 x i16> %ld to <2 x double> 3181 ret <2 x double> %cvt 3182} 3183 3184define <2 x double> @sitofp_load_2i8_to_2f64(<2 x i8> *%a) { 3185; SSE2-LABEL: sitofp_load_2i8_to_2f64: 3186; SSE2: # %bb.0: 3187; SSE2-NEXT: movzwl (%rdi), %eax 3188; SSE2-NEXT: movd %eax, %xmm0 3189; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 3190; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 3191; SSE2-NEXT: psrad $24, %xmm0 3192; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 3193; SSE2-NEXT: retq 3194; 3195; SSE41-LABEL: sitofp_load_2i8_to_2f64: 3196; SSE41: # %bb.0: 3197; SSE41-NEXT: pmovsxbq (%rdi), %xmm0 3198; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] 3199; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 3200; SSE41-NEXT: retq 3201; 3202; AVX-LABEL: sitofp_load_2i8_to_2f64: 3203; AVX: # %bb.0: 3204; AVX-NEXT: vpmovsxbq (%rdi), %xmm0 3205; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] 3206; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 3207; AVX-NEXT: retq 3208 %ld = load <2 x i8>, <2 x i8> *%a 3209 %cvt = sitofp <2 x i8> %ld to <2 x double> 3210 ret <2 x double> %cvt 3211} 3212 3213define <4 x double> @sitofp_load_4i64_to_4f64(<4 x i64> *%a) { 3214; SSE2-LABEL: sitofp_load_4i64_to_4f64: 3215; SSE2: # %bb.0: 3216; SSE2-NEXT: movdqa (%rdi), %xmm1 3217; SSE2-NEXT: movdqa 16(%rdi), %xmm2 3218; SSE2-NEXT: movq %xmm1, %rax 3219; SSE2-NEXT: cvtsi2sdq %rax, %xmm0 3220; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3221; SSE2-NEXT: movq %xmm1, %rax 3222; SSE2-NEXT: xorps %xmm1, %xmm1 3223; SSE2-NEXT: cvtsi2sdq %rax, %xmm1 3224; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 3225; SSE2-NEXT: movq %xmm2, %rax 3226; SSE2-NEXT: xorps %xmm1, %xmm1 3227; SSE2-NEXT: cvtsi2sdq %rax, %xmm1 3228; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] 3229; SSE2-NEXT: movq %xmm2, %rax 3230; SSE2-NEXT: xorps %xmm2, %xmm2 3231; SSE2-NEXT: cvtsi2sdq %rax, %xmm2 3232; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 3233; SSE2-NEXT: retq 3234; 3235; SSE41-LABEL: sitofp_load_4i64_to_4f64: 3236; SSE41: # %bb.0: 3237; SSE41-NEXT: movdqa (%rdi), %xmm0 3238; SSE41-NEXT: movdqa 16(%rdi), %xmm1 3239; SSE41-NEXT: pextrq $1, %xmm0, %rax 3240; SSE41-NEXT: cvtsi2sdq %rax, %xmm2 3241; SSE41-NEXT: movq %xmm0, %rax 3242; SSE41-NEXT: xorps %xmm0, %xmm0 3243; SSE41-NEXT: cvtsi2sdq %rax, %xmm0 3244; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 3245; SSE41-NEXT: pextrq $1, %xmm1, %rax 3246; SSE41-NEXT: xorps %xmm2, %xmm2 3247; SSE41-NEXT: cvtsi2sdq %rax, %xmm2 3248; SSE41-NEXT: movq %xmm1, %rax 3249; SSE41-NEXT: xorps %xmm1, %xmm1 3250; SSE41-NEXT: cvtsi2sdq %rax, %xmm1 3251; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 3252; SSE41-NEXT: retq 3253; 3254; VEX-LABEL: sitofp_load_4i64_to_4f64: 3255; VEX: # %bb.0: 3256; VEX-NEXT: vmovdqa (%rdi), %xmm0 3257; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 3258; VEX-NEXT: vpextrq $1, %xmm1, %rax 3259; VEX-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 3260; VEX-NEXT: vmovq %xmm1, %rax 3261; VEX-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1 3262; VEX-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 3263; VEX-NEXT: vpextrq $1, %xmm0, %rax 3264; VEX-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2 3265; VEX-NEXT: vmovq %xmm0, %rax 3266; VEX-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0 3267; VEX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 3268; VEX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 3269; VEX-NEXT: retq 3270; 3271; AVX512F-LABEL: sitofp_load_4i64_to_4f64: 3272; AVX512F: # %bb.0: 3273; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 3274; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 3275; AVX512F-NEXT: vpextrq $1, %xmm1, %rax 3276; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 3277; AVX512F-NEXT: vmovq %xmm1, %rax 3278; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1 3279; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 3280; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 3281; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2 3282; AVX512F-NEXT: vmovq %xmm0, %rax 3283; AVX512F-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0 3284; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 3285; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 3286; AVX512F-NEXT: retq 3287; 3288; AVX512VL-LABEL: sitofp_load_4i64_to_4f64: 3289; AVX512VL: # %bb.0: 3290; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 3291; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 3292; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax 3293; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm2, %xmm2 3294; AVX512VL-NEXT: vmovq %xmm1, %rax 3295; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm1 3296; AVX512VL-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0] 3297; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 3298; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm2 3299; AVX512VL-NEXT: vmovq %xmm0, %rax 3300; AVX512VL-NEXT: vcvtsi2sdq %rax, %xmm3, %xmm0 3301; AVX512VL-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 3302; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 3303; AVX512VL-NEXT: retq 3304; 3305; AVX512DQ-LABEL: sitofp_load_4i64_to_4f64: 3306; AVX512DQ: # %bb.0: 3307; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 3308; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 3309; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 3310; AVX512DQ-NEXT: retq 3311; 3312; AVX512VLDQ-LABEL: sitofp_load_4i64_to_4f64: 3313; AVX512VLDQ: # %bb.0: 3314; AVX512VLDQ-NEXT: vcvtqq2pd (%rdi), %ymm0 3315; AVX512VLDQ-NEXT: retq 3316 %ld = load <4 x i64>, <4 x i64> *%a 3317 %cvt = sitofp <4 x i64> %ld to <4 x double> 3318 ret <4 x double> %cvt 3319} 3320 3321define <4 x double> @sitofp_load_4i32_to_4f64(<4 x i32> *%a) { 3322; SSE-LABEL: sitofp_load_4i32_to_4f64: 3323; SSE: # %bb.0: 3324; SSE-NEXT: movdqa (%rdi), %xmm1 3325; SSE-NEXT: cvtdq2pd %xmm1, %xmm0 3326; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3327; SSE-NEXT: cvtdq2pd %xmm1, %xmm1 3328; SSE-NEXT: retq 3329; 3330; AVX-LABEL: sitofp_load_4i32_to_4f64: 3331; AVX: # %bb.0: 3332; AVX-NEXT: vcvtdq2pd (%rdi), %ymm0 3333; AVX-NEXT: retq 3334 %ld = load <4 x i32>, <4 x i32> *%a 3335 %cvt = sitofp <4 x i32> %ld to <4 x double> 3336 ret <4 x double> %cvt 3337} 3338 3339define <4 x double> @sitofp_load_4i16_to_4f64(<4 x i16> *%a) { 3340; SSE2-LABEL: sitofp_load_4i16_to_4f64: 3341; SSE2: # %bb.0: 3342; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 3343; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 3344; SSE2-NEXT: psrad $16, %xmm1 3345; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 3346; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3347; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 3348; SSE2-NEXT: retq 3349; 3350; SSE41-LABEL: sitofp_load_4i16_to_4f64: 3351; SSE41: # %bb.0: 3352; SSE41-NEXT: pmovsxwd (%rdi), %xmm1 3353; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 3354; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3355; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 3356; SSE41-NEXT: retq 3357; 3358; AVX-LABEL: sitofp_load_4i16_to_4f64: 3359; AVX: # %bb.0: 3360; AVX-NEXT: vpmovsxwd (%rdi), %xmm0 3361; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 3362; AVX-NEXT: retq 3363 %ld = load <4 x i16>, <4 x i16> *%a 3364 %cvt = sitofp <4 x i16> %ld to <4 x double> 3365 ret <4 x double> %cvt 3366} 3367 3368define <4 x double> @sitofp_load_4i8_to_4f64(<4 x i8> *%a) { 3369; SSE2-LABEL: sitofp_load_4i8_to_4f64: 3370; SSE2: # %bb.0: 3371; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 3372; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 3373; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 3374; SSE2-NEXT: psrad $24, %xmm1 3375; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 3376; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3377; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 3378; SSE2-NEXT: retq 3379; 3380; SSE41-LABEL: sitofp_load_4i8_to_4f64: 3381; SSE41: # %bb.0: 3382; SSE41-NEXT: pmovsxbd (%rdi), %xmm1 3383; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 3384; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3385; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 3386; SSE41-NEXT: retq 3387; 3388; AVX-LABEL: sitofp_load_4i8_to_4f64: 3389; AVX: # %bb.0: 3390; AVX-NEXT: vpmovsxbd (%rdi), %xmm0 3391; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 3392; AVX-NEXT: retq 3393 %ld = load <4 x i8>, <4 x i8> *%a 3394 %cvt = sitofp <4 x i8> %ld to <4 x double> 3395 ret <4 x double> %cvt 3396} 3397 3398; 3399; Load Unsigned Integer to Double 3400; 3401 3402define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) { 3403; SSE2-LABEL: uitofp_load_2i64_to_2f64: 3404; SSE2: # %bb.0: 3405; SSE2-NEXT: movdqa (%rdi), %xmm0 3406; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295] 3407; SSE2-NEXT: pand %xmm0, %xmm1 3408; SSE2-NEXT: por {{.*}}(%rip), %xmm1 3409; SSE2-NEXT: psrlq $32, %xmm0 3410; SSE2-NEXT: por {{.*}}(%rip), %xmm0 3411; SSE2-NEXT: subpd {{.*}}(%rip), %xmm0 3412; SSE2-NEXT: addpd %xmm1, %xmm0 3413; SSE2-NEXT: retq 3414; 3415; SSE41-LABEL: uitofp_load_2i64_to_2f64: 3416; SSE41: # %bb.0: 3417; SSE41-NEXT: movdqa (%rdi), %xmm0 3418; SSE41-NEXT: pxor %xmm1, %xmm1 3419; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 3420; SSE41-NEXT: por {{.*}}(%rip), %xmm1 3421; SSE41-NEXT: psrlq $32, %xmm0 3422; SSE41-NEXT: por {{.*}}(%rip), %xmm0 3423; SSE41-NEXT: subpd {{.*}}(%rip), %xmm0 3424; SSE41-NEXT: addpd %xmm1, %xmm0 3425; SSE41-NEXT: retq 3426; 3427; AVX1-LABEL: uitofp_load_2i64_to_2f64: 3428; AVX1: # %bb.0: 3429; AVX1-NEXT: vmovdqa (%rdi), %xmm0 3430; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 3431; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 3432; AVX1-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 3433; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0 3434; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 3435; AVX1-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 3436; AVX1-NEXT: vaddpd %xmm0, %xmm1, %xmm0 3437; AVX1-NEXT: retq 3438; 3439; AVX2-LABEL: uitofp_load_2i64_to_2f64: 3440; AVX2: # %bb.0: 3441; AVX2-NEXT: vmovdqa (%rdi), %xmm0 3442; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 3443; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 3444; AVX2-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 3445; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0 3446; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 3447; AVX2-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 3448; AVX2-NEXT: vaddpd %xmm0, %xmm1, %xmm0 3449; AVX2-NEXT: retq 3450; 3451; AVX512F-LABEL: uitofp_load_2i64_to_2f64: 3452; AVX512F: # %bb.0: 3453; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 3454; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 3455; AVX512F-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 3456; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 3457; AVX512F-NEXT: vpsrlq $32, %xmm0, %xmm0 3458; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 3459; AVX512F-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 3460; AVX512F-NEXT: vaddpd %xmm0, %xmm1, %xmm0 3461; AVX512F-NEXT: retq 3462; 3463; AVX512VL-LABEL: uitofp_load_2i64_to_2f64: 3464; AVX512VL: # %bb.0: 3465; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 3466; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1 3467; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm1, %xmm1 3468; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0 3469; AVX512VL-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 3470; AVX512VL-NEXT: vsubpd {{.*}}(%rip), %xmm0, %xmm0 3471; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0 3472; AVX512VL-NEXT: retq 3473; 3474; AVX512DQ-LABEL: uitofp_load_2i64_to_2f64: 3475; AVX512DQ: # %bb.0: 3476; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 3477; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 3478; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 3479; AVX512DQ-NEXT: vzeroupper 3480; AVX512DQ-NEXT: retq 3481; 3482; AVX512VLDQ-LABEL: uitofp_load_2i64_to_2f64: 3483; AVX512VLDQ: # %bb.0: 3484; AVX512VLDQ-NEXT: vcvtuqq2pd (%rdi), %xmm0 3485; AVX512VLDQ-NEXT: retq 3486 %ld = load <2 x i64>, <2 x i64> *%a 3487 %cvt = uitofp <2 x i64> %ld to <2 x double> 3488 ret <2 x double> %cvt 3489} 3490 3491define <2 x double> @uitofp_load_2i32_to_2f64(<2 x i32> *%a) { 3492; SSE2-LABEL: uitofp_load_2i32_to_2f64: 3493; SSE2: # %bb.0: 3494; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 3495; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0] 3496; SSE2-NEXT: pand %xmm0, %xmm1 3497; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 3498; SSE2-NEXT: psrld $16, %xmm0 3499; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 3500; SSE2-NEXT: mulpd {{.*}}(%rip), %xmm0 3501; SSE2-NEXT: addpd %xmm1, %xmm0 3502; SSE2-NEXT: retq 3503; 3504; SSE41-LABEL: uitofp_load_2i32_to_2f64: 3505; SSE41: # %bb.0: 3506; SSE41-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 3507; SSE41-NEXT: pxor %xmm1, %xmm1 3508; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7] 3509; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 3510; SSE41-NEXT: psrld $16, %xmm0 3511; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 3512; SSE41-NEXT: mulpd {{.*}}(%rip), %xmm0 3513; SSE41-NEXT: addpd %xmm1, %xmm0 3514; SSE41-NEXT: retq 3515; 3516; VEX-LABEL: uitofp_load_2i32_to_2f64: 3517; VEX: # %bb.0: 3518; VEX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero 3519; VEX-NEXT: vpxor %xmm1, %xmm1, %xmm1 3520; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7] 3521; VEX-NEXT: vcvtdq2pd %xmm1, %xmm1 3522; VEX-NEXT: vpsrld $16, %xmm0, %xmm0 3523; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0 3524; VEX-NEXT: vmulpd {{.*}}(%rip), %xmm0, %xmm0 3525; VEX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 3526; VEX-NEXT: retq 3527; 3528; AVX512F-LABEL: uitofp_load_2i32_to_2f64: 3529; AVX512F: # %bb.0: 3530; AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero 3531; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 3532; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 3533; AVX512F-NEXT: vzeroupper 3534; AVX512F-NEXT: retq 3535; 3536; AVX512VL-LABEL: uitofp_load_2i32_to_2f64: 3537; AVX512VL: # %bb.0: 3538; AVX512VL-NEXT: vcvtudq2pd (%rdi), %xmm0 3539; AVX512VL-NEXT: retq 3540; 3541; AVX512DQ-LABEL: uitofp_load_2i32_to_2f64: 3542; AVX512DQ: # %bb.0: 3543; AVX512DQ-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero 3544; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 3545; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 3546; AVX512DQ-NEXT: vzeroupper 3547; AVX512DQ-NEXT: retq 3548; 3549; AVX512VLDQ-LABEL: uitofp_load_2i32_to_2f64: 3550; AVX512VLDQ: # %bb.0: 3551; AVX512VLDQ-NEXT: vcvtudq2pd (%rdi), %xmm0 3552; AVX512VLDQ-NEXT: retq 3553 %ld = load <2 x i32>, <2 x i32> *%a 3554 %cvt = uitofp <2 x i32> %ld to <2 x double> 3555 ret <2 x double> %cvt 3556} 3557 3558define <2 x double> @uitofp_load_2i16_to_2f64(<2 x i16> *%a) { 3559; SSE2-LABEL: uitofp_load_2i16_to_2f64: 3560; SSE2: # %bb.0: 3561; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 3562; SSE2-NEXT: pxor %xmm1, %xmm1 3563; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 3564; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 3565; SSE2-NEXT: retq 3566; 3567; SSE41-LABEL: uitofp_load_2i16_to_2f64: 3568; SSE41: # %bb.0: 3569; SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 3570; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 3571; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 3572; SSE41-NEXT: retq 3573; 3574; AVX-LABEL: uitofp_load_2i16_to_2f64: 3575; AVX: # %bb.0: 3576; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero 3577; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 3578; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 3579; AVX-NEXT: retq 3580 %ld = load <2 x i16>, <2 x i16> *%a 3581 %cvt = uitofp <2 x i16> %ld to <2 x double> 3582 ret <2 x double> %cvt 3583} 3584 3585define <2 x double> @uitofp_load_2i8_to_2f64(<2 x i8> *%a) { 3586; SSE2-LABEL: uitofp_load_2i8_to_2f64: 3587; SSE2: # %bb.0: 3588; SSE2-NEXT: movzwl (%rdi), %eax 3589; SSE2-NEXT: movd %eax, %xmm0 3590; SSE2-NEXT: pxor %xmm1, %xmm1 3591; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 3592; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 3593; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 3594; SSE2-NEXT: retq 3595; 3596; SSE41-LABEL: uitofp_load_2i8_to_2f64: 3597; SSE41: # %bb.0: 3598; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero 3599; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] 3600; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 3601; SSE41-NEXT: retq 3602; 3603; AVX-LABEL: uitofp_load_2i8_to_2f64: 3604; AVX: # %bb.0: 3605; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero 3606; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] 3607; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 3608; AVX-NEXT: retq 3609 %ld = load <2 x i8>, <2 x i8> *%a 3610 %cvt = uitofp <2 x i8> %ld to <2 x double> 3611 ret <2 x double> %cvt 3612} 3613 3614define <4 x double> @uitofp_load_4i64_to_4f64(<4 x i64> *%a) { 3615; SSE2-LABEL: uitofp_load_4i64_to_4f64: 3616; SSE2: # %bb.0: 3617; SSE2-NEXT: movdqa (%rdi), %xmm0 3618; SSE2-NEXT: movdqa 16(%rdi), %xmm1 3619; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295] 3620; SSE2-NEXT: movdqa %xmm0, %xmm3 3621; SSE2-NEXT: pand %xmm2, %xmm3 3622; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200] 3623; SSE2-NEXT: por %xmm4, %xmm3 3624; SSE2-NEXT: psrlq $32, %xmm0 3625; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072] 3626; SSE2-NEXT: por %xmm5, %xmm0 3627; SSE2-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25] 3628; SSE2-NEXT: subpd %xmm6, %xmm0 3629; SSE2-NEXT: addpd %xmm3, %xmm0 3630; SSE2-NEXT: pand %xmm1, %xmm2 3631; SSE2-NEXT: por %xmm4, %xmm2 3632; SSE2-NEXT: psrlq $32, %xmm1 3633; SSE2-NEXT: por %xmm5, %xmm1 3634; SSE2-NEXT: subpd %xmm6, %xmm1 3635; SSE2-NEXT: addpd %xmm2, %xmm1 3636; SSE2-NEXT: retq 3637; 3638; SSE41-LABEL: uitofp_load_4i64_to_4f64: 3639; SSE41: # %bb.0: 3640; SSE41-NEXT: movdqa (%rdi), %xmm0 3641; SSE41-NEXT: movdqa 16(%rdi), %xmm1 3642; SSE41-NEXT: pxor %xmm2, %xmm2 3643; SSE41-NEXT: movdqa %xmm0, %xmm3 3644; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] 3645; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200] 3646; SSE41-NEXT: por %xmm4, %xmm3 3647; SSE41-NEXT: psrlq $32, %xmm0 3648; SSE41-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072] 3649; SSE41-NEXT: por %xmm5, %xmm0 3650; SSE41-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25] 3651; SSE41-NEXT: subpd %xmm6, %xmm0 3652; SSE41-NEXT: addpd %xmm3, %xmm0 3653; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] 3654; SSE41-NEXT: por %xmm4, %xmm2 3655; SSE41-NEXT: psrlq $32, %xmm1 3656; SSE41-NEXT: por %xmm5, %xmm1 3657; SSE41-NEXT: subpd %xmm6, %xmm1 3658; SSE41-NEXT: addpd %xmm2, %xmm1 3659; SSE41-NEXT: retq 3660; 3661; AVX1-LABEL: uitofp_load_4i64_to_4f64: 3662; AVX1: # %bb.0: 3663; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 3664; AVX1-NEXT: vblendps {{.*#+}} ymm0 = mem[0],ymm0[1],mem[2],ymm0[3],mem[4],ymm0[5],mem[6],ymm0[7] 3665; AVX1-NEXT: vorps {{.*}}(%rip), %ymm0, %ymm0 3666; AVX1-NEXT: vmovdqa (%rdi), %xmm1 3667; AVX1-NEXT: vmovdqa 16(%rdi), %xmm2 3668; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm1 3669; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm2 3670; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 3671; AVX1-NEXT: vorpd {{.*}}(%rip), %ymm1, %ymm1 3672; AVX1-NEXT: vsubpd {{.*}}(%rip), %ymm1, %ymm1 3673; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0 3674; AVX1-NEXT: retq 3675; 3676; AVX2-LABEL: uitofp_load_4i64_to_4f64: 3677; AVX2: # %bb.0: 3678; AVX2-NEXT: vmovdqa (%rdi), %ymm0 3679; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 3680; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 3681; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200] 3682; AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1 3683; AVX2-NEXT: vpsrlq $32, %ymm0, %ymm0 3684; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4985484787499139072,4985484787499139072,4985484787499139072,4985484787499139072] 3685; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0 3686; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25] 3687; AVX2-NEXT: vsubpd %ymm2, %ymm0, %ymm0 3688; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0 3689; AVX2-NEXT: retq 3690; 3691; AVX512F-LABEL: uitofp_load_4i64_to_4f64: 3692; AVX512F: # %bb.0: 3693; AVX512F-NEXT: vmovdqa (%rdi), %ymm0 3694; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 3695; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 3696; AVX512F-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4841369599423283200,4841369599423283200,4841369599423283200,4841369599423283200] 3697; AVX512F-NEXT: vpor %ymm2, %ymm1, %ymm1 3698; AVX512F-NEXT: vpsrlq $32, %ymm0, %ymm0 3699; AVX512F-NEXT: vpbroadcastq {{.*#+}} ymm2 = [4985484787499139072,4985484787499139072,4985484787499139072,4985484787499139072] 3700; AVX512F-NEXT: vpor %ymm2, %ymm0, %ymm0 3701; AVX512F-NEXT: vbroadcastsd {{.*#+}} ymm2 = [1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25,1.9342813118337666E+25] 3702; AVX512F-NEXT: vsubpd %ymm2, %ymm0, %ymm0 3703; AVX512F-NEXT: vaddpd %ymm0, %ymm1, %ymm0 3704; AVX512F-NEXT: retq 3705; 3706; AVX512VL-LABEL: uitofp_load_4i64_to_4f64: 3707; AVX512VL: # %bb.0: 3708; AVX512VL-NEXT: vmovdqa (%rdi), %ymm0 3709; AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm0, %ymm1 3710; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm1, %ymm1 3711; AVX512VL-NEXT: vpsrlq $32, %ymm0, %ymm0 3712; AVX512VL-NEXT: vporq {{.*}}(%rip){1to4}, %ymm0, %ymm0 3713; AVX512VL-NEXT: vsubpd {{.*}}(%rip){1to4}, %ymm0, %ymm0 3714; AVX512VL-NEXT: vaddpd %ymm0, %ymm1, %ymm0 3715; AVX512VL-NEXT: retq 3716; 3717; AVX512DQ-LABEL: uitofp_load_4i64_to_4f64: 3718; AVX512DQ: # %bb.0: 3719; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 3720; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 3721; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 3722; AVX512DQ-NEXT: retq 3723; 3724; AVX512VLDQ-LABEL: uitofp_load_4i64_to_4f64: 3725; AVX512VLDQ: # %bb.0: 3726; AVX512VLDQ-NEXT: vcvtuqq2pd (%rdi), %ymm0 3727; AVX512VLDQ-NEXT: retq 3728 %ld = load <4 x i64>, <4 x i64> *%a 3729 %cvt = uitofp <4 x i64> %ld to <4 x double> 3730 ret <4 x double> %cvt 3731} 3732 3733define <4 x double> @uitofp_load_4i32_to_4f64(<4 x i32> *%a) { 3734; SSE2-LABEL: uitofp_load_4i32_to_4f64: 3735; SSE2: # %bb.0: 3736; SSE2-NEXT: movdqa (%rdi), %xmm0 3737; SSE2-NEXT: movdqa %xmm0, %xmm1 3738; SSE2-NEXT: psrld $16, %xmm1 3739; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 3740; SSE2-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4] 3741; SSE2-NEXT: mulpd %xmm2, %xmm1 3742; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65535,0,65535,0,0,0,0,0] 3743; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1] 3744; SSE2-NEXT: pand %xmm3, %xmm0 3745; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 3746; SSE2-NEXT: addpd %xmm1, %xmm0 3747; SSE2-NEXT: movdqa %xmm4, %xmm1 3748; SSE2-NEXT: psrld $16, %xmm1 3749; SSE2-NEXT: cvtdq2pd %xmm1, %xmm5 3750; SSE2-NEXT: mulpd %xmm2, %xmm5 3751; SSE2-NEXT: pand %xmm3, %xmm4 3752; SSE2-NEXT: cvtdq2pd %xmm4, %xmm1 3753; SSE2-NEXT: addpd %xmm5, %xmm1 3754; SSE2-NEXT: retq 3755; 3756; SSE41-LABEL: uitofp_load_4i32_to_4f64: 3757; SSE41: # %bb.0: 3758; SSE41-NEXT: movdqa (%rdi), %xmm0 3759; SSE41-NEXT: movdqa %xmm0, %xmm1 3760; SSE41-NEXT: psrld $16, %xmm1 3761; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 3762; SSE41-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4] 3763; SSE41-NEXT: mulpd %xmm2, %xmm1 3764; SSE41-NEXT: pxor %xmm3, %xmm3 3765; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1] 3766; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4,5,6,7] 3767; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 3768; SSE41-NEXT: addpd %xmm1, %xmm0 3769; SSE41-NEXT: movdqa %xmm4, %xmm1 3770; SSE41-NEXT: psrld $16, %xmm1 3771; SSE41-NEXT: cvtdq2pd %xmm1, %xmm5 3772; SSE41-NEXT: mulpd %xmm2, %xmm5 3773; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm3[1],xmm4[2],xmm3[3],xmm4[4,5,6,7] 3774; SSE41-NEXT: cvtdq2pd %xmm4, %xmm1 3775; SSE41-NEXT: addpd %xmm5, %xmm1 3776; SSE41-NEXT: retq 3777; 3778; AVX1-LABEL: uitofp_load_4i32_to_4f64: 3779; AVX1: # %bb.0: 3780; AVX1-NEXT: vmovdqa (%rdi), %xmm0 3781; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 3782; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 3783; AVX1-NEXT: vcvtdq2pd %xmm1, %ymm1 3784; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0 3785; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 3786; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0 3787; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0 3788; AVX1-NEXT: retq 3789; 3790; AVX2-LABEL: uitofp_load_4i32_to_4f64: 3791; AVX2: # %bb.0: 3792; AVX2-NEXT: vmovdqa (%rdi), %xmm0 3793; AVX2-NEXT: vpsrld $16, %xmm0, %xmm1 3794; AVX2-NEXT: vcvtdq2pd %xmm1, %ymm1 3795; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4] 3796; AVX2-NEXT: vmulpd %ymm2, %ymm1, %ymm1 3797; AVX2-NEXT: vxorpd %xmm2, %xmm2, %xmm2 3798; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] 3799; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 3800; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0 3801; AVX2-NEXT: retq 3802; 3803; AVX512F-LABEL: uitofp_load_4i32_to_4f64: 3804; AVX512F: # %bb.0: 3805; AVX512F-NEXT: vmovaps (%rdi), %xmm0 3806; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 3807; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 3808; AVX512F-NEXT: retq 3809; 3810; AVX512VL-LABEL: uitofp_load_4i32_to_4f64: 3811; AVX512VL: # %bb.0: 3812; AVX512VL-NEXT: vcvtudq2pd (%rdi), %ymm0 3813; AVX512VL-NEXT: retq 3814; 3815; AVX512DQ-LABEL: uitofp_load_4i32_to_4f64: 3816; AVX512DQ: # %bb.0: 3817; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 3818; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 3819; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 3820; AVX512DQ-NEXT: retq 3821; 3822; AVX512VLDQ-LABEL: uitofp_load_4i32_to_4f64: 3823; AVX512VLDQ: # %bb.0: 3824; AVX512VLDQ-NEXT: vcvtudq2pd (%rdi), %ymm0 3825; AVX512VLDQ-NEXT: retq 3826 %ld = load <4 x i32>, <4 x i32> *%a 3827 %cvt = uitofp <4 x i32> %ld to <4 x double> 3828 ret <4 x double> %cvt 3829} 3830 3831define <4 x double> @uitofp_load_4i16_to_4f64(<4 x i16> *%a) { 3832; SSE2-LABEL: uitofp_load_4i16_to_4f64: 3833; SSE2: # %bb.0: 3834; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero 3835; SSE2-NEXT: pxor %xmm0, %xmm0 3836; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 3837; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 3838; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3839; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 3840; SSE2-NEXT: retq 3841; 3842; SSE41-LABEL: uitofp_load_4i16_to_4f64: 3843; SSE41: # %bb.0: 3844; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 3845; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 3846; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3847; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 3848; SSE41-NEXT: retq 3849; 3850; AVX-LABEL: uitofp_load_4i16_to_4f64: 3851; AVX: # %bb.0: 3852; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 3853; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 3854; AVX-NEXT: retq 3855 %ld = load <4 x i16>, <4 x i16> *%a 3856 %cvt = uitofp <4 x i16> %ld to <4 x double> 3857 ret <4 x double> %cvt 3858} 3859 3860define <4 x double> @uitofp_load_4i8_to_4f64(<4 x i8> *%a) { 3861; SSE2-LABEL: uitofp_load_4i8_to_4f64: 3862; SSE2: # %bb.0: 3863; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 3864; SSE2-NEXT: pxor %xmm0, %xmm0 3865; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 3866; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 3867; SSE2-NEXT: cvtdq2pd %xmm1, %xmm0 3868; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3869; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1 3870; SSE2-NEXT: retq 3871; 3872; SSE41-LABEL: uitofp_load_4i8_to_4f64: 3873; SSE41: # %bb.0: 3874; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 3875; SSE41-NEXT: cvtdq2pd %xmm1, %xmm0 3876; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3877; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1 3878; SSE41-NEXT: retq 3879; 3880; AVX-LABEL: uitofp_load_4i8_to_4f64: 3881; AVX: # %bb.0: 3882; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 3883; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 3884; AVX-NEXT: retq 3885 %ld = load <4 x i8>, <4 x i8> *%a 3886 %cvt = uitofp <4 x i8> %ld to <4 x double> 3887 ret <4 x double> %cvt 3888} 3889 3890; 3891; Load Signed Integer to Float 3892; 3893 3894define <4 x float> @sitofp_load_4i64_to_4f32(<4 x i64> *%a) { 3895; SSE2-LABEL: sitofp_load_4i64_to_4f32: 3896; SSE2: # %bb.0: 3897; SSE2-NEXT: movdqa (%rdi), %xmm1 3898; SSE2-NEXT: movdqa 16(%rdi), %xmm0 3899; SSE2-NEXT: movq %xmm0, %rax 3900; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 3901; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 3902; SSE2-NEXT: movq %xmm0, %rax 3903; SSE2-NEXT: xorps %xmm0, %xmm0 3904; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 3905; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] 3906; SSE2-NEXT: movq %xmm1, %rax 3907; SSE2-NEXT: xorps %xmm0, %xmm0 3908; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 3909; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 3910; SSE2-NEXT: movq %xmm1, %rax 3911; SSE2-NEXT: xorps %xmm1, %xmm1 3912; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 3913; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 3914; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 3915; SSE2-NEXT: retq 3916; 3917; SSE41-LABEL: sitofp_load_4i64_to_4f32: 3918; SSE41: # %bb.0: 3919; SSE41-NEXT: movdqa (%rdi), %xmm0 3920; SSE41-NEXT: movdqa 16(%rdi), %xmm1 3921; SSE41-NEXT: pextrq $1, %xmm0, %rax 3922; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 3923; SSE41-NEXT: movq %xmm0, %rax 3924; SSE41-NEXT: xorps %xmm0, %xmm0 3925; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 3926; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 3927; SSE41-NEXT: movq %xmm1, %rax 3928; SSE41-NEXT: xorps %xmm2, %xmm2 3929; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 3930; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 3931; SSE41-NEXT: pextrq $1, %xmm1, %rax 3932; SSE41-NEXT: xorps %xmm1, %xmm1 3933; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 3934; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 3935; SSE41-NEXT: retq 3936; 3937; VEX-LABEL: sitofp_load_4i64_to_4f32: 3938; VEX: # %bb.0: 3939; VEX-NEXT: vmovdqa (%rdi), %xmm0 3940; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 3941; VEX-NEXT: vpextrq $1, %xmm0, %rax 3942; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 3943; VEX-NEXT: vmovq %xmm0, %rax 3944; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 3945; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 3946; VEX-NEXT: vmovq %xmm1, %rax 3947; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 3948; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 3949; VEX-NEXT: vpextrq $1, %xmm1, %rax 3950; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm1 3951; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 3952; VEX-NEXT: retq 3953; 3954; AVX512F-LABEL: sitofp_load_4i64_to_4f32: 3955; AVX512F: # %bb.0: 3956; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 3957; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 3958; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 3959; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 3960; AVX512F-NEXT: vmovq %xmm0, %rax 3961; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 3962; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 3963; AVX512F-NEXT: vmovq %xmm1, %rax 3964; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 3965; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 3966; AVX512F-NEXT: vpextrq $1, %xmm1, %rax 3967; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm1 3968; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 3969; AVX512F-NEXT: retq 3970; 3971; AVX512VL-LABEL: sitofp_load_4i64_to_4f32: 3972; AVX512VL: # %bb.0: 3973; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 3974; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 3975; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 3976; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 3977; AVX512VL-NEXT: vmovq %xmm0, %rax 3978; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 3979; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 3980; AVX512VL-NEXT: vmovq %xmm1, %rax 3981; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 3982; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 3983; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax 3984; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm1 3985; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 3986; AVX512VL-NEXT: retq 3987; 3988; AVX512DQ-LABEL: sitofp_load_4i64_to_4f32: 3989; AVX512DQ: # %bb.0: 3990; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 3991; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 3992; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 3993; AVX512DQ-NEXT: vzeroupper 3994; AVX512DQ-NEXT: retq 3995; 3996; AVX512VLDQ-LABEL: sitofp_load_4i64_to_4f32: 3997; AVX512VLDQ: # %bb.0: 3998; AVX512VLDQ-NEXT: vcvtqq2psy (%rdi), %xmm0 3999; AVX512VLDQ-NEXT: retq 4000 %ld = load <4 x i64>, <4 x i64> *%a 4001 %cvt = sitofp <4 x i64> %ld to <4 x float> 4002 ret <4 x float> %cvt 4003} 4004 4005define <4 x float> @sitofp_load_4i32_to_4f32(<4 x i32> *%a) { 4006; SSE-LABEL: sitofp_load_4i32_to_4f32: 4007; SSE: # %bb.0: 4008; SSE-NEXT: cvtdq2ps (%rdi), %xmm0 4009; SSE-NEXT: retq 4010; 4011; AVX-LABEL: sitofp_load_4i32_to_4f32: 4012; AVX: # %bb.0: 4013; AVX-NEXT: vcvtdq2ps (%rdi), %xmm0 4014; AVX-NEXT: retq 4015 %ld = load <4 x i32>, <4 x i32> *%a 4016 %cvt = sitofp <4 x i32> %ld to <4 x float> 4017 ret <4 x float> %cvt 4018} 4019 4020define <4 x float> @sitofp_load_4i16_to_4f32(<4 x i16> *%a) { 4021; SSE2-LABEL: sitofp_load_4i16_to_4f32: 4022; SSE2: # %bb.0: 4023; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 4024; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 4025; SSE2-NEXT: psrad $16, %xmm0 4026; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 4027; SSE2-NEXT: retq 4028; 4029; SSE41-LABEL: sitofp_load_4i16_to_4f32: 4030; SSE41: # %bb.0: 4031; SSE41-NEXT: pmovsxwd (%rdi), %xmm0 4032; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 4033; SSE41-NEXT: retq 4034; 4035; AVX-LABEL: sitofp_load_4i16_to_4f32: 4036; AVX: # %bb.0: 4037; AVX-NEXT: vpmovsxwd (%rdi), %xmm0 4038; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 4039; AVX-NEXT: retq 4040 %ld = load <4 x i16>, <4 x i16> *%a 4041 %cvt = sitofp <4 x i16> %ld to <4 x float> 4042 ret <4 x float> %cvt 4043} 4044 4045define <4 x float> @sitofp_load_4i8_to_4f32(<4 x i8> *%a) { 4046; SSE2-LABEL: sitofp_load_4i8_to_4f32: 4047; SSE2: # %bb.0: 4048; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 4049; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 4050; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] 4051; SSE2-NEXT: psrad $24, %xmm0 4052; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 4053; SSE2-NEXT: retq 4054; 4055; SSE41-LABEL: sitofp_load_4i8_to_4f32: 4056; SSE41: # %bb.0: 4057; SSE41-NEXT: pmovsxbd (%rdi), %xmm0 4058; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 4059; SSE41-NEXT: retq 4060; 4061; AVX-LABEL: sitofp_load_4i8_to_4f32: 4062; AVX: # %bb.0: 4063; AVX-NEXT: vpmovsxbd (%rdi), %xmm0 4064; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 4065; AVX-NEXT: retq 4066 %ld = load <4 x i8>, <4 x i8> *%a 4067 %cvt = sitofp <4 x i8> %ld to <4 x float> 4068 ret <4 x float> %cvt 4069} 4070 4071define <8 x float> @sitofp_load_8i64_to_8f32(<8 x i64> *%a) { 4072; SSE2-LABEL: sitofp_load_8i64_to_8f32: 4073; SSE2: # %bb.0: 4074; SSE2-NEXT: movdqa (%rdi), %xmm1 4075; SSE2-NEXT: movdqa 16(%rdi), %xmm0 4076; SSE2-NEXT: movdqa 32(%rdi), %xmm2 4077; SSE2-NEXT: movdqa 48(%rdi), %xmm3 4078; SSE2-NEXT: movq %xmm0, %rax 4079; SSE2-NEXT: cvtsi2ssq %rax, %xmm4 4080; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 4081; SSE2-NEXT: movq %xmm0, %rax 4082; SSE2-NEXT: xorps %xmm0, %xmm0 4083; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 4084; SSE2-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm0[0],xmm4[1],xmm0[1] 4085; SSE2-NEXT: movq %xmm1, %rax 4086; SSE2-NEXT: xorps %xmm0, %xmm0 4087; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 4088; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 4089; SSE2-NEXT: movq %xmm1, %rax 4090; SSE2-NEXT: xorps %xmm1, %xmm1 4091; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 4092; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 4093; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm4[0] 4094; SSE2-NEXT: movq %xmm3, %rax 4095; SSE2-NEXT: xorps %xmm4, %xmm4 4096; SSE2-NEXT: cvtsi2ssq %rax, %xmm4 4097; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[2,3,0,1] 4098; SSE2-NEXT: movq %xmm1, %rax 4099; SSE2-NEXT: xorps %xmm1, %xmm1 4100; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 4101; SSE2-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] 4102; SSE2-NEXT: movq %xmm2, %rax 4103; SSE2-NEXT: xorps %xmm1, %xmm1 4104; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 4105; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] 4106; SSE2-NEXT: movq %xmm2, %rax 4107; SSE2-NEXT: xorps %xmm2, %xmm2 4108; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 4109; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] 4110; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm4[0] 4111; SSE2-NEXT: retq 4112; 4113; SSE41-LABEL: sitofp_load_8i64_to_8f32: 4114; SSE41: # %bb.0: 4115; SSE41-NEXT: movdqa (%rdi), %xmm0 4116; SSE41-NEXT: movdqa 16(%rdi), %xmm1 4117; SSE41-NEXT: movdqa 32(%rdi), %xmm2 4118; SSE41-NEXT: movdqa 48(%rdi), %xmm3 4119; SSE41-NEXT: pextrq $1, %xmm0, %rax 4120; SSE41-NEXT: cvtsi2ssq %rax, %xmm4 4121; SSE41-NEXT: movq %xmm0, %rax 4122; SSE41-NEXT: xorps %xmm0, %xmm0 4123; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 4124; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[2,3] 4125; SSE41-NEXT: movq %xmm1, %rax 4126; SSE41-NEXT: xorps %xmm4, %xmm4 4127; SSE41-NEXT: cvtsi2ssq %rax, %xmm4 4128; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm4[0],xmm0[3] 4129; SSE41-NEXT: pextrq $1, %xmm1, %rax 4130; SSE41-NEXT: xorps %xmm1, %xmm1 4131; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 4132; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4133; SSE41-NEXT: pextrq $1, %xmm2, %rax 4134; SSE41-NEXT: xorps %xmm4, %xmm4 4135; SSE41-NEXT: cvtsi2ssq %rax, %xmm4 4136; SSE41-NEXT: movq %xmm2, %rax 4137; SSE41-NEXT: xorps %xmm1, %xmm1 4138; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 4139; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[2,3] 4140; SSE41-NEXT: movq %xmm3, %rax 4141; SSE41-NEXT: xorps %xmm2, %xmm2 4142; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 4143; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 4144; SSE41-NEXT: pextrq $1, %xmm3, %rax 4145; SSE41-NEXT: xorps %xmm2, %xmm2 4146; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 4147; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] 4148; SSE41-NEXT: retq 4149; 4150; VEX-LABEL: sitofp_load_8i64_to_8f32: 4151; VEX: # %bb.0: 4152; VEX-NEXT: vmovdqa (%rdi), %xmm0 4153; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 4154; VEX-NEXT: vmovdqa 32(%rdi), %xmm2 4155; VEX-NEXT: vmovdqa 48(%rdi), %xmm3 4156; VEX-NEXT: vpextrq $1, %xmm2, %rax 4157; VEX-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4 4158; VEX-NEXT: vmovq %xmm2, %rax 4159; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2 4160; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] 4161; VEX-NEXT: vmovq %xmm3, %rax 4162; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm4 4163; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] 4164; VEX-NEXT: vpextrq $1, %xmm3, %rax 4165; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4166; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] 4167; VEX-NEXT: vpextrq $1, %xmm0, %rax 4168; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4169; VEX-NEXT: vmovq %xmm0, %rax 4170; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm0 4171; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] 4172; VEX-NEXT: vmovq %xmm1, %rax 4173; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4174; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] 4175; VEX-NEXT: vpextrq $1, %xmm1, %rax 4176; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm1 4177; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4178; VEX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 4179; VEX-NEXT: retq 4180; 4181; AVX512F-LABEL: sitofp_load_8i64_to_8f32: 4182; AVX512F: # %bb.0: 4183; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 4184; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 4185; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2 4186; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3 4187; AVX512F-NEXT: vpextrq $1, %xmm2, %rax 4188; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4 4189; AVX512F-NEXT: vmovq %xmm2, %rax 4190; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2 4191; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] 4192; AVX512F-NEXT: vmovq %xmm3, %rax 4193; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm4 4194; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] 4195; AVX512F-NEXT: vpextrq $1, %xmm3, %rax 4196; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4197; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] 4198; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 4199; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4200; AVX512F-NEXT: vmovq %xmm0, %rax 4201; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm0 4202; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] 4203; AVX512F-NEXT: vmovq %xmm1, %rax 4204; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4205; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] 4206; AVX512F-NEXT: vpextrq $1, %xmm1, %rax 4207; AVX512F-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm1 4208; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4209; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 4210; AVX512F-NEXT: retq 4211; 4212; AVX512VL-LABEL: sitofp_load_8i64_to_8f32: 4213; AVX512VL: # %bb.0: 4214; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 4215; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 4216; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2 4217; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3 4218; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax 4219; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm4, %xmm4 4220; AVX512VL-NEXT: vmovq %xmm2, %rax 4221; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm2 4222; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] 4223; AVX512VL-NEXT: vmovq %xmm3, %rax 4224; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm4 4225; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] 4226; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax 4227; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4228; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] 4229; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 4230; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4231; AVX512VL-NEXT: vmovq %xmm0, %rax 4232; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm0 4233; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] 4234; AVX512VL-NEXT: vmovq %xmm1, %rax 4235; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm3 4236; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] 4237; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax 4238; AVX512VL-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm1 4239; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4240; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 4241; AVX512VL-NEXT: retq 4242; 4243; AVX512DQ-LABEL: sitofp_load_8i64_to_8f32: 4244; AVX512DQ: # %bb.0: 4245; AVX512DQ-NEXT: vcvtqq2ps (%rdi), %ymm0 4246; AVX512DQ-NEXT: retq 4247; 4248; AVX512VLDQ-LABEL: sitofp_load_8i64_to_8f32: 4249; AVX512VLDQ: # %bb.0: 4250; AVX512VLDQ-NEXT: vcvtqq2ps (%rdi), %ymm0 4251; AVX512VLDQ-NEXT: retq 4252 %ld = load <8 x i64>, <8 x i64> *%a 4253 %cvt = sitofp <8 x i64> %ld to <8 x float> 4254 ret <8 x float> %cvt 4255} 4256 4257define <8 x float> @sitofp_load_8i32_to_8f32(<8 x i32> *%a) { 4258; SSE-LABEL: sitofp_load_8i32_to_8f32: 4259; SSE: # %bb.0: 4260; SSE-NEXT: cvtdq2ps (%rdi), %xmm0 4261; SSE-NEXT: cvtdq2ps 16(%rdi), %xmm1 4262; SSE-NEXT: retq 4263; 4264; AVX-LABEL: sitofp_load_8i32_to_8f32: 4265; AVX: # %bb.0: 4266; AVX-NEXT: vcvtdq2ps (%rdi), %ymm0 4267; AVX-NEXT: retq 4268 %ld = load <8 x i32>, <8 x i32> *%a 4269 %cvt = sitofp <8 x i32> %ld to <8 x float> 4270 ret <8 x float> %cvt 4271} 4272 4273define <8 x float> @sitofp_load_8i16_to_8f32(<8 x i16> *%a) { 4274; SSE2-LABEL: sitofp_load_8i16_to_8f32: 4275; SSE2: # %bb.0: 4276; SSE2-NEXT: movdqa (%rdi), %xmm1 4277; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 4278; SSE2-NEXT: psrad $16, %xmm0 4279; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 4280; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] 4281; SSE2-NEXT: psrad $16, %xmm1 4282; SSE2-NEXT: cvtdq2ps %xmm1, %xmm1 4283; SSE2-NEXT: retq 4284; 4285; SSE41-LABEL: sitofp_load_8i16_to_8f32: 4286; SSE41: # %bb.0: 4287; SSE41-NEXT: pmovsxwd 8(%rdi), %xmm1 4288; SSE41-NEXT: pmovsxwd (%rdi), %xmm0 4289; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 4290; SSE41-NEXT: cvtdq2ps %xmm1, %xmm1 4291; SSE41-NEXT: retq 4292; 4293; AVX1-LABEL: sitofp_load_8i16_to_8f32: 4294; AVX1: # %bb.0: 4295; AVX1-NEXT: vpmovsxwd 8(%rdi), %xmm0 4296; AVX1-NEXT: vpmovsxwd (%rdi), %xmm1 4297; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 4298; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 4299; AVX1-NEXT: retq 4300; 4301; AVX2-LABEL: sitofp_load_8i16_to_8f32: 4302; AVX2: # %bb.0: 4303; AVX2-NEXT: vpmovsxwd (%rdi), %ymm0 4304; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 4305; AVX2-NEXT: retq 4306; 4307; AVX512-LABEL: sitofp_load_8i16_to_8f32: 4308; AVX512: # %bb.0: 4309; AVX512-NEXT: vpmovsxwd (%rdi), %ymm0 4310; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 4311; AVX512-NEXT: retq 4312 %ld = load <8 x i16>, <8 x i16> *%a 4313 %cvt = sitofp <8 x i16> %ld to <8 x float> 4314 ret <8 x float> %cvt 4315} 4316 4317define <8 x float> @sitofp_load_8i8_to_8f32(<8 x i8> *%a) { 4318; SSE2-LABEL: sitofp_load_8i8_to_8f32: 4319; SSE2: # %bb.0: 4320; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero 4321; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] 4322; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 4323; SSE2-NEXT: psrad $24, %xmm0 4324; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 4325; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] 4326; SSE2-NEXT: psrad $24, %xmm1 4327; SSE2-NEXT: cvtdq2ps %xmm1, %xmm1 4328; SSE2-NEXT: retq 4329; 4330; SSE41-LABEL: sitofp_load_8i8_to_8f32: 4331; SSE41: # %bb.0: 4332; SSE41-NEXT: pmovsxbd 4(%rdi), %xmm1 4333; SSE41-NEXT: pmovsxbd (%rdi), %xmm0 4334; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 4335; SSE41-NEXT: cvtdq2ps %xmm1, %xmm1 4336; SSE41-NEXT: retq 4337; 4338; AVX1-LABEL: sitofp_load_8i8_to_8f32: 4339; AVX1: # %bb.0: 4340; AVX1-NEXT: vpmovsxbd 4(%rdi), %xmm0 4341; AVX1-NEXT: vpmovsxbd (%rdi), %xmm1 4342; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 4343; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 4344; AVX1-NEXT: retq 4345; 4346; AVX2-LABEL: sitofp_load_8i8_to_8f32: 4347; AVX2: # %bb.0: 4348; AVX2-NEXT: vpmovsxbd (%rdi), %ymm0 4349; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 4350; AVX2-NEXT: retq 4351; 4352; AVX512-LABEL: sitofp_load_8i8_to_8f32: 4353; AVX512: # %bb.0: 4354; AVX512-NEXT: vpmovsxbd (%rdi), %ymm0 4355; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 4356; AVX512-NEXT: retq 4357 %ld = load <8 x i8>, <8 x i8> *%a 4358 %cvt = sitofp <8 x i8> %ld to <8 x float> 4359 ret <8 x float> %cvt 4360} 4361 4362; 4363; Load Unsigned Integer to Float 4364; 4365 4366define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) { 4367; SSE2-LABEL: uitofp_load_4i64_to_4f32: 4368; SSE2: # %bb.0: 4369; SSE2-NEXT: movdqa (%rdi), %xmm2 4370; SSE2-NEXT: movdqa 16(%rdi), %xmm0 4371; SSE2-NEXT: movq %xmm0, %rax 4372; SSE2-NEXT: testq %rax, %rax 4373; SSE2-NEXT: js .LBB76_1 4374; SSE2-NEXT: # %bb.2: 4375; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 4376; SSE2-NEXT: jmp .LBB76_3 4377; SSE2-NEXT: .LBB76_1: 4378; SSE2-NEXT: movq %rax, %rcx 4379; SSE2-NEXT: shrq %rcx 4380; SSE2-NEXT: andl $1, %eax 4381; SSE2-NEXT: orq %rcx, %rax 4382; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 4383; SSE2-NEXT: addss %xmm1, %xmm1 4384; SSE2-NEXT: .LBB76_3: 4385; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 4386; SSE2-NEXT: movq %xmm0, %rax 4387; SSE2-NEXT: testq %rax, %rax 4388; SSE2-NEXT: js .LBB76_4 4389; SSE2-NEXT: # %bb.5: 4390; SSE2-NEXT: cvtsi2ssq %rax, %xmm3 4391; SSE2-NEXT: jmp .LBB76_6 4392; SSE2-NEXT: .LBB76_4: 4393; SSE2-NEXT: movq %rax, %rcx 4394; SSE2-NEXT: shrq %rcx 4395; SSE2-NEXT: andl $1, %eax 4396; SSE2-NEXT: orq %rcx, %rax 4397; SSE2-NEXT: cvtsi2ssq %rax, %xmm3 4398; SSE2-NEXT: addss %xmm3, %xmm3 4399; SSE2-NEXT: .LBB76_6: 4400; SSE2-NEXT: movq %xmm2, %rax 4401; SSE2-NEXT: testq %rax, %rax 4402; SSE2-NEXT: js .LBB76_7 4403; SSE2-NEXT: # %bb.8: 4404; SSE2-NEXT: xorps %xmm0, %xmm0 4405; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 4406; SSE2-NEXT: jmp .LBB76_9 4407; SSE2-NEXT: .LBB76_7: 4408; SSE2-NEXT: movq %rax, %rcx 4409; SSE2-NEXT: shrq %rcx 4410; SSE2-NEXT: andl $1, %eax 4411; SSE2-NEXT: orq %rcx, %rax 4412; SSE2-NEXT: xorps %xmm0, %xmm0 4413; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 4414; SSE2-NEXT: addss %xmm0, %xmm0 4415; SSE2-NEXT: .LBB76_9: 4416; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] 4417; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] 4418; SSE2-NEXT: movq %xmm2, %rax 4419; SSE2-NEXT: testq %rax, %rax 4420; SSE2-NEXT: js .LBB76_10 4421; SSE2-NEXT: # %bb.11: 4422; SSE2-NEXT: xorps %xmm2, %xmm2 4423; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 4424; SSE2-NEXT: jmp .LBB76_12 4425; SSE2-NEXT: .LBB76_10: 4426; SSE2-NEXT: movq %rax, %rcx 4427; SSE2-NEXT: shrq %rcx 4428; SSE2-NEXT: andl $1, %eax 4429; SSE2-NEXT: orq %rcx, %rax 4430; SSE2-NEXT: xorps %xmm2, %xmm2 4431; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 4432; SSE2-NEXT: addss %xmm2, %xmm2 4433; SSE2-NEXT: .LBB76_12: 4434; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 4435; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 4436; SSE2-NEXT: retq 4437; 4438; SSE41-LABEL: uitofp_load_4i64_to_4f32: 4439; SSE41: # %bb.0: 4440; SSE41-NEXT: movdqa (%rdi), %xmm0 4441; SSE41-NEXT: movdqa 16(%rdi), %xmm1 4442; SSE41-NEXT: pextrq $1, %xmm0, %rax 4443; SSE41-NEXT: testq %rax, %rax 4444; SSE41-NEXT: js .LBB76_1 4445; SSE41-NEXT: # %bb.2: 4446; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 4447; SSE41-NEXT: jmp .LBB76_3 4448; SSE41-NEXT: .LBB76_1: 4449; SSE41-NEXT: movq %rax, %rcx 4450; SSE41-NEXT: shrq %rcx 4451; SSE41-NEXT: andl $1, %eax 4452; SSE41-NEXT: orq %rcx, %rax 4453; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 4454; SSE41-NEXT: addss %xmm2, %xmm2 4455; SSE41-NEXT: .LBB76_3: 4456; SSE41-NEXT: movq %xmm0, %rax 4457; SSE41-NEXT: testq %rax, %rax 4458; SSE41-NEXT: js .LBB76_4 4459; SSE41-NEXT: # %bb.5: 4460; SSE41-NEXT: xorps %xmm0, %xmm0 4461; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 4462; SSE41-NEXT: jmp .LBB76_6 4463; SSE41-NEXT: .LBB76_4: 4464; SSE41-NEXT: movq %rax, %rcx 4465; SSE41-NEXT: shrq %rcx 4466; SSE41-NEXT: andl $1, %eax 4467; SSE41-NEXT: orq %rcx, %rax 4468; SSE41-NEXT: xorps %xmm0, %xmm0 4469; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 4470; SSE41-NEXT: addss %xmm0, %xmm0 4471; SSE41-NEXT: .LBB76_6: 4472; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 4473; SSE41-NEXT: movq %xmm1, %rax 4474; SSE41-NEXT: testq %rax, %rax 4475; SSE41-NEXT: js .LBB76_7 4476; SSE41-NEXT: # %bb.8: 4477; SSE41-NEXT: xorps %xmm2, %xmm2 4478; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 4479; SSE41-NEXT: jmp .LBB76_9 4480; SSE41-NEXT: .LBB76_7: 4481; SSE41-NEXT: movq %rax, %rcx 4482; SSE41-NEXT: shrq %rcx 4483; SSE41-NEXT: andl $1, %eax 4484; SSE41-NEXT: orq %rcx, %rax 4485; SSE41-NEXT: xorps %xmm2, %xmm2 4486; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 4487; SSE41-NEXT: addss %xmm2, %xmm2 4488; SSE41-NEXT: .LBB76_9: 4489; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 4490; SSE41-NEXT: pextrq $1, %xmm1, %rax 4491; SSE41-NEXT: testq %rax, %rax 4492; SSE41-NEXT: js .LBB76_10 4493; SSE41-NEXT: # %bb.11: 4494; SSE41-NEXT: xorps %xmm1, %xmm1 4495; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 4496; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4497; SSE41-NEXT: retq 4498; SSE41-NEXT: .LBB76_10: 4499; SSE41-NEXT: movq %rax, %rcx 4500; SSE41-NEXT: shrq %rcx 4501; SSE41-NEXT: andl $1, %eax 4502; SSE41-NEXT: orq %rcx, %rax 4503; SSE41-NEXT: xorps %xmm1, %xmm1 4504; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 4505; SSE41-NEXT: addss %xmm1, %xmm1 4506; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4507; SSE41-NEXT: retq 4508; 4509; VEX-LABEL: uitofp_load_4i64_to_4f32: 4510; VEX: # %bb.0: 4511; VEX-NEXT: vmovdqa (%rdi), %xmm2 4512; VEX-NEXT: vmovdqa 16(%rdi), %xmm0 4513; VEX-NEXT: vpextrq $1, %xmm2, %rax 4514; VEX-NEXT: testq %rax, %rax 4515; VEX-NEXT: js .LBB76_1 4516; VEX-NEXT: # %bb.2: 4517; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 4518; VEX-NEXT: jmp .LBB76_3 4519; VEX-NEXT: .LBB76_1: 4520; VEX-NEXT: movq %rax, %rcx 4521; VEX-NEXT: shrq %rcx 4522; VEX-NEXT: andl $1, %eax 4523; VEX-NEXT: orq %rcx, %rax 4524; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm1 4525; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1 4526; VEX-NEXT: .LBB76_3: 4527; VEX-NEXT: vmovq %xmm2, %rax 4528; VEX-NEXT: testq %rax, %rax 4529; VEX-NEXT: js .LBB76_4 4530; VEX-NEXT: # %bb.5: 4531; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 4532; VEX-NEXT: jmp .LBB76_6 4533; VEX-NEXT: .LBB76_4: 4534; VEX-NEXT: movq %rax, %rcx 4535; VEX-NEXT: shrq %rcx 4536; VEX-NEXT: andl $1, %eax 4537; VEX-NEXT: orq %rcx, %rax 4538; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 4539; VEX-NEXT: vaddss %xmm2, %xmm2, %xmm2 4540; VEX-NEXT: .LBB76_6: 4541; VEX-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] 4542; VEX-NEXT: vmovq %xmm0, %rax 4543; VEX-NEXT: testq %rax, %rax 4544; VEX-NEXT: js .LBB76_7 4545; VEX-NEXT: # %bb.8: 4546; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 4547; VEX-NEXT: jmp .LBB76_9 4548; VEX-NEXT: .LBB76_7: 4549; VEX-NEXT: movq %rax, %rcx 4550; VEX-NEXT: shrq %rcx 4551; VEX-NEXT: andl $1, %eax 4552; VEX-NEXT: orq %rcx, %rax 4553; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm2 4554; VEX-NEXT: vaddss %xmm2, %xmm2, %xmm2 4555; VEX-NEXT: .LBB76_9: 4556; VEX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] 4557; VEX-NEXT: vpextrq $1, %xmm0, %rax 4558; VEX-NEXT: testq %rax, %rax 4559; VEX-NEXT: js .LBB76_10 4560; VEX-NEXT: # %bb.11: 4561; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 4562; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 4563; VEX-NEXT: retq 4564; VEX-NEXT: .LBB76_10: 4565; VEX-NEXT: movq %rax, %rcx 4566; VEX-NEXT: shrq %rcx 4567; VEX-NEXT: andl $1, %eax 4568; VEX-NEXT: orq %rcx, %rax 4569; VEX-NEXT: vcvtsi2ssq %rax, %xmm3, %xmm0 4570; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0 4571; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] 4572; VEX-NEXT: retq 4573; 4574; AVX512F-LABEL: uitofp_load_4i64_to_4f32: 4575; AVX512F: # %bb.0: 4576; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 4577; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 4578; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 4579; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2 4580; AVX512F-NEXT: vmovq %xmm0, %rax 4581; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0 4582; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 4583; AVX512F-NEXT: vmovq %xmm1, %rax 4584; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2 4585; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 4586; AVX512F-NEXT: vpextrq $1, %xmm1, %rax 4587; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm1 4588; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4589; AVX512F-NEXT: retq 4590; 4591; AVX512VL-LABEL: uitofp_load_4i64_to_4f32: 4592; AVX512VL: # %bb.0: 4593; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 4594; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 4595; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 4596; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm2, %xmm2 4597; AVX512VL-NEXT: vmovq %xmm0, %rax 4598; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm0 4599; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] 4600; AVX512VL-NEXT: vmovq %xmm1, %rax 4601; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm2 4602; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 4603; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax 4604; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm3, %xmm1 4605; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 4606; AVX512VL-NEXT: retq 4607; 4608; AVX512DQ-LABEL: uitofp_load_4i64_to_4f32: 4609; AVX512DQ: # %bb.0: 4610; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 4611; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 4612; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 4613; AVX512DQ-NEXT: vzeroupper 4614; AVX512DQ-NEXT: retq 4615; 4616; AVX512VLDQ-LABEL: uitofp_load_4i64_to_4f32: 4617; AVX512VLDQ: # %bb.0: 4618; AVX512VLDQ-NEXT: vcvtuqq2psy (%rdi), %xmm0 4619; AVX512VLDQ-NEXT: retq 4620 %ld = load <4 x i64>, <4 x i64> *%a 4621 %cvt = uitofp <4 x i64> %ld to <4 x float> 4622 ret <4 x float> %cvt 4623} 4624 4625define <4 x float> @uitofp_load_4i32_to_4f32(<4 x i32> *%a) { 4626; SSE2-LABEL: uitofp_load_4i32_to_4f32: 4627; SSE2: # %bb.0: 4628; SSE2-NEXT: movdqa (%rdi), %xmm0 4629; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] 4630; SSE2-NEXT: pand %xmm0, %xmm1 4631; SSE2-NEXT: por {{.*}}(%rip), %xmm1 4632; SSE2-NEXT: psrld $16, %xmm0 4633; SSE2-NEXT: por {{.*}}(%rip), %xmm0 4634; SSE2-NEXT: addps {{.*}}(%rip), %xmm0 4635; SSE2-NEXT: addps %xmm1, %xmm0 4636; SSE2-NEXT: retq 4637; 4638; SSE41-LABEL: uitofp_load_4i32_to_4f32: 4639; SSE41: # %bb.0: 4640; SSE41-NEXT: movdqa (%rdi), %xmm0 4641; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200] 4642; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 4643; SSE41-NEXT: psrld $16, %xmm0 4644; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 4645; SSE41-NEXT: addps {{.*}}(%rip), %xmm0 4646; SSE41-NEXT: addps %xmm1, %xmm0 4647; SSE41-NEXT: retq 4648; 4649; AVX1-LABEL: uitofp_load_4i32_to_4f32: 4650; AVX1: # %bb.0: 4651; AVX1-NEXT: vmovdqa (%rdi), %xmm0 4652; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 4653; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0 4654; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 4655; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0 4656; AVX1-NEXT: vaddps %xmm0, %xmm1, %xmm0 4657; AVX1-NEXT: retq 4658; 4659; AVX2-LABEL: uitofp_load_4i32_to_4f32: 4660; AVX2: # %bb.0: 4661; AVX2-NEXT: vmovdqa (%rdi), %xmm0 4662; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200] 4663; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 4664; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0 4665; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1392508928,1392508928,1392508928,1392508928] 4666; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] 4667; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 4668; AVX2-NEXT: vaddps %xmm2, %xmm0, %xmm0 4669; AVX2-NEXT: vaddps %xmm0, %xmm1, %xmm0 4670; AVX2-NEXT: retq 4671; 4672; AVX512F-LABEL: uitofp_load_4i32_to_4f32: 4673; AVX512F: # %bb.0: 4674; AVX512F-NEXT: vmovaps (%rdi), %xmm0 4675; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 4676; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 4677; AVX512F-NEXT: vzeroupper 4678; AVX512F-NEXT: retq 4679; 4680; AVX512VL-LABEL: uitofp_load_4i32_to_4f32: 4681; AVX512VL: # %bb.0: 4682; AVX512VL-NEXT: vcvtudq2ps (%rdi), %xmm0 4683; AVX512VL-NEXT: retq 4684; 4685; AVX512DQ-LABEL: uitofp_load_4i32_to_4f32: 4686; AVX512DQ: # %bb.0: 4687; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 4688; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 4689; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 4690; AVX512DQ-NEXT: vzeroupper 4691; AVX512DQ-NEXT: retq 4692; 4693; AVX512VLDQ-LABEL: uitofp_load_4i32_to_4f32: 4694; AVX512VLDQ: # %bb.0: 4695; AVX512VLDQ-NEXT: vcvtudq2ps (%rdi), %xmm0 4696; AVX512VLDQ-NEXT: retq 4697 %ld = load <4 x i32>, <4 x i32> *%a 4698 %cvt = uitofp <4 x i32> %ld to <4 x float> 4699 ret <4 x float> %cvt 4700} 4701 4702define <4 x float> @uitofp_load_4i16_to_4f32(<4 x i16> *%a) { 4703; SSE2-LABEL: uitofp_load_4i16_to_4f32: 4704; SSE2: # %bb.0: 4705; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 4706; SSE2-NEXT: pxor %xmm1, %xmm1 4707; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 4708; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 4709; SSE2-NEXT: retq 4710; 4711; SSE41-LABEL: uitofp_load_4i16_to_4f32: 4712; SSE41: # %bb.0: 4713; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 4714; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 4715; SSE41-NEXT: retq 4716; 4717; AVX-LABEL: uitofp_load_4i16_to_4f32: 4718; AVX: # %bb.0: 4719; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 4720; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 4721; AVX-NEXT: retq 4722 %ld = load <4 x i16>, <4 x i16> *%a 4723 %cvt = uitofp <4 x i16> %ld to <4 x float> 4724 ret <4 x float> %cvt 4725} 4726 4727define <4 x float> @uitofp_load_4i8_to_4f32(<4 x i8> *%a) { 4728; SSE2-LABEL: uitofp_load_4i8_to_4f32: 4729; SSE2: # %bb.0: 4730; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 4731; SSE2-NEXT: pxor %xmm1, %xmm1 4732; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 4733; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 4734; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 4735; SSE2-NEXT: retq 4736; 4737; SSE41-LABEL: uitofp_load_4i8_to_4f32: 4738; SSE41: # %bb.0: 4739; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 4740; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 4741; SSE41-NEXT: retq 4742; 4743; AVX-LABEL: uitofp_load_4i8_to_4f32: 4744; AVX: # %bb.0: 4745; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 4746; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 4747; AVX-NEXT: retq 4748 %ld = load <4 x i8>, <4 x i8> *%a 4749 %cvt = uitofp <4 x i8> %ld to <4 x float> 4750 ret <4 x float> %cvt 4751} 4752 4753define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) { 4754; SSE2-LABEL: uitofp_load_8i64_to_8f32: 4755; SSE2: # %bb.0: 4756; SSE2-NEXT: movdqa (%rdi), %xmm5 4757; SSE2-NEXT: movdqa 16(%rdi), %xmm0 4758; SSE2-NEXT: movdqa 32(%rdi), %xmm2 4759; SSE2-NEXT: movdqa 48(%rdi), %xmm1 4760; SSE2-NEXT: movq %xmm0, %rax 4761; SSE2-NEXT: testq %rax, %rax 4762; SSE2-NEXT: js .LBB80_1 4763; SSE2-NEXT: # %bb.2: 4764; SSE2-NEXT: cvtsi2ssq %rax, %xmm3 4765; SSE2-NEXT: jmp .LBB80_3 4766; SSE2-NEXT: .LBB80_1: 4767; SSE2-NEXT: movq %rax, %rcx 4768; SSE2-NEXT: shrq %rcx 4769; SSE2-NEXT: andl $1, %eax 4770; SSE2-NEXT: orq %rcx, %rax 4771; SSE2-NEXT: cvtsi2ssq %rax, %xmm3 4772; SSE2-NEXT: addss %xmm3, %xmm3 4773; SSE2-NEXT: .LBB80_3: 4774; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 4775; SSE2-NEXT: movq %xmm0, %rax 4776; SSE2-NEXT: testq %rax, %rax 4777; SSE2-NEXT: js .LBB80_4 4778; SSE2-NEXT: # %bb.5: 4779; SSE2-NEXT: cvtsi2ssq %rax, %xmm4 4780; SSE2-NEXT: jmp .LBB80_6 4781; SSE2-NEXT: .LBB80_4: 4782; SSE2-NEXT: movq %rax, %rcx 4783; SSE2-NEXT: shrq %rcx 4784; SSE2-NEXT: andl $1, %eax 4785; SSE2-NEXT: orq %rcx, %rax 4786; SSE2-NEXT: cvtsi2ssq %rax, %xmm4 4787; SSE2-NEXT: addss %xmm4, %xmm4 4788; SSE2-NEXT: .LBB80_6: 4789; SSE2-NEXT: movq %xmm5, %rax 4790; SSE2-NEXT: testq %rax, %rax 4791; SSE2-NEXT: js .LBB80_7 4792; SSE2-NEXT: # %bb.8: 4793; SSE2-NEXT: xorps %xmm0, %xmm0 4794; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 4795; SSE2-NEXT: jmp .LBB80_9 4796; SSE2-NEXT: .LBB80_7: 4797; SSE2-NEXT: movq %rax, %rcx 4798; SSE2-NEXT: shrq %rcx 4799; SSE2-NEXT: andl $1, %eax 4800; SSE2-NEXT: orq %rcx, %rax 4801; SSE2-NEXT: xorps %xmm0, %xmm0 4802; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 4803; SSE2-NEXT: addss %xmm0, %xmm0 4804; SSE2-NEXT: .LBB80_9: 4805; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,0,1] 4806; SSE2-NEXT: movq %xmm5, %rax 4807; SSE2-NEXT: testq %rax, %rax 4808; SSE2-NEXT: js .LBB80_10 4809; SSE2-NEXT: # %bb.11: 4810; SSE2-NEXT: cvtsi2ssq %rax, %xmm6 4811; SSE2-NEXT: jmp .LBB80_12 4812; SSE2-NEXT: .LBB80_10: 4813; SSE2-NEXT: movq %rax, %rcx 4814; SSE2-NEXT: shrq %rcx 4815; SSE2-NEXT: andl $1, %eax 4816; SSE2-NEXT: orq %rcx, %rax 4817; SSE2-NEXT: cvtsi2ssq %rax, %xmm6 4818; SSE2-NEXT: addss %xmm6, %xmm6 4819; SSE2-NEXT: .LBB80_12: 4820; SSE2-NEXT: movq %xmm1, %rax 4821; SSE2-NEXT: testq %rax, %rax 4822; SSE2-NEXT: js .LBB80_13 4823; SSE2-NEXT: # %bb.14: 4824; SSE2-NEXT: xorps %xmm5, %xmm5 4825; SSE2-NEXT: cvtsi2ssq %rax, %xmm5 4826; SSE2-NEXT: jmp .LBB80_15 4827; SSE2-NEXT: .LBB80_13: 4828; SSE2-NEXT: movq %rax, %rcx 4829; SSE2-NEXT: shrq %rcx 4830; SSE2-NEXT: andl $1, %eax 4831; SSE2-NEXT: orq %rcx, %rax 4832; SSE2-NEXT: xorps %xmm5, %xmm5 4833; SSE2-NEXT: cvtsi2ssq %rax, %xmm5 4834; SSE2-NEXT: addss %xmm5, %xmm5 4835; SSE2-NEXT: .LBB80_15: 4836; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] 4837; SSE2-NEXT: movq %xmm1, %rax 4838; SSE2-NEXT: testq %rax, %rax 4839; SSE2-NEXT: js .LBB80_16 4840; SSE2-NEXT: # %bb.17: 4841; SSE2-NEXT: cvtsi2ssq %rax, %xmm7 4842; SSE2-NEXT: jmp .LBB80_18 4843; SSE2-NEXT: .LBB80_16: 4844; SSE2-NEXT: movq %rax, %rcx 4845; SSE2-NEXT: shrq %rcx 4846; SSE2-NEXT: andl $1, %eax 4847; SSE2-NEXT: orq %rcx, %rax 4848; SSE2-NEXT: cvtsi2ssq %rax, %xmm7 4849; SSE2-NEXT: addss %xmm7, %xmm7 4850; SSE2-NEXT: .LBB80_18: 4851; SSE2-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] 4852; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[1] 4853; SSE2-NEXT: movq %xmm2, %rax 4854; SSE2-NEXT: testq %rax, %rax 4855; SSE2-NEXT: js .LBB80_19 4856; SSE2-NEXT: # %bb.20: 4857; SSE2-NEXT: xorps %xmm1, %xmm1 4858; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 4859; SSE2-NEXT: jmp .LBB80_21 4860; SSE2-NEXT: .LBB80_19: 4861; SSE2-NEXT: movq %rax, %rcx 4862; SSE2-NEXT: shrq %rcx 4863; SSE2-NEXT: andl $1, %eax 4864; SSE2-NEXT: orq %rcx, %rax 4865; SSE2-NEXT: xorps %xmm1, %xmm1 4866; SSE2-NEXT: cvtsi2ssq %rax, %xmm1 4867; SSE2-NEXT: addss %xmm1, %xmm1 4868; SSE2-NEXT: .LBB80_21: 4869; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0] 4870; SSE2-NEXT: unpcklps {{.*#+}} xmm5 = xmm5[0],xmm7[0],xmm5[1],xmm7[1] 4871; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] 4872; SSE2-NEXT: movq %xmm2, %rax 4873; SSE2-NEXT: testq %rax, %rax 4874; SSE2-NEXT: js .LBB80_22 4875; SSE2-NEXT: # %bb.23: 4876; SSE2-NEXT: xorps %xmm2, %xmm2 4877; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 4878; SSE2-NEXT: jmp .LBB80_24 4879; SSE2-NEXT: .LBB80_22: 4880; SSE2-NEXT: movq %rax, %rcx 4881; SSE2-NEXT: shrq %rcx 4882; SSE2-NEXT: andl $1, %eax 4883; SSE2-NEXT: orq %rcx, %rax 4884; SSE2-NEXT: xorps %xmm2, %xmm2 4885; SSE2-NEXT: cvtsi2ssq %rax, %xmm2 4886; SSE2-NEXT: addss %xmm2, %xmm2 4887; SSE2-NEXT: .LBB80_24: 4888; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] 4889; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm5[0] 4890; SSE2-NEXT: retq 4891; 4892; SSE41-LABEL: uitofp_load_8i64_to_8f32: 4893; SSE41: # %bb.0: 4894; SSE41-NEXT: movdqa (%rdi), %xmm0 4895; SSE41-NEXT: movdqa 16(%rdi), %xmm4 4896; SSE41-NEXT: movdqa 32(%rdi), %xmm1 4897; SSE41-NEXT: movdqa 48(%rdi), %xmm2 4898; SSE41-NEXT: pextrq $1, %xmm0, %rax 4899; SSE41-NEXT: testq %rax, %rax 4900; SSE41-NEXT: js .LBB80_1 4901; SSE41-NEXT: # %bb.2: 4902; SSE41-NEXT: cvtsi2ssq %rax, %xmm3 4903; SSE41-NEXT: jmp .LBB80_3 4904; SSE41-NEXT: .LBB80_1: 4905; SSE41-NEXT: movq %rax, %rcx 4906; SSE41-NEXT: shrq %rcx 4907; SSE41-NEXT: andl $1, %eax 4908; SSE41-NEXT: orq %rcx, %rax 4909; SSE41-NEXT: cvtsi2ssq %rax, %xmm3 4910; SSE41-NEXT: addss %xmm3, %xmm3 4911; SSE41-NEXT: .LBB80_3: 4912; SSE41-NEXT: movq %xmm0, %rax 4913; SSE41-NEXT: testq %rax, %rax 4914; SSE41-NEXT: js .LBB80_4 4915; SSE41-NEXT: # %bb.5: 4916; SSE41-NEXT: xorps %xmm0, %xmm0 4917; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 4918; SSE41-NEXT: jmp .LBB80_6 4919; SSE41-NEXT: .LBB80_4: 4920; SSE41-NEXT: movq %rax, %rcx 4921; SSE41-NEXT: shrq %rcx 4922; SSE41-NEXT: andl $1, %eax 4923; SSE41-NEXT: orq %rcx, %rax 4924; SSE41-NEXT: xorps %xmm0, %xmm0 4925; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 4926; SSE41-NEXT: addss %xmm0, %xmm0 4927; SSE41-NEXT: .LBB80_6: 4928; SSE41-NEXT: movq %xmm4, %rax 4929; SSE41-NEXT: testq %rax, %rax 4930; SSE41-NEXT: js .LBB80_7 4931; SSE41-NEXT: # %bb.8: 4932; SSE41-NEXT: cvtsi2ssq %rax, %xmm5 4933; SSE41-NEXT: jmp .LBB80_9 4934; SSE41-NEXT: .LBB80_7: 4935; SSE41-NEXT: movq %rax, %rcx 4936; SSE41-NEXT: shrq %rcx 4937; SSE41-NEXT: andl $1, %eax 4938; SSE41-NEXT: orq %rcx, %rax 4939; SSE41-NEXT: cvtsi2ssq %rax, %xmm5 4940; SSE41-NEXT: addss %xmm5, %xmm5 4941; SSE41-NEXT: .LBB80_9: 4942; SSE41-NEXT: pextrq $1, %xmm4, %rax 4943; SSE41-NEXT: testq %rax, %rax 4944; SSE41-NEXT: js .LBB80_10 4945; SSE41-NEXT: # %bb.11: 4946; SSE41-NEXT: xorps %xmm4, %xmm4 4947; SSE41-NEXT: cvtsi2ssq %rax, %xmm4 4948; SSE41-NEXT: jmp .LBB80_12 4949; SSE41-NEXT: .LBB80_10: 4950; SSE41-NEXT: movq %rax, %rcx 4951; SSE41-NEXT: shrq %rcx 4952; SSE41-NEXT: andl $1, %eax 4953; SSE41-NEXT: orq %rcx, %rax 4954; SSE41-NEXT: xorps %xmm4, %xmm4 4955; SSE41-NEXT: cvtsi2ssq %rax, %xmm4 4956; SSE41-NEXT: addss %xmm4, %xmm4 4957; SSE41-NEXT: .LBB80_12: 4958; SSE41-NEXT: pextrq $1, %xmm1, %rax 4959; SSE41-NEXT: testq %rax, %rax 4960; SSE41-NEXT: js .LBB80_13 4961; SSE41-NEXT: # %bb.14: 4962; SSE41-NEXT: cvtsi2ssq %rax, %xmm6 4963; SSE41-NEXT: jmp .LBB80_15 4964; SSE41-NEXT: .LBB80_13: 4965; SSE41-NEXT: movq %rax, %rcx 4966; SSE41-NEXT: shrq %rcx 4967; SSE41-NEXT: andl $1, %eax 4968; SSE41-NEXT: orq %rcx, %rax 4969; SSE41-NEXT: cvtsi2ssq %rax, %xmm6 4970; SSE41-NEXT: addss %xmm6, %xmm6 4971; SSE41-NEXT: .LBB80_15: 4972; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] 4973; SSE41-NEXT: movq %xmm1, %rax 4974; SSE41-NEXT: testq %rax, %rax 4975; SSE41-NEXT: js .LBB80_16 4976; SSE41-NEXT: # %bb.17: 4977; SSE41-NEXT: xorps %xmm1, %xmm1 4978; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 4979; SSE41-NEXT: jmp .LBB80_18 4980; SSE41-NEXT: .LBB80_16: 4981; SSE41-NEXT: movq %rax, %rcx 4982; SSE41-NEXT: shrq %rcx 4983; SSE41-NEXT: andl $1, %eax 4984; SSE41-NEXT: orq %rcx, %rax 4985; SSE41-NEXT: xorps %xmm1, %xmm1 4986; SSE41-NEXT: cvtsi2ssq %rax, %xmm1 4987; SSE41-NEXT: addss %xmm1, %xmm1 4988; SSE41-NEXT: .LBB80_18: 4989; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[2,3] 4990; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm5[0],xmm0[3] 4991; SSE41-NEXT: movq %xmm2, %rax 4992; SSE41-NEXT: testq %rax, %rax 4993; SSE41-NEXT: js .LBB80_19 4994; SSE41-NEXT: # %bb.20: 4995; SSE41-NEXT: xorps %xmm3, %xmm3 4996; SSE41-NEXT: cvtsi2ssq %rax, %xmm3 4997; SSE41-NEXT: jmp .LBB80_21 4998; SSE41-NEXT: .LBB80_19: 4999; SSE41-NEXT: movq %rax, %rcx 5000; SSE41-NEXT: shrq %rcx 5001; SSE41-NEXT: andl $1, %eax 5002; SSE41-NEXT: orq %rcx, %rax 5003; SSE41-NEXT: xorps %xmm3, %xmm3 5004; SSE41-NEXT: cvtsi2ssq %rax, %xmm3 5005; SSE41-NEXT: addss %xmm3, %xmm3 5006; SSE41-NEXT: .LBB80_21: 5007; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3] 5008; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0] 5009; SSE41-NEXT: pextrq $1, %xmm2, %rax 5010; SSE41-NEXT: testq %rax, %rax 5011; SSE41-NEXT: js .LBB80_22 5012; SSE41-NEXT: # %bb.23: 5013; SSE41-NEXT: xorps %xmm2, %xmm2 5014; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 5015; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] 5016; SSE41-NEXT: retq 5017; SSE41-NEXT: .LBB80_22: 5018; SSE41-NEXT: movq %rax, %rcx 5019; SSE41-NEXT: shrq %rcx 5020; SSE41-NEXT: andl $1, %eax 5021; SSE41-NEXT: orq %rcx, %rax 5022; SSE41-NEXT: xorps %xmm2, %xmm2 5023; SSE41-NEXT: cvtsi2ssq %rax, %xmm2 5024; SSE41-NEXT: addss %xmm2, %xmm2 5025; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] 5026; SSE41-NEXT: retq 5027; 5028; VEX-LABEL: uitofp_load_8i64_to_8f32: 5029; VEX: # %bb.0: 5030; VEX-NEXT: vmovdqa (%rdi), %xmm1 5031; VEX-NEXT: vmovdqa 16(%rdi), %xmm0 5032; VEX-NEXT: vmovdqa 32(%rdi), %xmm4 5033; VEX-NEXT: vmovdqa 48(%rdi), %xmm3 5034; VEX-NEXT: vpextrq $1, %xmm4, %rax 5035; VEX-NEXT: testq %rax, %rax 5036; VEX-NEXT: js .LBB80_1 5037; VEX-NEXT: # %bb.2: 5038; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 5039; VEX-NEXT: jmp .LBB80_3 5040; VEX-NEXT: .LBB80_1: 5041; VEX-NEXT: movq %rax, %rcx 5042; VEX-NEXT: shrq %rcx 5043; VEX-NEXT: andl $1, %eax 5044; VEX-NEXT: orq %rcx, %rax 5045; VEX-NEXT: vcvtsi2ssq %rax, %xmm2, %xmm2 5046; VEX-NEXT: vaddss %xmm2, %xmm2, %xmm2 5047; VEX-NEXT: .LBB80_3: 5048; VEX-NEXT: vmovq %xmm4, %rax 5049; VEX-NEXT: testq %rax, %rax 5050; VEX-NEXT: js .LBB80_4 5051; VEX-NEXT: # %bb.5: 5052; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm5 5053; VEX-NEXT: jmp .LBB80_6 5054; VEX-NEXT: .LBB80_4: 5055; VEX-NEXT: movq %rax, %rcx 5056; VEX-NEXT: shrq %rcx 5057; VEX-NEXT: andl $1, %eax 5058; VEX-NEXT: orq %rcx, %rax 5059; VEX-NEXT: vcvtsi2ssq %rax, %xmm5, %xmm4 5060; VEX-NEXT: vaddss %xmm4, %xmm4, %xmm5 5061; VEX-NEXT: .LBB80_6: 5062; VEX-NEXT: vmovq %xmm3, %rax 5063; VEX-NEXT: testq %rax, %rax 5064; VEX-NEXT: js .LBB80_7 5065; VEX-NEXT: # %bb.8: 5066; VEX-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm4 5067; VEX-NEXT: jmp .LBB80_9 5068; VEX-NEXT: .LBB80_7: 5069; VEX-NEXT: movq %rax, %rcx 5070; VEX-NEXT: shrq %rcx 5071; VEX-NEXT: andl $1, %eax 5072; VEX-NEXT: orq %rcx, %rax 5073; VEX-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm4 5074; VEX-NEXT: vaddss %xmm4, %xmm4, %xmm4 5075; VEX-NEXT: .LBB80_9: 5076; VEX-NEXT: vpextrq $1, %xmm3, %rax 5077; VEX-NEXT: testq %rax, %rax 5078; VEX-NEXT: js .LBB80_10 5079; VEX-NEXT: # %bb.11: 5080; VEX-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3 5081; VEX-NEXT: jmp .LBB80_12 5082; VEX-NEXT: .LBB80_10: 5083; VEX-NEXT: movq %rax, %rcx 5084; VEX-NEXT: shrq %rcx 5085; VEX-NEXT: andl $1, %eax 5086; VEX-NEXT: orq %rcx, %rax 5087; VEX-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm3 5088; VEX-NEXT: vaddss %xmm3, %xmm3, %xmm3 5089; VEX-NEXT: .LBB80_12: 5090; VEX-NEXT: vpextrq $1, %xmm1, %rax 5091; VEX-NEXT: testq %rax, %rax 5092; VEX-NEXT: js .LBB80_13 5093; VEX-NEXT: # %bb.14: 5094; VEX-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm6 5095; VEX-NEXT: jmp .LBB80_15 5096; VEX-NEXT: .LBB80_13: 5097; VEX-NEXT: movq %rax, %rcx 5098; VEX-NEXT: shrq %rcx 5099; VEX-NEXT: andl $1, %eax 5100; VEX-NEXT: orq %rcx, %rax 5101; VEX-NEXT: vcvtsi2ssq %rax, %xmm6, %xmm6 5102; VEX-NEXT: vaddss %xmm6, %xmm6, %xmm6 5103; VEX-NEXT: .LBB80_15: 5104; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm5[0],xmm2[0],xmm5[2,3] 5105; VEX-NEXT: vmovq %xmm1, %rax 5106; VEX-NEXT: testq %rax, %rax 5107; VEX-NEXT: js .LBB80_16 5108; VEX-NEXT: # %bb.17: 5109; VEX-NEXT: vcvtsi2ssq %rax, %xmm7, %xmm1 5110; VEX-NEXT: jmp .LBB80_18 5111; VEX-NEXT: .LBB80_16: 5112; VEX-NEXT: movq %rax, %rcx 5113; VEX-NEXT: shrq %rcx 5114; VEX-NEXT: andl $1, %eax 5115; VEX-NEXT: orq %rcx, %rax 5116; VEX-NEXT: vcvtsi2ssq %rax, %xmm7, %xmm1 5117; VEX-NEXT: vaddss %xmm1, %xmm1, %xmm1 5118; VEX-NEXT: .LBB80_18: 5119; VEX-NEXT: vinsertps {{.*#+}} xmm5 = xmm1[0],xmm6[0],xmm1[2,3] 5120; VEX-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm4[0],xmm2[3] 5121; VEX-NEXT: vmovq %xmm0, %rax 5122; VEX-NEXT: testq %rax, %rax 5123; VEX-NEXT: js .LBB80_19 5124; VEX-NEXT: # %bb.20: 5125; VEX-NEXT: vcvtsi2ssq %rax, %xmm7, %xmm2 5126; VEX-NEXT: jmp .LBB80_21 5127; VEX-NEXT: .LBB80_19: 5128; VEX-NEXT: movq %rax, %rcx 5129; VEX-NEXT: shrq %rcx 5130; VEX-NEXT: andl $1, %eax 5131; VEX-NEXT: orq %rcx, %rax 5132; VEX-NEXT: vcvtsi2ssq %rax, %xmm7, %xmm2 5133; VEX-NEXT: vaddss %xmm2, %xmm2, %xmm2 5134; VEX-NEXT: .LBB80_21: 5135; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm5[0,1],xmm2[0],xmm5[3] 5136; VEX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0] 5137; VEX-NEXT: vpextrq $1, %xmm0, %rax 5138; VEX-NEXT: testq %rax, %rax 5139; VEX-NEXT: js .LBB80_22 5140; VEX-NEXT: # %bb.23: 5141; VEX-NEXT: vcvtsi2ssq %rax, %xmm7, %xmm0 5142; VEX-NEXT: jmp .LBB80_24 5143; VEX-NEXT: .LBB80_22: 5144; VEX-NEXT: movq %rax, %rcx 5145; VEX-NEXT: shrq %rcx 5146; VEX-NEXT: andl $1, %eax 5147; VEX-NEXT: orq %rcx, %rax 5148; VEX-NEXT: vcvtsi2ssq %rax, %xmm7, %xmm0 5149; VEX-NEXT: vaddss %xmm0, %xmm0, %xmm0 5150; VEX-NEXT: .LBB80_24: 5151; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] 5152; VEX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 5153; VEX-NEXT: retq 5154; 5155; AVX512F-LABEL: uitofp_load_8i64_to_8f32: 5156; AVX512F: # %bb.0: 5157; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 5158; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 5159; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2 5160; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3 5161; AVX512F-NEXT: vpextrq $1, %xmm2, %rax 5162; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm4 5163; AVX512F-NEXT: vmovq %xmm2, %rax 5164; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm2 5165; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] 5166; AVX512F-NEXT: vmovq %xmm3, %rax 5167; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm4 5168; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] 5169; AVX512F-NEXT: vpextrq $1, %xmm3, %rax 5170; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm3 5171; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] 5172; AVX512F-NEXT: vpextrq $1, %xmm0, %rax 5173; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm3 5174; AVX512F-NEXT: vmovq %xmm0, %rax 5175; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm0 5176; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] 5177; AVX512F-NEXT: vmovq %xmm1, %rax 5178; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm3 5179; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] 5180; AVX512F-NEXT: vpextrq $1, %xmm1, %rax 5181; AVX512F-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm1 5182; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 5183; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 5184; AVX512F-NEXT: retq 5185; 5186; AVX512VL-LABEL: uitofp_load_8i64_to_8f32: 5187; AVX512VL: # %bb.0: 5188; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 5189; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 5190; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2 5191; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3 5192; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax 5193; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm4, %xmm4 5194; AVX512VL-NEXT: vmovq %xmm2, %rax 5195; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm2 5196; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] 5197; AVX512VL-NEXT: vmovq %xmm3, %rax 5198; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm4 5199; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] 5200; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax 5201; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm3 5202; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] 5203; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax 5204; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm3 5205; AVX512VL-NEXT: vmovq %xmm0, %rax 5206; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm0 5207; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] 5208; AVX512VL-NEXT: vmovq %xmm1, %rax 5209; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm3 5210; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] 5211; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax 5212; AVX512VL-NEXT: vcvtusi2ssq %rax, %xmm5, %xmm1 5213; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] 5214; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 5215; AVX512VL-NEXT: retq 5216; 5217; AVX512DQ-LABEL: uitofp_load_8i64_to_8f32: 5218; AVX512DQ: # %bb.0: 5219; AVX512DQ-NEXT: vcvtuqq2ps (%rdi), %ymm0 5220; AVX512DQ-NEXT: retq 5221; 5222; AVX512VLDQ-LABEL: uitofp_load_8i64_to_8f32: 5223; AVX512VLDQ: # %bb.0: 5224; AVX512VLDQ-NEXT: vcvtuqq2ps (%rdi), %ymm0 5225; AVX512VLDQ-NEXT: retq 5226 %ld = load <8 x i64>, <8 x i64> *%a 5227 %cvt = uitofp <8 x i64> %ld to <8 x float> 5228 ret <8 x float> %cvt 5229} 5230 5231define <8 x float> @uitofp_load_8i32_to_8f32(<8 x i32> *%a) { 5232; SSE2-LABEL: uitofp_load_8i32_to_8f32: 5233; SSE2: # %bb.0: 5234; SSE2-NEXT: movdqa (%rdi), %xmm0 5235; SSE2-NEXT: movdqa 16(%rdi), %xmm1 5236; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,65535,65535,65535] 5237; SSE2-NEXT: movdqa %xmm0, %xmm3 5238; SSE2-NEXT: pand %xmm2, %xmm3 5239; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1258291200,1258291200,1258291200,1258291200] 5240; SSE2-NEXT: por %xmm4, %xmm3 5241; SSE2-NEXT: psrld $16, %xmm0 5242; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1392508928,1392508928,1392508928,1392508928] 5243; SSE2-NEXT: por %xmm5, %xmm0 5244; SSE2-NEXT: movaps {{.*#+}} xmm6 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 5245; SSE2-NEXT: addps %xmm6, %xmm0 5246; SSE2-NEXT: addps %xmm3, %xmm0 5247; SSE2-NEXT: pand %xmm1, %xmm2 5248; SSE2-NEXT: por %xmm4, %xmm2 5249; SSE2-NEXT: psrld $16, %xmm1 5250; SSE2-NEXT: por %xmm5, %xmm1 5251; SSE2-NEXT: addps %xmm6, %xmm1 5252; SSE2-NEXT: addps %xmm2, %xmm1 5253; SSE2-NEXT: retq 5254; 5255; SSE41-LABEL: uitofp_load_8i32_to_8f32: 5256; SSE41: # %bb.0: 5257; SSE41-NEXT: movdqa (%rdi), %xmm0 5258; SSE41-NEXT: movdqa 16(%rdi), %xmm1 5259; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [1258291200,1258291200,1258291200,1258291200] 5260; SSE41-NEXT: movdqa %xmm0, %xmm3 5261; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm2[1],xmm3[2],xmm2[3],xmm3[4],xmm2[5],xmm3[6],xmm2[7] 5262; SSE41-NEXT: psrld $16, %xmm0 5263; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [1392508928,1392508928,1392508928,1392508928] 5264; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm4[1],xmm0[2],xmm4[3],xmm0[4],xmm4[5],xmm0[6],xmm4[7] 5265; SSE41-NEXT: movaps {{.*#+}} xmm5 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 5266; SSE41-NEXT: addps %xmm5, %xmm0 5267; SSE41-NEXT: addps %xmm3, %xmm0 5268; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7] 5269; SSE41-NEXT: psrld $16, %xmm1 5270; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],xmm4[1],xmm1[2],xmm4[3],xmm1[4],xmm4[5],xmm1[6],xmm4[7] 5271; SSE41-NEXT: addps %xmm5, %xmm1 5272; SSE41-NEXT: addps %xmm2, %xmm1 5273; SSE41-NEXT: retq 5274; 5275; AVX1-LABEL: uitofp_load_8i32_to_8f32: 5276; AVX1: # %bb.0: 5277; AVX1-NEXT: vmovaps (%rdi), %ymm0 5278; AVX1-NEXT: vmovdqa (%rdi), %xmm1 5279; AVX1-NEXT: vmovdqa 16(%rdi), %xmm2 5280; AVX1-NEXT: vpsrld $16, %xmm1, %xmm1 5281; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2 5282; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 5283; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 5284; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1 5285; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 5286; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 5287; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0 5288; AVX1-NEXT: retq 5289; 5290; AVX2-LABEL: uitofp_load_8i32_to_8f32: 5291; AVX2: # %bb.0: 5292; AVX2-NEXT: vmovdqa (%rdi), %ymm0 5293; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] 5294; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] 5295; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 5296; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] 5297; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] 5298; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11,-5.49764202E+11] 5299; AVX2-NEXT: vaddps %ymm2, %ymm0, %ymm0 5300; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0 5301; AVX2-NEXT: retq 5302; 5303; AVX512F-LABEL: uitofp_load_8i32_to_8f32: 5304; AVX512F: # %bb.0: 5305; AVX512F-NEXT: vmovaps (%rdi), %ymm0 5306; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 5307; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 5308; AVX512F-NEXT: retq 5309; 5310; AVX512VL-LABEL: uitofp_load_8i32_to_8f32: 5311; AVX512VL: # %bb.0: 5312; AVX512VL-NEXT: vcvtudq2ps (%rdi), %ymm0 5313; AVX512VL-NEXT: retq 5314; 5315; AVX512DQ-LABEL: uitofp_load_8i32_to_8f32: 5316; AVX512DQ: # %bb.0: 5317; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 5318; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 5319; AVX512DQ-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 5320; AVX512DQ-NEXT: retq 5321; 5322; AVX512VLDQ-LABEL: uitofp_load_8i32_to_8f32: 5323; AVX512VLDQ: # %bb.0: 5324; AVX512VLDQ-NEXT: vcvtudq2ps (%rdi), %ymm0 5325; AVX512VLDQ-NEXT: retq 5326 %ld = load <8 x i32>, <8 x i32> *%a 5327 %cvt = uitofp <8 x i32> %ld to <8 x float> 5328 ret <8 x float> %cvt 5329} 5330 5331define <8 x float> @uitofp_load_8i16_to_8f32(<8 x i16> *%a) { 5332; SSE2-LABEL: uitofp_load_8i16_to_8f32: 5333; SSE2: # %bb.0: 5334; SSE2-NEXT: movdqa (%rdi), %xmm1 5335; SSE2-NEXT: pxor %xmm2, %xmm2 5336; SSE2-NEXT: movdqa %xmm1, %xmm0 5337; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] 5338; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 5339; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] 5340; SSE2-NEXT: cvtdq2ps %xmm1, %xmm1 5341; SSE2-NEXT: retq 5342; 5343; SSE41-LABEL: uitofp_load_8i16_to_8f32: 5344; SSE41: # %bb.0: 5345; SSE41-NEXT: pmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 5346; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 5347; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 5348; SSE41-NEXT: cvtdq2ps %xmm1, %xmm1 5349; SSE41-NEXT: retq 5350; 5351; AVX1-LABEL: uitofp_load_8i16_to_8f32: 5352; AVX1: # %bb.0: 5353; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 5354; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero 5355; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 5356; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 5357; AVX1-NEXT: retq 5358; 5359; AVX2-LABEL: uitofp_load_8i16_to_8f32: 5360; AVX2: # %bb.0: 5361; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero 5362; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 5363; AVX2-NEXT: retq 5364; 5365; AVX512-LABEL: uitofp_load_8i16_to_8f32: 5366; AVX512: # %bb.0: 5367; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero 5368; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 5369; AVX512-NEXT: retq 5370 %ld = load <8 x i16>, <8 x i16> *%a 5371 %cvt = uitofp <8 x i16> %ld to <8 x float> 5372 ret <8 x float> %cvt 5373} 5374 5375define <8 x float> @uitofp_load_8i8_to_8f32(<8 x i8> *%a) { 5376; SSE2-LABEL: uitofp_load_8i8_to_8f32: 5377; SSE2: # %bb.0: 5378; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero 5379; SSE2-NEXT: pxor %xmm2, %xmm2 5380; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] 5381; SSE2-NEXT: movdqa %xmm1, %xmm0 5382; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] 5383; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 5384; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] 5385; SSE2-NEXT: cvtdq2ps %xmm1, %xmm1 5386; SSE2-NEXT: retq 5387; 5388; SSE41-LABEL: uitofp_load_8i8_to_8f32: 5389; SSE41: # %bb.0: 5390; SSE41-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 5391; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 5392; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 5393; SSE41-NEXT: cvtdq2ps %xmm1, %xmm1 5394; SSE41-NEXT: retq 5395; 5396; AVX1-LABEL: uitofp_load_8i8_to_8f32: 5397; AVX1: # %bb.0: 5398; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 5399; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero 5400; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 5401; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 5402; AVX1-NEXT: retq 5403; 5404; AVX2-LABEL: uitofp_load_8i8_to_8f32: 5405; AVX2: # %bb.0: 5406; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero 5407; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 5408; AVX2-NEXT: retq 5409; 5410; AVX512-LABEL: uitofp_load_8i8_to_8f32: 5411; AVX512: # %bb.0: 5412; AVX512-NEXT: vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero 5413; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 5414; AVX512-NEXT: retq 5415 %ld = load <8 x i8>, <8 x i8> *%a 5416 %cvt = uitofp <8 x i8> %ld to <8 x float> 5417 ret <8 x float> %cvt 5418} 5419 5420; 5421; Aggregates 5422; 5423 5424%Arguments = type <{ <8 x i8>, <8 x i16>, <8 x float>* }> 5425define void @aggregate_sitofp_8i16_to_8f32(%Arguments* nocapture readonly %a0) { 5426; SSE2-LABEL: aggregate_sitofp_8i16_to_8f32: 5427; SSE2: # %bb.0: 5428; SSE2-NEXT: movq 24(%rdi), %rax 5429; SSE2-NEXT: movdqu 8(%rdi), %xmm0 5430; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 5431; SSE2-NEXT: psrad $16, %xmm1 5432; SSE2-NEXT: cvtdq2ps %xmm1, %xmm1 5433; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7] 5434; SSE2-NEXT: psrad $16, %xmm0 5435; SSE2-NEXT: cvtdq2ps %xmm0, %xmm0 5436; SSE2-NEXT: movaps %xmm0, 16(%rax) 5437; SSE2-NEXT: movaps %xmm1, (%rax) 5438; SSE2-NEXT: retq 5439; 5440; SSE41-LABEL: aggregate_sitofp_8i16_to_8f32: 5441; SSE41: # %bb.0: 5442; SSE41-NEXT: movq 24(%rdi), %rax 5443; SSE41-NEXT: movdqu 8(%rdi), %xmm0 5444; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] 5445; SSE41-NEXT: pmovsxwd %xmm1, %xmm1 5446; SSE41-NEXT: cvtdq2ps %xmm1, %xmm1 5447; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 5448; SSE41-NEXT: cvtdq2ps %xmm0, %xmm0 5449; SSE41-NEXT: movaps %xmm0, (%rax) 5450; SSE41-NEXT: movaps %xmm1, 16(%rax) 5451; SSE41-NEXT: retq 5452; 5453; AVX1-LABEL: aggregate_sitofp_8i16_to_8f32: 5454; AVX1: # %bb.0: 5455; AVX1-NEXT: movq 24(%rdi), %rax 5456; AVX1-NEXT: vpmovsxwd 16(%rdi), %xmm0 5457; AVX1-NEXT: vpmovsxwd 8(%rdi), %xmm1 5458; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 5459; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 5460; AVX1-NEXT: vmovaps %ymm0, (%rax) 5461; AVX1-NEXT: vzeroupper 5462; AVX1-NEXT: retq 5463; 5464; AVX2-LABEL: aggregate_sitofp_8i16_to_8f32: 5465; AVX2: # %bb.0: 5466; AVX2-NEXT: movq 24(%rdi), %rax 5467; AVX2-NEXT: vpmovsxwd 8(%rdi), %ymm0 5468; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 5469; AVX2-NEXT: vmovaps %ymm0, (%rax) 5470; AVX2-NEXT: vzeroupper 5471; AVX2-NEXT: retq 5472; 5473; AVX512-LABEL: aggregate_sitofp_8i16_to_8f32: 5474; AVX512: # %bb.0: 5475; AVX512-NEXT: movq 24(%rdi), %rax 5476; AVX512-NEXT: vpmovsxwd 8(%rdi), %ymm0 5477; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 5478; AVX512-NEXT: vmovaps %ymm0, (%rax) 5479; AVX512-NEXT: vzeroupper 5480; AVX512-NEXT: retq 5481 %1 = load %Arguments, %Arguments* %a0, align 1 5482 %2 = extractvalue %Arguments %1, 1 5483 %3 = extractvalue %Arguments %1, 2 5484 %4 = sitofp <8 x i16> %2 to <8 x float> 5485 store <8 x float> %4, <8 x float>* %3, align 32 5486 ret void 5487} 5488 5489define <2 x double> @sitofp_i32_to_2f64(<2 x double> %a0, i32 %a1) nounwind { 5490; SSE-LABEL: sitofp_i32_to_2f64: 5491; SSE: # %bb.0: 5492; SSE-NEXT: cvtsi2sdl %edi, %xmm0 5493; SSE-NEXT: retq 5494; 5495; AVX-LABEL: sitofp_i32_to_2f64: 5496; AVX: # %bb.0: 5497; AVX-NEXT: vcvtsi2sdl %edi, %xmm0, %xmm0 5498; AVX-NEXT: retq 5499 %cvt = sitofp i32 %a1 to double 5500 %res = insertelement <2 x double> %a0, double %cvt, i32 0 5501 ret <2 x double> %res 5502} 5503 5504define <4 x float> @sitofp_i32_to_4f32(<4 x float> %a0, i32 %a1) nounwind { 5505; SSE-LABEL: sitofp_i32_to_4f32: 5506; SSE: # %bb.0: 5507; SSE-NEXT: cvtsi2ssl %edi, %xmm0 5508; SSE-NEXT: retq 5509; 5510; AVX-LABEL: sitofp_i32_to_4f32: 5511; AVX: # %bb.0: 5512; AVX-NEXT: vcvtsi2ssl %edi, %xmm0, %xmm0 5513; AVX-NEXT: retq 5514 %cvt = sitofp i32 %a1 to float 5515 %res = insertelement <4 x float> %a0, float %cvt, i32 0 5516 ret <4 x float> %res 5517} 5518 5519define <2 x double> @sitofp_i64_to_2f64(<2 x double> %a0, i64 %a1) nounwind { 5520; SSE-LABEL: sitofp_i64_to_2f64: 5521; SSE: # %bb.0: 5522; SSE-NEXT: cvtsi2sdq %rdi, %xmm0 5523; SSE-NEXT: retq 5524; 5525; AVX-LABEL: sitofp_i64_to_2f64: 5526; AVX: # %bb.0: 5527; AVX-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 5528; AVX-NEXT: retq 5529 %cvt = sitofp i64 %a1 to double 5530 %res = insertelement <2 x double> %a0, double %cvt, i32 0 5531 ret <2 x double> %res 5532} 5533 5534define <4 x float> @sitofp_i64_to_4f32(<4 x float> %a0, i64 %a1) nounwind { 5535; SSE-LABEL: sitofp_i64_to_4f32: 5536; SSE: # %bb.0: 5537; SSE-NEXT: cvtsi2ssq %rdi, %xmm0 5538; SSE-NEXT: retq 5539; 5540; AVX-LABEL: sitofp_i64_to_4f32: 5541; AVX: # %bb.0: 5542; AVX-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 5543; AVX-NEXT: retq 5544 %cvt = sitofp i64 %a1 to float 5545 %res = insertelement <4 x float> %a0, float %cvt, i32 0 5546 ret <4 x float> %res 5547} 5548 5549; Extract from int vector and convert to FP. 5550 5551define float @extract0_sitofp_v4i32_f32(<4 x i32> %x) nounwind { 5552; SSE-LABEL: extract0_sitofp_v4i32_f32: 5553; SSE: # %bb.0: 5554; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 5555; SSE-NEXT: retq 5556; 5557; AVX-LABEL: extract0_sitofp_v4i32_f32: 5558; AVX: # %bb.0: 5559; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 5560; AVX-NEXT: retq 5561 %e = extractelement <4 x i32> %x, i32 0 5562 %r = sitofp i32 %e to float 5563 ret float %r 5564} 5565 5566define float @extract0_sitofp_v4i32_f32i_multiuse1(<4 x i32> %x) nounwind { 5567; SSE-LABEL: extract0_sitofp_v4i32_f32i_multiuse1: 5568; SSE: # %bb.0: 5569; SSE-NEXT: movd %xmm0, %eax 5570; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 5571; SSE-NEXT: incl %eax 5572; SSE-NEXT: cvtsi2ssl %eax, %xmm1 5573; SSE-NEXT: divss %xmm1, %xmm0 5574; SSE-NEXT: retq 5575; 5576; AVX-LABEL: extract0_sitofp_v4i32_f32i_multiuse1: 5577; AVX: # %bb.0: 5578; AVX-NEXT: vmovd %xmm0, %eax 5579; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 5580; AVX-NEXT: incl %eax 5581; AVX-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm1 5582; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0 5583; AVX-NEXT: retq 5584 %e = extractelement <4 x i32> %x, i32 0 5585 %f = sitofp i32 %e to float 5586 %e1 = add i32 %e, 1 5587 %f1 = sitofp i32 %e1 to float 5588 %r = fdiv float %f, %f1 5589 ret float %r 5590} 5591 5592define float @extract0_sitofp_v4i32_f32_multiuse2(<4 x i32> %x, i32* %p) nounwind { 5593; SSE-LABEL: extract0_sitofp_v4i32_f32_multiuse2: 5594; SSE: # %bb.0: 5595; SSE-NEXT: cvtdq2ps %xmm0, %xmm1 5596; SSE-NEXT: movss %xmm0, (%rdi) 5597; SSE-NEXT: movaps %xmm1, %xmm0 5598; SSE-NEXT: retq 5599; 5600; AVX-LABEL: extract0_sitofp_v4i32_f32_multiuse2: 5601; AVX: # %bb.0: 5602; AVX-NEXT: vcvtdq2ps %xmm0, %xmm1 5603; AVX-NEXT: vmovss %xmm0, (%rdi) 5604; AVX-NEXT: vmovaps %xmm1, %xmm0 5605; AVX-NEXT: retq 5606 %e = extractelement <4 x i32> %x, i32 0 5607 %r = sitofp i32 %e to float 5608 store i32 %e, i32* %p 5609 ret float %r 5610} 5611 5612define double @extract0_sitofp_v4i32_f64(<4 x i32> %x) nounwind { 5613; SSE-LABEL: extract0_sitofp_v4i32_f64: 5614; SSE: # %bb.0: 5615; SSE-NEXT: movd %xmm0, %eax 5616; SSE-NEXT: xorps %xmm0, %xmm0 5617; SSE-NEXT: cvtsi2sdl %eax, %xmm0 5618; SSE-NEXT: retq 5619; 5620; AVX-LABEL: extract0_sitofp_v4i32_f64: 5621; AVX: # %bb.0: 5622; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 5623; AVX-NEXT: retq 5624 %e = extractelement <4 x i32> %x, i32 0 5625 %r = sitofp i32 %e to double 5626 ret double %r 5627} 5628 5629define float @extract0_uitofp_v4i32_f32(<4 x i32> %x) nounwind { 5630; SSE-LABEL: extract0_uitofp_v4i32_f32: 5631; SSE: # %bb.0: 5632; SSE-NEXT: movd %xmm0, %eax 5633; SSE-NEXT: xorps %xmm0, %xmm0 5634; SSE-NEXT: cvtsi2ssq %rax, %xmm0 5635; SSE-NEXT: retq 5636; 5637; VEX-LABEL: extract0_uitofp_v4i32_f32: 5638; VEX: # %bb.0: 5639; VEX-NEXT: vmovd %xmm0, %eax 5640; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm0 5641; VEX-NEXT: retq 5642; 5643; AVX512F-LABEL: extract0_uitofp_v4i32_f32: 5644; AVX512F: # %bb.0: 5645; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 5646; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 5647; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5648; AVX512F-NEXT: vzeroupper 5649; AVX512F-NEXT: retq 5650; 5651; AVX512VL-LABEL: extract0_uitofp_v4i32_f32: 5652; AVX512VL: # %bb.0: 5653; AVX512VL-NEXT: vcvtudq2ps %xmm0, %xmm0 5654; AVX512VL-NEXT: retq 5655; 5656; AVX512DQ-LABEL: extract0_uitofp_v4i32_f32: 5657; AVX512DQ: # %bb.0: 5658; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 5659; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 5660; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5661; AVX512DQ-NEXT: vzeroupper 5662; AVX512DQ-NEXT: retq 5663; 5664; AVX512VLDQ-LABEL: extract0_uitofp_v4i32_f32: 5665; AVX512VLDQ: # %bb.0: 5666; AVX512VLDQ-NEXT: vcvtudq2ps %xmm0, %xmm0 5667; AVX512VLDQ-NEXT: retq 5668 %e = extractelement <4 x i32> %x, i32 0 5669 %r = uitofp i32 %e to float 5670 ret float %r 5671} 5672 5673define double @extract0_uitofp_v4i32_f64(<4 x i32> %x) nounwind { 5674; SSE-LABEL: extract0_uitofp_v4i32_f64: 5675; SSE: # %bb.0: 5676; SSE-NEXT: movd %xmm0, %eax 5677; SSE-NEXT: xorps %xmm0, %xmm0 5678; SSE-NEXT: cvtsi2sdq %rax, %xmm0 5679; SSE-NEXT: retq 5680; 5681; VEX-LABEL: extract0_uitofp_v4i32_f64: 5682; VEX: # %bb.0: 5683; VEX-NEXT: vmovd %xmm0, %eax 5684; VEX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm0 5685; VEX-NEXT: retq 5686; 5687; AVX512F-LABEL: extract0_uitofp_v4i32_f64: 5688; AVX512F: # %bb.0: 5689; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 5690; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 5691; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5692; AVX512F-NEXT: vzeroupper 5693; AVX512F-NEXT: retq 5694; 5695; AVX512VL-LABEL: extract0_uitofp_v4i32_f64: 5696; AVX512VL: # %bb.0: 5697; AVX512VL-NEXT: vcvtudq2pd %xmm0, %xmm0 5698; AVX512VL-NEXT: retq 5699; 5700; AVX512DQ-LABEL: extract0_uitofp_v4i32_f64: 5701; AVX512DQ: # %bb.0: 5702; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 5703; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 5704; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5705; AVX512DQ-NEXT: vzeroupper 5706; AVX512DQ-NEXT: retq 5707; 5708; AVX512VLDQ-LABEL: extract0_uitofp_v4i32_f64: 5709; AVX512VLDQ: # %bb.0: 5710; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %xmm0 5711; AVX512VLDQ-NEXT: retq 5712 %e = extractelement <4 x i32> %x, i32 0 5713 %r = uitofp i32 %e to double 5714 ret double %r 5715} 5716 5717; Extract non-zero element from int vector and convert to FP. 5718 5719define float @extract3_sitofp_v4i32_f32(<4 x i32> %x) nounwind { 5720; SSE-LABEL: extract3_sitofp_v4i32_f32: 5721; SSE: # %bb.0: 5722; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] 5723; SSE-NEXT: cvtdq2ps %xmm0, %xmm0 5724; SSE-NEXT: retq 5725; 5726; AVX-LABEL: extract3_sitofp_v4i32_f32: 5727; AVX: # %bb.0: 5728; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5729; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 5730; AVX-NEXT: retq 5731 %e = extractelement <4 x i32> %x, i32 3 5732 %r = sitofp i32 %e to float 5733 ret float %r 5734} 5735 5736define double @extract3_sitofp_v4i32_f64(<4 x i32> %x) nounwind { 5737; SSE2-LABEL: extract3_sitofp_v4i32_f64: 5738; SSE2: # %bb.0: 5739; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] 5740; SSE2-NEXT: movd %xmm0, %eax 5741; SSE2-NEXT: xorps %xmm0, %xmm0 5742; SSE2-NEXT: cvtsi2sdl %eax, %xmm0 5743; SSE2-NEXT: retq 5744; 5745; SSE41-LABEL: extract3_sitofp_v4i32_f64: 5746; SSE41: # %bb.0: 5747; SSE41-NEXT: extractps $3, %xmm0, %eax 5748; SSE41-NEXT: xorps %xmm0, %xmm0 5749; SSE41-NEXT: cvtsi2sdl %eax, %xmm0 5750; SSE41-NEXT: retq 5751; 5752; AVX-LABEL: extract3_sitofp_v4i32_f64: 5753; AVX: # %bb.0: 5754; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5755; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 5756; AVX-NEXT: retq 5757 %e = extractelement <4 x i32> %x, i32 3 5758 %r = sitofp i32 %e to double 5759 ret double %r 5760} 5761 5762define float @extract3_uitofp_v4i32_f32(<4 x i32> %x) nounwind { 5763; SSE2-LABEL: extract3_uitofp_v4i32_f32: 5764; SSE2: # %bb.0: 5765; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] 5766; SSE2-NEXT: movd %xmm0, %eax 5767; SSE2-NEXT: xorps %xmm0, %xmm0 5768; SSE2-NEXT: cvtsi2ssq %rax, %xmm0 5769; SSE2-NEXT: retq 5770; 5771; SSE41-LABEL: extract3_uitofp_v4i32_f32: 5772; SSE41: # %bb.0: 5773; SSE41-NEXT: extractps $3, %xmm0, %eax 5774; SSE41-NEXT: xorps %xmm0, %xmm0 5775; SSE41-NEXT: cvtsi2ssq %rax, %xmm0 5776; SSE41-NEXT: retq 5777; 5778; VEX-LABEL: extract3_uitofp_v4i32_f32: 5779; VEX: # %bb.0: 5780; VEX-NEXT: vextractps $3, %xmm0, %eax 5781; VEX-NEXT: vcvtsi2ssq %rax, %xmm1, %xmm0 5782; VEX-NEXT: retq 5783; 5784; AVX512F-LABEL: extract3_uitofp_v4i32_f32: 5785; AVX512F: # %bb.0: 5786; AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5787; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 5788; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5789; AVX512F-NEXT: vzeroupper 5790; AVX512F-NEXT: retq 5791; 5792; AVX512VL-LABEL: extract3_uitofp_v4i32_f32: 5793; AVX512VL: # %bb.0: 5794; AVX512VL-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5795; AVX512VL-NEXT: vcvtudq2ps %xmm0, %xmm0 5796; AVX512VL-NEXT: retq 5797; 5798; AVX512DQ-LABEL: extract3_uitofp_v4i32_f32: 5799; AVX512DQ: # %bb.0: 5800; AVX512DQ-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5801; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 5802; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5803; AVX512DQ-NEXT: vzeroupper 5804; AVX512DQ-NEXT: retq 5805; 5806; AVX512VLDQ-LABEL: extract3_uitofp_v4i32_f32: 5807; AVX512VLDQ: # %bb.0: 5808; AVX512VLDQ-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5809; AVX512VLDQ-NEXT: vcvtudq2ps %xmm0, %xmm0 5810; AVX512VLDQ-NEXT: retq 5811 %e = extractelement <4 x i32> %x, i32 3 5812 %r = uitofp i32 %e to float 5813 ret float %r 5814} 5815 5816define double @extract3_uitofp_v4i32_f64(<4 x i32> %x) nounwind { 5817; SSE2-LABEL: extract3_uitofp_v4i32_f64: 5818; SSE2: # %bb.0: 5819; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] 5820; SSE2-NEXT: movd %xmm0, %eax 5821; SSE2-NEXT: xorps %xmm0, %xmm0 5822; SSE2-NEXT: cvtsi2sdq %rax, %xmm0 5823; SSE2-NEXT: retq 5824; 5825; SSE41-LABEL: extract3_uitofp_v4i32_f64: 5826; SSE41: # %bb.0: 5827; SSE41-NEXT: extractps $3, %xmm0, %eax 5828; SSE41-NEXT: xorps %xmm0, %xmm0 5829; SSE41-NEXT: cvtsi2sdq %rax, %xmm0 5830; SSE41-NEXT: retq 5831; 5832; VEX-LABEL: extract3_uitofp_v4i32_f64: 5833; VEX: # %bb.0: 5834; VEX-NEXT: vextractps $3, %xmm0, %eax 5835; VEX-NEXT: vcvtsi2sdq %rax, %xmm1, %xmm0 5836; VEX-NEXT: retq 5837; 5838; AVX512F-LABEL: extract3_uitofp_v4i32_f64: 5839; AVX512F: # %bb.0: 5840; AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5841; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 5842; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5843; AVX512F-NEXT: vzeroupper 5844; AVX512F-NEXT: retq 5845; 5846; AVX512VL-LABEL: extract3_uitofp_v4i32_f64: 5847; AVX512VL: # %bb.0: 5848; AVX512VL-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5849; AVX512VL-NEXT: vcvtudq2pd %xmm0, %xmm0 5850; AVX512VL-NEXT: retq 5851; 5852; AVX512DQ-LABEL: extract3_uitofp_v4i32_f64: 5853; AVX512DQ: # %bb.0: 5854; AVX512DQ-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5855; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 5856; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 5857; AVX512DQ-NEXT: vzeroupper 5858; AVX512DQ-NEXT: retq 5859; 5860; AVX512VLDQ-LABEL: extract3_uitofp_v4i32_f64: 5861; AVX512VLDQ: # %bb.0: 5862; AVX512VLDQ-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 5863; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %xmm0 5864; AVX512VLDQ-NEXT: retq 5865 %e = extractelement <4 x i32> %x, i32 3 5866 %r = uitofp i32 %e to double 5867 ret double %r 5868} 5869 5870