1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -march=x86 -mattr=+sse2,+ssse3 | FileCheck %s
3; There are no MMX operations in @t1
4
5define void  @t1(i32 %a, x86_mmx* %P) nounwind {
6; CHECK-LABEL: t1:
7; CHECK:       # BB#0:
8; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
9; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
10; CHECK-NEXT:    shll $12, %ecx
11; CHECK-NEXT:    movd %ecx, %xmm0
12; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
13; CHECK-NEXT:    movq %xmm0, (%eax)
14; CHECK-NEXT:    retl
15 %tmp12 = shl i32 %a, 12
16 %tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1
17 %tmp22 = insertelement <2 x i32> %tmp21, i32 0, i32 0
18 %tmp23 = bitcast <2 x i32> %tmp22 to x86_mmx
19 store x86_mmx %tmp23, x86_mmx* %P
20 ret void
21}
22
23define <4 x float> @t2(<4 x float>* %P) nounwind {
24; CHECK-LABEL: t2:
25; CHECK:       # BB#0:
26; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
27; CHECK-NEXT:    movaps (%eax), %xmm1
28; CHECK-NEXT:    xorps %xmm0, %xmm0
29; CHECK-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
30; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
31; CHECK-NEXT:    retl
32  %tmp1 = load <4 x float>, <4 x float>* %P
33  %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
34  ret <4 x float> %tmp2
35}
36
37define <4 x float> @t3(<4 x float>* %P) nounwind {
38; CHECK-LABEL: t3:
39; CHECK:       # BB#0:
40; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
41; CHECK-NEXT:    movapd (%eax), %xmm0
42; CHECK-NEXT:    xorpd %xmm1, %xmm1
43; CHECK-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
44; CHECK-NEXT:    retl
45  %tmp1 = load <4 x float>, <4 x float>* %P
46  %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
47  ret <4 x float> %tmp2
48}
49
50define <4 x float> @t4(<4 x float>* %P) nounwind {
51; CHECK-LABEL: t4:
52; CHECK:       # BB#0:
53; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
54; CHECK-NEXT:    movaps (%eax), %xmm0
55; CHECK-NEXT:    xorps %xmm1, %xmm1
56; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[1,0]
57; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[2,3]
58; CHECK-NEXT:    retl
59  %tmp1 = load <4 x float>, <4 x float>* %P
60  %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
61  ret <4 x float> %tmp2
62}
63
64define <16 x i8> @t5(<16 x i8> %x) nounwind {
65; CHECK-LABEL: t5:
66; CHECK:       # BB#0:
67; CHECK-NEXT:    psrlw $8, %xmm0
68; CHECK-NEXT:    retl
69  %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
70  ret <16 x i8> %s
71}
72
73define <16 x i8> @t6(<16 x i8> %x) nounwind {
74; CHECK-LABEL: t6:
75; CHECK:       # BB#0:
76; CHECK-NEXT:    psrlw $8, %xmm0
77; CHECK-NEXT:    retl
78  %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
79  ret <16 x i8> %s
80}
81
82define <16 x i8> @t7(<16 x i8> %x) nounwind {
83; CHECK-LABEL: t7:
84; CHECK:       # BB#0:
85; CHECK-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2]
86; CHECK-NEXT:    retl
87  %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2>
88  ret <16 x i8> %s
89}
90
91define <16 x i8> @t8(<16 x i8> %x) nounwind {
92; CHECK-LABEL: t8:
93; CHECK:       # BB#0:
94; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
95; CHECK-NEXT:    retl
96  %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
97  ret <16 x i8> %s
98}
99
100define <16 x i8> @t9(<16 x i8> %x) nounwind {
101; CHECK-LABEL: t9:
102; CHECK:       # BB#0:
103; CHECK-NEXT:    psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero
104; CHECK-NEXT:    retl
105  %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 14, i32 undef, i32 undef>
106  ret <16 x i8> %s
107}
108