1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X32
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
4
5define i32 @test0(<1 x i64>* %v4) nounwind {
6; X32-LABEL: test0:
7; X32:       # BB#0: # %entry
8; X32-NEXT:    pushl %ebp
9; X32-NEXT:    movl %esp, %ebp
10; X32-NEXT:    andl $-8, %esp
11; X32-NEXT:    subl $24, %esp
12; X32-NEXT:    movl 8(%ebp), %eax
13; X32-NEXT:    movl (%eax), %ecx
14; X32-NEXT:    movl 4(%eax), %eax
15; X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
16; X32-NEXT:    movl %ecx, (%esp)
17; X32-NEXT:    pshufw $238, (%esp), %mm0 # mm0 = mem[2,3,2,3]
18; X32-NEXT:    movq %mm0, {{[0-9]+}}(%esp)
19; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
20; X32-NEXT:    addl $32, %eax
21; X32-NEXT:    movl %ebp, %esp
22; X32-NEXT:    popl %ebp
23; X32-NEXT:    retl
24;
25; X64-LABEL: test0:
26; X64:       # BB#0: # %entry
27; X64-NEXT:    pshufw $238, (%rdi), %mm0 # mm0 = mem[2,3,2,3]
28; X64-NEXT:    movd %mm0, %eax
29; X64-NEXT:    addl $32, %eax
30; X64-NEXT:    retq
31entry:
32  %v5 = load <1 x i64>, <1 x i64>* %v4, align 8
33  %v12 = bitcast <1 x i64> %v5 to <4 x i16>
34  %v13 = bitcast <4 x i16> %v12 to x86_mmx
35  %v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
36  %v15 = bitcast x86_mmx %v14 to <4 x i16>
37  %v16 = bitcast <4 x i16> %v15 to <1 x i64>
38  %v17 = extractelement <1 x i64> %v16, i32 0
39  %v18 = bitcast i64 %v17 to <2 x i32>
40  %v19 = extractelement <2 x i32> %v18, i32 0
41  %v20 = add i32 %v19, 32
42  ret i32 %v20
43}
44
45define i32 @test1(i32* nocapture readonly %ptr) nounwind {
46; X32-LABEL: test1:
47; X32:       # BB#0: # %entry
48; X32-NEXT:    pushl %ebp
49; X32-NEXT:    movl %esp, %ebp
50; X32-NEXT:    andl $-8, %esp
51; X32-NEXT:    subl $16, %esp
52; X32-NEXT:    movl 8(%ebp), %eax
53; X32-NEXT:    movd (%eax), %mm0
54; X32-NEXT:    pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
55; X32-NEXT:    movq %mm0, (%esp)
56; X32-NEXT:    movl (%esp), %eax
57; X32-NEXT:    emms
58; X32-NEXT:    movl %ebp, %esp
59; X32-NEXT:    popl %ebp
60; X32-NEXT:    retl
61;
62; X64-LABEL: test1:
63; X64:       # BB#0: # %entry
64; X64-NEXT:    movd (%rdi), %mm0
65; X64-NEXT:    pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
66; X64-NEXT:    movd %mm0, %eax
67; X64-NEXT:    emms
68; X64-NEXT:    retq
69entry:
70  %0 = load i32, i32* %ptr, align 4
71  %1 = insertelement <2 x i32> undef, i32 %0, i32 0
72  %2 = insertelement <2 x i32> %1, i32 0, i32 1
73  %3 = bitcast <2 x i32> %2 to x86_mmx
74  %4 = bitcast x86_mmx %3 to i64
75  %5 = bitcast i64 %4 to <4 x i16>
76  %6 = bitcast <4 x i16> %5 to x86_mmx
77  %7 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %6, i8 -24)
78  %8 = bitcast x86_mmx %7 to <4 x i16>
79  %9 = bitcast <4 x i16> %8 to <1 x i64>
80  %10 = extractelement <1 x i64> %9, i32 0
81  %11 = bitcast i64 %10 to <2 x i32>
82  %12 = extractelement <2 x i32> %11, i32 0
83  tail call void @llvm.x86.mmx.emms()
84  ret i32 %12
85}
86
87define i32 @test2(i32* nocapture readonly %ptr) nounwind {
88; X32-LABEL: test2:
89; X32:       # BB#0: # %entry
90; X32-NEXT:    pushl %ebp
91; X32-NEXT:    movl %esp, %ebp
92; X32-NEXT:    andl $-8, %esp
93; X32-NEXT:    subl $16, %esp
94; X32-NEXT:    movl 8(%ebp), %eax
95; X32-NEXT:    pshufw $232, (%eax), %mm0 # mm0 = mem[0,2,2,3]
96; X32-NEXT:    movq %mm0, (%esp)
97; X32-NEXT:    movl (%esp), %eax
98; X32-NEXT:    emms
99; X32-NEXT:    movl %ebp, %esp
100; X32-NEXT:    popl %ebp
101; X32-NEXT:    retl
102;
103; X64-LABEL: test2:
104; X64:       # BB#0: # %entry
105; X64-NEXT:    pshufw $232, (%rdi), %mm0 # mm0 = mem[0,2,2,3]
106; X64-NEXT:    movd %mm0, %eax
107; X64-NEXT:    emms
108; X64-NEXT:    retq
109entry:
110  %0 = bitcast i32* %ptr to x86_mmx*
111  %1 = load x86_mmx, x86_mmx* %0, align 8
112  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
113  %3 = bitcast x86_mmx %2 to <4 x i16>
114  %4 = bitcast <4 x i16> %3 to <1 x i64>
115  %5 = extractelement <1 x i64> %4, i32 0
116  %6 = bitcast i64 %5 to <2 x i32>
117  %7 = extractelement <2 x i32> %6, i32 0
118  tail call void @llvm.x86.mmx.emms()
119  ret i32 %7
120}
121
122define i32 @test3(x86_mmx %a) nounwind {
123; X32-LABEL: test3:
124; X32:       # BB#0:
125; X32-NEXT:    movd %mm0, %eax
126; X32-NEXT:    retl
127;
128; X64-LABEL: test3:
129; X64:       # BB#0:
130; X64-NEXT:    movd %mm0, %eax
131; X64-NEXT:    retq
132  %tmp0 = bitcast x86_mmx %a to <2 x i32>
133  %tmp1 = extractelement <2 x i32> %tmp0, i32 0
134  ret i32 %tmp1
135}
136
137; Verify we don't muck with extractelts from the upper lane.
138define i32 @test4(x86_mmx %a) nounwind {
139; X32-LABEL: test4:
140; X32:       # BB#0:
141; X32-NEXT:    pushl %ebp
142; X32-NEXT:    movl %esp, %ebp
143; X32-NEXT:    andl $-8, %esp
144; X32-NEXT:    subl $8, %esp
145; X32-NEXT:    movq %mm0, (%esp)
146; X32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
147; X32-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,0,1]
148; X32-NEXT:    movd %xmm0, %eax
149; X32-NEXT:    movl %ebp, %esp
150; X32-NEXT:    popl %ebp
151; X32-NEXT:    retl
152;
153; X64-LABEL: test4:
154; X64:       # BB#0:
155; X64-NEXT:    movq %mm0, -{{[0-9]+}}(%rsp)
156; X64-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
157; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,0,1]
158; X64-NEXT:    movd %xmm0, %eax
159; X64-NEXT:    retq
160  %tmp0 = bitcast x86_mmx %a to <2 x i32>
161  %tmp1 = extractelement <2 x i32> %tmp0, i32 1
162  ret i32 %tmp1
163}
164
165declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
166declare void @llvm.x86.mmx.emms()
167