1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+avx | FileCheck %s
3; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE
4
5define <8 x float> @cvt_v8i8_v8f32(<8 x i8> %src) {
6; CHECK-LABEL: cvt_v8i8_v8f32:
7; CHECK:       ## %bb.0:
8; CHECK-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4,4,5,5,6,6,7,7]
9; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
10; CHECK-NEXT:    vpslld $24, %xmm0, %xmm0
11; CHECK-NEXT:    vpsrad $24, %xmm0, %xmm0
12; CHECK-NEXT:    vpslld $24, %xmm1, %xmm1
13; CHECK-NEXT:    vpsrad $24, %xmm1, %xmm1
14; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
15; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
16; CHECK-NEXT:    retl
17;
18; CHECK-WIDE-LABEL: cvt_v8i8_v8f32:
19; CHECK-WIDE:       ## %bb.0:
20; CHECK-WIDE-NEXT:    vpmovsxbd %xmm0, %xmm1
21; CHECK-WIDE-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
22; CHECK-WIDE-NEXT:    vpmovsxbd %xmm0, %xmm0
23; CHECK-WIDE-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
24; CHECK-WIDE-NEXT:    vcvtdq2ps %ymm0, %ymm0
25; CHECK-WIDE-NEXT:    retl
26  %res = sitofp <8 x i8> %src to <8 x float>
27  ret <8 x float> %res
28}
29
30define <8 x float> @cvt_v8i16_v8f32(<8 x i16> %src) {
31; CHECK-LABEL: cvt_v8i16_v8f32:
32; CHECK:       ## %bb.0:
33; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm1
34; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
35; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm0
36; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
37; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
38; CHECK-NEXT:    retl
39;
40; CHECK-WIDE-LABEL: cvt_v8i16_v8f32:
41; CHECK-WIDE:       ## %bb.0:
42; CHECK-WIDE-NEXT:    vpmovsxwd %xmm0, %xmm1
43; CHECK-WIDE-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
44; CHECK-WIDE-NEXT:    vpmovsxwd %xmm0, %xmm0
45; CHECK-WIDE-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
46; CHECK-WIDE-NEXT:    vcvtdq2ps %ymm0, %ymm0
47; CHECK-WIDE-NEXT:    retl
48  %res = sitofp <8 x i16> %src to <8 x float>
49  ret <8 x float> %res
50}
51
52define <4 x float> @cvt_v4i8_v4f32(<4 x i8> %src) {
53; CHECK-LABEL: cvt_v4i8_v4f32:
54; CHECK:       ## %bb.0:
55; CHECK-NEXT:    vpslld $24, %xmm0, %xmm0
56; CHECK-NEXT:    vpsrad $24, %xmm0, %xmm0
57; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
58; CHECK-NEXT:    retl
59;
60; CHECK-WIDE-LABEL: cvt_v4i8_v4f32:
61; CHECK-WIDE:       ## %bb.0:
62; CHECK-WIDE-NEXT:    vpmovsxbd %xmm0, %xmm0
63; CHECK-WIDE-NEXT:    vcvtdq2ps %xmm0, %xmm0
64; CHECK-WIDE-NEXT:    retl
65  %res = sitofp <4 x i8> %src to <4 x float>
66  ret <4 x float> %res
67}
68
69define <4 x float> @cvt_v4i16_v4f32(<4 x i16> %src) {
70; CHECK-LABEL: cvt_v4i16_v4f32:
71; CHECK:       ## %bb.0:
72; CHECK-NEXT:    vpslld $16, %xmm0, %xmm0
73; CHECK-NEXT:    vpsrad $16, %xmm0, %xmm0
74; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
75; CHECK-NEXT:    retl
76;
77; CHECK-WIDE-LABEL: cvt_v4i16_v4f32:
78; CHECK-WIDE:       ## %bb.0:
79; CHECK-WIDE-NEXT:    vpmovsxwd %xmm0, %xmm0
80; CHECK-WIDE-NEXT:    vcvtdq2ps %xmm0, %xmm0
81; CHECK-WIDE-NEXT:    retl
82  %res = sitofp <4 x i16> %src to <4 x float>
83  ret <4 x float> %res
84}
85
86define <8 x float> @cvt_v8u8_v8f32(<8 x i8> %src) {
87; CHECK-LABEL: cvt_v8u8_v8f32:
88; CHECK:       ## %bb.0:
89; CHECK-NEXT:    vpand LCPI4_0, %xmm0, %xmm0
90; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
91; CHECK-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
92; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
93; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
94; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
95; CHECK-NEXT:    retl
96;
97; CHECK-WIDE-LABEL: cvt_v8u8_v8f32:
98; CHECK-WIDE:       ## %bb.0:
99; CHECK-WIDE-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
100; CHECK-WIDE-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
101; CHECK-WIDE-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
102; CHECK-WIDE-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
103; CHECK-WIDE-NEXT:    vcvtdq2ps %ymm0, %ymm0
104; CHECK-WIDE-NEXT:    retl
105  %res = uitofp <8 x i8> %src to <8 x float>
106  ret <8 x float> %res
107}
108
109define <8 x float> @cvt_v8u16_v8f32(<8 x i16> %src) {
110; CHECK-LABEL: cvt_v8u16_v8f32:
111; CHECK:       ## %bb.0:
112; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
113; CHECK-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
114; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
115; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
116; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
117; CHECK-NEXT:    retl
118;
119; CHECK-WIDE-LABEL: cvt_v8u16_v8f32:
120; CHECK-WIDE:       ## %bb.0:
121; CHECK-WIDE-NEXT:    vpxor %xmm1, %xmm1, %xmm1
122; CHECK-WIDE-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
123; CHECK-WIDE-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
124; CHECK-WIDE-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
125; CHECK-WIDE-NEXT:    vcvtdq2ps %ymm0, %ymm0
126; CHECK-WIDE-NEXT:    retl
127  %res = uitofp <8 x i16> %src to <8 x float>
128  ret <8 x float> %res
129}
130
131define <4 x float> @cvt_v4u8_v4f32(<4 x i8> %src) {
132; CHECK-LABEL: cvt_v4u8_v4f32:
133; CHECK:       ## %bb.0:
134; CHECK-NEXT:    vandps LCPI6_0, %xmm0, %xmm0
135; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
136; CHECK-NEXT:    retl
137;
138; CHECK-WIDE-LABEL: cvt_v4u8_v4f32:
139; CHECK-WIDE:       ## %bb.0:
140; CHECK-WIDE-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
141; CHECK-WIDE-NEXT:    vcvtdq2ps %xmm0, %xmm0
142; CHECK-WIDE-NEXT:    retl
143  %res = uitofp <4 x i8> %src to <4 x float>
144  ret <4 x float> %res
145}
146
147define <4 x float> @cvt_v4u16_v4f32(<4 x i16> %src) {
148; CHECK-LABEL: cvt_v4u16_v4f32:
149; CHECK:       ## %bb.0:
150; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
151; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
152; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
153; CHECK-NEXT:    retl
154;
155; CHECK-WIDE-LABEL: cvt_v4u16_v4f32:
156; CHECK-WIDE:       ## %bb.0:
157; CHECK-WIDE-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
158; CHECK-WIDE-NEXT:    vcvtdq2ps %xmm0, %xmm0
159; CHECK-WIDE-NEXT:    retl
160  %res = uitofp <4 x i16> %src to <4 x float>
161  ret <4 x float> %res
162}
163
164define <8 x i8> @cvt_v8f32_v8i8(<8 x float> %src) {
165; CHECK-LABEL: cvt_v8f32_v8i8:
166; CHECK:       ## %bb.0:
167; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
168; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
169; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
170; CHECK-NEXT:    vzeroupper
171; CHECK-NEXT:    retl
172;
173; CHECK-WIDE-LABEL: cvt_v8f32_v8i8:
174; CHECK-WIDE:       ## %bb.0:
175; CHECK-WIDE-NEXT:    vcvttps2dq %ymm0, %ymm0
176; CHECK-WIDE-NEXT:    vextractf128 $1, %ymm0, %xmm1
177; CHECK-WIDE-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
178; CHECK-WIDE-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
179; CHECK-WIDE-NEXT:    vzeroupper
180; CHECK-WIDE-NEXT:    retl
181  %res = fptosi <8 x float> %src to <8 x i8>
182  ret <8 x i8> %res
183}
184
185define <8 x i16> @cvt_v8f32_v8i16(<8 x float> %src) {
186; CHECK-LABEL: cvt_v8f32_v8i16:
187; CHECK:       ## %bb.0:
188; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
189; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
190; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
191; CHECK-NEXT:    vzeroupper
192; CHECK-NEXT:    retl
193;
194; CHECK-WIDE-LABEL: cvt_v8f32_v8i16:
195; CHECK-WIDE:       ## %bb.0:
196; CHECK-WIDE-NEXT:    vcvttps2dq %ymm0, %ymm0
197; CHECK-WIDE-NEXT:    vextractf128 $1, %ymm0, %xmm1
198; CHECK-WIDE-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
199; CHECK-WIDE-NEXT:    vzeroupper
200; CHECK-WIDE-NEXT:    retl
201  %res = fptosi <8 x float> %src to <8 x i16>
202  ret <8 x i16> %res
203}
204
205define <4 x i8> @cvt_v4f32_v4i8(<4 x float> %src) {
206; CHECK-LABEL: cvt_v4f32_v4i8:
207; CHECK:       ## %bb.0:
208; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
209; CHECK-NEXT:    retl
210;
211; CHECK-WIDE-LABEL: cvt_v4f32_v4i8:
212; CHECK-WIDE:       ## %bb.0:
213; CHECK-WIDE-NEXT:    vcvttps2dq %xmm0, %xmm0
214; CHECK-WIDE-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
215; CHECK-WIDE-NEXT:    retl
216  %res = fptosi <4 x float> %src to <4 x i8>
217  ret <4 x i8> %res
218}
219
220define <4 x i16> @cvt_v4f32_v4i16(<4 x float> %src) {
221; CHECK-LABEL: cvt_v4f32_v4i16:
222; CHECK:       ## %bb.0:
223; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
224; CHECK-NEXT:    retl
225;
226; CHECK-WIDE-LABEL: cvt_v4f32_v4i16:
227; CHECK-WIDE:       ## %bb.0:
228; CHECK-WIDE-NEXT:    vcvttps2dq %xmm0, %xmm0
229; CHECK-WIDE-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
230; CHECK-WIDE-NEXT:    retl
231  %res = fptosi <4 x float> %src to <4 x i16>
232  ret <4 x i16> %res
233}
234
235define <8 x i8> @cvt_v8f32_v8u8(<8 x float> %src) {
236; CHECK-LABEL: cvt_v8f32_v8u8:
237; CHECK:       ## %bb.0:
238; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
239; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
240; CHECK-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
241; CHECK-NEXT:    vzeroupper
242; CHECK-NEXT:    retl
243;
244; CHECK-WIDE-LABEL: cvt_v8f32_v8u8:
245; CHECK-WIDE:       ## %bb.0:
246; CHECK-WIDE-NEXT:    vcvttps2dq %ymm0, %ymm0
247; CHECK-WIDE-NEXT:    vextractf128 $1, %ymm0, %xmm1
248; CHECK-WIDE-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
249; CHECK-WIDE-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
250; CHECK-WIDE-NEXT:    vzeroupper
251; CHECK-WIDE-NEXT:    retl
252  %res = fptoui <8 x float> %src to <8 x i8>
253  ret <8 x i8> %res
254}
255
256define <8 x i16> @cvt_v8f32_v8u16(<8 x float> %src) {
257; CHECK-LABEL: cvt_v8f32_v8u16:
258; CHECK:       ## %bb.0:
259; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
260; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
261; CHECK-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
262; CHECK-NEXT:    vzeroupper
263; CHECK-NEXT:    retl
264;
265; CHECK-WIDE-LABEL: cvt_v8f32_v8u16:
266; CHECK-WIDE:       ## %bb.0:
267; CHECK-WIDE-NEXT:    vcvttps2dq %ymm0, %ymm0
268; CHECK-WIDE-NEXT:    vextractf128 $1, %ymm0, %xmm1
269; CHECK-WIDE-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
270; CHECK-WIDE-NEXT:    vzeroupper
271; CHECK-WIDE-NEXT:    retl
272  %res = fptoui <8 x float> %src to <8 x i16>
273  ret <8 x i16> %res
274}
275
276define <4 x i8> @cvt_v4f32_v4u8(<4 x float> %src) {
277; CHECK-LABEL: cvt_v4f32_v4u8:
278; CHECK:       ## %bb.0:
279; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
280; CHECK-NEXT:    retl
281;
282; CHECK-WIDE-LABEL: cvt_v4f32_v4u8:
283; CHECK-WIDE:       ## %bb.0:
284; CHECK-WIDE-NEXT:    vcvttps2dq %xmm0, %xmm0
285; CHECK-WIDE-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
286; CHECK-WIDE-NEXT:    retl
287  %res = fptoui <4 x float> %src to <4 x i8>
288  ret <4 x i8> %res
289}
290
291define <4 x i16> @cvt_v4f32_v4u16(<4 x float> %src) {
292; CHECK-LABEL: cvt_v4f32_v4u16:
293; CHECK:       ## %bb.0:
294; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
295; CHECK-NEXT:    retl
296;
297; CHECK-WIDE-LABEL: cvt_v4f32_v4u16:
298; CHECK-WIDE:       ## %bb.0:
299; CHECK-WIDE-NEXT:    vcvttps2dq %xmm0, %xmm0
300; CHECK-WIDE-NEXT:    vpackusdw %xmm0, %xmm0, %xmm0
301; CHECK-WIDE-NEXT:    retl
302  %res = fptoui <4 x float> %src to <4 x i16>
303  ret <4 x i16> %res
304}
305
306