1; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 2; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown -O0 | FileCheck --check-prefix=CHECK-O0 %s 3 4@var = global i32 0 5 6; Test how llvm handles return type of {i16, i8}. The return value will be 7; passed in %eax and %dl. 8; CHECK-LABEL: test: 9; CHECK: movl %edi 10; CHECK: callq gen 11; CHECK: movsbl %dl 12; CHECK: addl %{{.*}}, %eax 13; CHECK-O0-LABEL: test 14; CHECK-O0: movl %edi 15; CHECK-O0: callq gen 16; CHECK-O0: movswl %ax 17; CHECK-O0: movsbl %dl 18; CHECK-O0: addl 19; CHECK-O0: movw %{{.*}}, %ax 20define i16 @test(i32 %key) { 21entry: 22 %key.addr = alloca i32, align 4 23 store i32 %key, i32* %key.addr, align 4 24 %0 = load i32, i32* %key.addr, align 4 25 %call = call swiftcc { i16, i8 } @gen(i32 %0) 26 %v3 = extractvalue { i16, i8 } %call, 0 27 %v1 = sext i16 %v3 to i32 28 %v5 = extractvalue { i16, i8 } %call, 1 29 %v2 = sext i8 %v5 to i32 30 %add = add nsw i32 %v1, %v2 31 %conv = trunc i32 %add to i16 32 ret i16 %conv 33} 34 35declare swiftcc { i16, i8 } @gen(i32) 36 37; If we can't pass every return value in register, we will pass everything 38; in memroy. The caller provides space for the return value and passes 39; the address in %rax. The first input argument will be in %rdi. 40; CHECK-LABEL: test2: 41; CHECK: movq %rsp, %rax 42; CHECK: callq gen2 43; CHECK: movl (%rsp) 44; CHECK-DAG: addl 4(%rsp) 45; CHECK-DAG: addl 8(%rsp) 46; CHECK-DAG: addl 12(%rsp) 47; CHECK-DAG: addl 16(%rsp) 48; CHECK-O0-LABEL: test2: 49; CHECK-O0-DAG: movq %rsp, %rax 50; CHECK-O0: callq gen2 51; CHECK-O0-DAG: movl (%rsp) 52; CHECK-O0-DAG: movl 4(%rsp) 53; CHECK-O0-DAG: movl 8(%rsp) 54; CHECK-O0-DAG: movl 12(%rsp) 55; CHECK-O0-DAG: movl 16(%rsp) 56; CHECK-O0: addl 57; CHECK-O0: addl 58; CHECK-O0: addl 59; CHECK-O0: addl 60; CHECK-O0: movl %{{.*}}, %eax 61define i32 @test2(i32 %key) #0 { 62entry: 63 %key.addr = alloca i32, align 4 64 store i32 %key, i32* %key.addr, align 4 65 %0 = load i32, i32* %key.addr, align 4 66 %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0) 67 68 %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0 69 %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1 70 %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2 71 %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3 72 %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4 73 74 %add = add nsw i32 %v3, %v5 75 %add1 = add nsw i32 %add, %v6 76 %add2 = add nsw i32 %add1, %v7 77 %add3 = add nsw i32 %add2, %v8 78 ret i32 %add3 79} 80 81; The address of the return value is passed in %rax. 82; On return, we don't keep the address in %rax. 83; CHECK-LABEL: gen2: 84; CHECK: movl %edi, 16(%rax) 85; CHECK: movl %edi, 12(%rax) 86; CHECK: movl %edi, 8(%rax) 87; CHECK: movl %edi, 4(%rax) 88; CHECK: movl %edi, (%rax) 89; CHECK-O0-LABEL: gen2: 90; CHECK-O0-DAG: movl %edi, 16(%rax) 91; CHECK-O0-DAG: movl %edi, 12(%rax) 92; CHECK-O0-DAG: movl %edi, 8(%rax) 93; CHECK-O0-DAG: movl %edi, 4(%rax) 94; CHECK-O0-DAG: movl %edi, (%rax) 95define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) { 96 %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0 97 %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1 98 %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2 99 %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3 100 %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4 101 ret { i32, i32, i32, i32, i32 } %Z4 102} 103 104; The return value {i32, i32, i32, i32} will be returned via registers %eax, 105; %edx, %ecx, %r8d. 106; CHECK-LABEL: test3: 107; CHECK: callq gen3 108; CHECK: addl %edx, %eax 109; CHECK: addl %ecx, %eax 110; CHECK: addl %r8d, %eax 111; CHECK-O0-LABEL: test3: 112; CHECK-O0: callq gen3 113; CHECK-O0: addl %edx, %eax 114; CHECK-O0: addl %ecx, %eax 115; CHECK-O0: addl %r8d, %eax 116define i32 @test3(i32 %key) #0 { 117entry: 118 %key.addr = alloca i32, align 4 119 store i32 %key, i32* %key.addr, align 4 120 %0 = load i32, i32* %key.addr, align 4 121 %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0) 122 123 %v3 = extractvalue { i32, i32, i32, i32 } %call, 0 124 %v5 = extractvalue { i32, i32, i32, i32 } %call, 1 125 %v6 = extractvalue { i32, i32, i32, i32 } %call, 2 126 %v7 = extractvalue { i32, i32, i32, i32 } %call, 3 127 128 %add = add nsw i32 %v3, %v5 129 %add1 = add nsw i32 %add, %v6 130 %add2 = add nsw i32 %add1, %v7 131 ret i32 %add2 132} 133 134declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key) 135 136; The return value {float, float, float, float} will be returned via registers 137; %xmm0, %xmm1, %xmm2, %xmm3. 138; CHECK-LABEL: test4: 139; CHECK: callq gen4 140; CHECK: addss %xmm1, %xmm0 141; CHECK: addss %xmm2, %xmm0 142; CHECK: addss %xmm3, %xmm0 143; CHECK-O0-LABEL: test4: 144; CHECK-O0: callq gen4 145; CHECK-O0: addss %xmm1, %xmm0 146; CHECK-O0: addss %xmm2, %xmm0 147; CHECK-O0: addss %xmm3, %xmm0 148define float @test4(float %key) #0 { 149entry: 150 %key.addr = alloca float, align 4 151 store float %key, float* %key.addr, align 4 152 %0 = load float, float* %key.addr, align 4 153 %call = call swiftcc { float, float, float, float } @gen4(float %0) 154 155 %v3 = extractvalue { float, float, float, float } %call, 0 156 %v5 = extractvalue { float, float, float, float } %call, 1 157 %v6 = extractvalue { float, float, float, float } %call, 2 158 %v7 = extractvalue { float, float, float, float } %call, 3 159 160 %add = fadd float %v3, %v5 161 %add1 = fadd float %add, %v6 162 %add2 = fadd float %add1, %v7 163 ret float %add2 164} 165 166declare swiftcc { float, float, float, float } @gen4(float %key) 167 168; CHECK-LABEL: consume_i1_ret: 169; CHECK: callq produce_i1_ret 170; CHECK: andb $1, %al 171; CHECK: andb $1, %dl 172; CHECK: andb $1, %cl 173; CHECK: andb $1, %r8b 174; CHECK-O0-LABEL: consume_i1_ret: 175; CHECK-O0: callq produce_i1_ret 176; CHECK-O0: andb $1, %al 177; CHECK-O0: andb $1, %dl 178; CHECK-O0: andb $1, %cl 179; CHECK-O0: andb $1, %r8b 180define void @consume_i1_ret() { 181 %call = call swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 182 %v3 = extractvalue { i1, i1, i1, i1 } %call, 0 183 %v5 = extractvalue { i1, i1, i1, i1 } %call, 1 184 %v6 = extractvalue { i1, i1, i1, i1 } %call, 2 185 %v7 = extractvalue { i1, i1, i1, i1 } %call, 3 186 %val = zext i1 %v3 to i32 187 store i32 %val, i32* @var 188 %val2 = zext i1 %v5 to i32 189 store i32 %val2, i32* @var 190 %val3 = zext i1 %v6 to i32 191 store i32 %val3, i32* @var 192 %val4 = zext i1 %v7 to i32 193 store i32 %val4, i32* @var 194 ret void 195} 196 197declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret() 198 199; CHECK-LABEL: foo: 200; CHECK: movq %rdi, (%rax) 201; CHECK-O0-LABEL: foo: 202; CHECK-O0: movq %rdi, (%rax) 203define swiftcc void @foo(i64* sret %agg.result, i64 %val) { 204 store i64 %val, i64* %agg.result 205 ret void 206} 207 208; CHECK-LABEL: test5 209; CHECK: callq gen5 210; CHECK: addsd %xmm1, %xmm0 211; CHECK: addsd %xmm2, %xmm0 212; CHECK: addsd %xmm3, %xmm0 213define swiftcc double @test5() #0 { 214entry: 215 %call = call swiftcc { double, double, double, double } @gen5() 216 217 %v3 = extractvalue { double, double, double, double } %call, 0 218 %v5 = extractvalue { double, double, double, double } %call, 1 219 %v6 = extractvalue { double, double, double, double } %call, 2 220 %v7 = extractvalue { double, double, double, double } %call, 3 221 222 %add = fadd double %v3, %v5 223 %add1 = fadd double %add, %v6 224 %add2 = fadd double %add1, %v7 225 ret double %add2 226} 227 228declare swiftcc { double, double, double, double } @gen5() 229 230 231; CHECK-LABEL: test6 232; CHECK: callq gen6 233; CHECK: addsd %xmm1, %xmm0 234; CHECK: addsd %xmm2, %xmm0 235; CHECK: addsd %xmm3, %xmm0 236; CHECK: addq %rdx, %rax 237; CHECK: addq %rcx, %rax 238; CHECK: addq %r8, %rax 239define swiftcc { double, i64 } @test6() #0 { 240entry: 241 %call = call swiftcc { double, double, double, double, i64, i64, i64, i64 } @gen6() 242 243 %v3 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 0 244 %v5 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 1 245 %v6 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 2 246 %v7 = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 3 247 %v3.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 4 248 %v5.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 5 249 %v6.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 6 250 %v7.i = extractvalue { double, double, double, double, i64, i64, i64, i64 } %call, 7 251 252 %add = fadd double %v3, %v5 253 %add1 = fadd double %add, %v6 254 %add2 = fadd double %add1, %v7 255 256 %add.i = add nsw i64 %v3.i, %v5.i 257 %add1.i = add nsw i64 %add.i, %v6.i 258 %add2.i = add nsw i64 %add1.i, %v7.i 259 260 %Y = insertvalue { double, i64 } undef, double %add2, 0 261 %Z = insertvalue { double, i64 } %Y, i64 %add2.i, 1 262 ret { double, i64} %Z 263} 264 265declare swiftcc { double, double, double, double, i64, i64, i64, i64 } @gen6() 266 267; CHECK-LABEL: gen7 268; CHECK: movl %edi, %eax 269; CHECK: movl %edi, %edx 270; CHECK: movl %edi, %ecx 271; CHECK: movl %edi, %r8d 272; CHECK: retq 273define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) { 274 %v0 = insertvalue { i32, i32, i32, i32 } undef, i32 %key, 0 275 %v1 = insertvalue { i32, i32, i32, i32 } %v0, i32 %key, 1 276 %v2 = insertvalue { i32, i32, i32, i32 } %v1, i32 %key, 2 277 %v3 = insertvalue { i32, i32, i32, i32 } %v2, i32 %key, 3 278 ret { i32, i32, i32, i32 } %v3 279} 280 281; CHECK-LABEL: gen8 282; CHECK: movq %rdi, %rax 283; CHECK: movq %rdi, %rdx 284; CHECK: movq %rdi, %rcx 285; CHECK: movq %rdi, %r8 286; CHECK: retq 287define swiftcc { i64, i64, i64, i64 } @gen8(i64 %key) { 288 %v0 = insertvalue { i64, i64, i64, i64 } undef, i64 %key, 0 289 %v1 = insertvalue { i64, i64, i64, i64 } %v0, i64 %key, 1 290 %v2 = insertvalue { i64, i64, i64, i64 } %v1, i64 %key, 2 291 %v3 = insertvalue { i64, i64, i64, i64 } %v2, i64 %key, 3 292 ret { i64, i64, i64, i64 } %v3 293} 294 295; CHECK-LABEL: gen9 296; CHECK: movl %edi, %eax 297; CHECK: movl %edi, %edx 298; CHECK: movl %edi, %ecx 299; CHECK: movl %edi, %r8d 300; CHECK: retq 301define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) { 302 %v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0 303 %v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1 304 %v2 = insertvalue { i8, i8, i8, i8 } %v1, i8 %key, 2 305 %v3 = insertvalue { i8, i8, i8, i8 } %v2, i8 %key, 3 306 ret { i8, i8, i8, i8 } %v3 307} 308; CHECK-LABEL: gen10 309; CHECK: movaps %xmm0, %xmm1 310; CHECK: movaps %xmm0, %xmm2 311; CHECK: movaps %xmm0, %xmm3 312; CHECK: movq %rdi, %rax 313; CHECK: movq %rdi, %rdx 314; CHECK: movq %rdi, %rcx 315; CHECK: movq %rdi, %r8 316; CHECK: retq 317define swiftcc { double, double, double, double, i64, i64, i64, i64 } @gen10(double %keyd, i64 %keyi) { 318 %v0 = insertvalue { double, double, double, double, i64, i64, i64, i64 } undef, double %keyd, 0 319 %v1 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v0, double %keyd, 1 320 %v2 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v1, double %keyd, 2 321 %v3 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v2, double %keyd, 3 322 %v4 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v3, i64 %keyi, 4 323 %v5 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v4, i64 %keyi, 5 324 %v6 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v5, i64 %keyi, 6 325 %v7 = insertvalue { double, double, double, double, i64, i64, i64, i64 } %v6, i64 %keyi, 7 326 ret { double, double, double, double, i64, i64, i64, i64 } %v7 327} 328 329 330; CHECK-LABEL: test11 331; CHECK: callq gen11 332; CHECK: addps %xmm1, %xmm0 333; CHECK: addps %xmm2, %xmm0 334; CHECK: addps %xmm3, %xmm0 335define swiftcc <4 x float> @test11() #0 { 336entry: 337 %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11() 338 339 %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 0 340 %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 1 341 %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 2 342 %v7 = extractvalue { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %call, 3 343 344 %add = fadd <4 x float> %v3, %v5 345 %add1 = fadd <4 x float> %add, %v6 346 %add2 = fadd <4 x float> %add1, %v7 347 ret <4 x float> %add2 348} 349 350declare swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11() 351 352; CHECK-LABEL: test12 353; CHECK: callq gen12 354; CHECK: addps %xmm1, %xmm0 355; CHECK: addps %xmm2, %xmm0 356; CHECK: movaps %xmm3, %xmm1 357define swiftcc { <4 x float>, float } @test12() #0 { 358entry: 359 %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12() 360 361 %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 0 362 %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 1 363 %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 2 364 %v8 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 3 365 366 %add = fadd <4 x float> %v3, %v5 367 %add1 = fadd <4 x float> %add, %v6 368 %res.0 = insertvalue { <4 x float>, float } undef, <4 x float> %add1, 0 369 %res = insertvalue { <4 x float>, float } %res.0, float %v8, 1 370 ret { <4 x float>, float } %res 371} 372 373declare swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12() 374