1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X32 --check-prefix=X32-SSE
3; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4a,+avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX
6
7define <2 x i64> @test_extrqi(<2 x i64> %x) nounwind uwtable ssp {
8; X32-LABEL: test_extrqi:
9; X32:       # BB#0:
10; X32-NEXT:    extrq $2, $3, %xmm0
11; X32-NEXT:    retl
12;
13; X64-LABEL: test_extrqi:
14; X64:       # BB#0:
15; X64-NEXT:    extrq $2, $3, %xmm0
16; X64-NEXT:    retq
17  %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
18  ret <2 x i64> %1
19}
20
21define <2 x i64> @test_extrqi_domain(<2 x i64> *%p) nounwind uwtable ssp {
22; X32-SSE-LABEL: test_extrqi_domain:
23; X32-SSE:       # BB#0:
24; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
25; X32-SSE-NEXT:    movdqa (%eax), %xmm0
26; X32-SSE-NEXT:    extrq $2, $3, %xmm0
27; X32-SSE-NEXT:    retl
28;
29; X32-AVX-LABEL: test_extrqi_domain:
30; X32-AVX:       # BB#0:
31; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
32; X32-AVX-NEXT:    vmovdqa (%eax), %xmm0
33; X32-AVX-NEXT:    extrq $2, $3, %xmm0
34; X32-AVX-NEXT:    retl
35;
36; X64-SSE-LABEL: test_extrqi_domain:
37; X64-SSE:       # BB#0:
38; X64-SSE-NEXT:    movdqa (%rdi), %xmm0
39; X64-SSE-NEXT:    extrq $2, $3, %xmm0
40; X64-SSE-NEXT:    retq
41;
42; X64-AVX-LABEL: test_extrqi_domain:
43; X64-AVX:       # BB#0:
44; X64-AVX-NEXT:    vmovdqa (%rdi), %xmm0
45; X64-AVX-NEXT:    extrq $2, $3, %xmm0
46; X64-AVX-NEXT:    retq
47  %1 = load <2 x i64>, <2 x i64> *%p
48  %2 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %1, i8 3, i8 2)
49  ret <2 x i64> %2
50}
51
52declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
53
54define <2 x i64> @test_extrq(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
55; X32-LABEL: test_extrq:
56; X32:       # BB#0:
57; X32-NEXT:    extrq %xmm1, %xmm0
58; X32-NEXT:    retl
59;
60; X64-LABEL: test_extrq:
61; X64:       # BB#0:
62; X64-NEXT:    extrq %xmm1, %xmm0
63; X64-NEXT:    retq
64  %1 = bitcast <2 x i64> %y to <16 x i8>
65  %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
66  ret <2 x i64> %2
67}
68
69define <2 x i64> @test_extrq_domain(<2 x i64> *%p, <2 x i64> %y) nounwind uwtable ssp {
70; X32-SSE-LABEL: test_extrq_domain:
71; X32-SSE:       # BB#0:
72; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
73; X32-SSE-NEXT:    movdqa (%eax), %xmm1
74; X32-SSE-NEXT:    extrq %xmm0, %xmm1
75; X32-SSE-NEXT:    movdqa %xmm1, %xmm0
76; X32-SSE-NEXT:    retl
77;
78; X32-AVX-LABEL: test_extrq_domain:
79; X32-AVX:       # BB#0:
80; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
81; X32-AVX-NEXT:    vmovdqa (%eax), %xmm1
82; X32-AVX-NEXT:    extrq %xmm0, %xmm1
83; X32-AVX-NEXT:    vmovdqa %xmm1, %xmm0
84; X32-AVX-NEXT:    retl
85;
86; X64-SSE-LABEL: test_extrq_domain:
87; X64-SSE:       # BB#0:
88; X64-SSE-NEXT:    movdqa (%rdi), %xmm1
89; X64-SSE-NEXT:    extrq %xmm0, %xmm1
90; X64-SSE-NEXT:    movdqa %xmm1, %xmm0
91; X64-SSE-NEXT:    retq
92;
93; X64-AVX-LABEL: test_extrq_domain:
94; X64-AVX:       # BB#0:
95; X64-AVX-NEXT:    vmovdqa (%rdi), %xmm1
96; X64-AVX-NEXT:    extrq %xmm0, %xmm1
97; X64-AVX-NEXT:    vmovdqa %xmm1, %xmm0
98; X64-AVX-NEXT:    retq
99  %1 = load <2 x i64>, <2 x i64> *%p
100  %2 = bitcast <2 x i64> %y to <16 x i8>
101  %3 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %2) nounwind
102  ret <2 x i64> %3
103}
104
105declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
106
107define <2 x i64> @test_insertqi(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
108; X32-LABEL: test_insertqi:
109; X32:       # BB#0:
110; X32-NEXT:    insertq $6, $5, %xmm1, %xmm0
111; X32-NEXT:    retl
112;
113; X64-LABEL: test_insertqi:
114; X64:       # BB#0:
115; X64-NEXT:    insertq $6, $5, %xmm1, %xmm0
116; X64-NEXT:    retq
117  %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
118  ret <2 x i64> %1
119}
120
121define <2 x i64> @test_insertqi_domain(<2 x i64> *%p, <2 x i64> %y) nounwind uwtable ssp {
122; X32-SSE-LABEL: test_insertqi_domain:
123; X32-SSE:       # BB#0:
124; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
125; X32-SSE-NEXT:    movdqa (%eax), %xmm1
126; X32-SSE-NEXT:    insertq $6, $5, %xmm0, %xmm1
127; X32-SSE-NEXT:    movdqa %xmm1, %xmm0
128; X32-SSE-NEXT:    retl
129;
130; X32-AVX-LABEL: test_insertqi_domain:
131; X32-AVX:       # BB#0:
132; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
133; X32-AVX-NEXT:    vmovdqa (%eax), %xmm1
134; X32-AVX-NEXT:    insertq $6, $5, %xmm0, %xmm1
135; X32-AVX-NEXT:    vmovdqa %xmm1, %xmm0
136; X32-AVX-NEXT:    retl
137;
138; X64-SSE-LABEL: test_insertqi_domain:
139; X64-SSE:       # BB#0:
140; X64-SSE-NEXT:    movdqa (%rdi), %xmm1
141; X64-SSE-NEXT:    insertq $6, $5, %xmm0, %xmm1
142; X64-SSE-NEXT:    movdqa %xmm1, %xmm0
143; X64-SSE-NEXT:    retq
144;
145; X64-AVX-LABEL: test_insertqi_domain:
146; X64-AVX:       # BB#0:
147; X64-AVX-NEXT:    vmovdqa (%rdi), %xmm1
148; X64-AVX-NEXT:    insertq $6, $5, %xmm0, %xmm1
149; X64-AVX-NEXT:    vmovdqa %xmm1, %xmm0
150; X64-AVX-NEXT:    retq
151  %1 = load <2 x i64>, <2 x i64> *%p
152  %2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %y, i8 5, i8 6)
153  ret <2 x i64> %2
154}
155
156declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
157
158define <2 x i64> @test_insertq(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
159; X32-LABEL: test_insertq:
160; X32:       # BB#0:
161; X32-NEXT:    insertq %xmm1, %xmm0
162; X32-NEXT:    retl
163;
164; X64-LABEL: test_insertq:
165; X64:       # BB#0:
166; X64-NEXT:    insertq %xmm1, %xmm0
167; X64-NEXT:    retq
168  %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
169  ret <2 x i64> %1
170}
171
172define <2 x i64> @test_insertq_domain(<2 x i64> *%p, <2 x i64> %y) nounwind uwtable ssp {
173; X32-SSE-LABEL: test_insertq_domain:
174; X32-SSE:       # BB#0:
175; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
176; X32-SSE-NEXT:    movdqa (%eax), %xmm1
177; X32-SSE-NEXT:    insertq %xmm0, %xmm1
178; X32-SSE-NEXT:    movdqa %xmm1, %xmm0
179; X32-SSE-NEXT:    retl
180;
181; X32-AVX-LABEL: test_insertq_domain:
182; X32-AVX:       # BB#0:
183; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
184; X32-AVX-NEXT:    vmovdqa (%eax), %xmm1
185; X32-AVX-NEXT:    insertq %xmm0, %xmm1
186; X32-AVX-NEXT:    vmovdqa %xmm1, %xmm0
187; X32-AVX-NEXT:    retl
188;
189; X64-SSE-LABEL: test_insertq_domain:
190; X64-SSE:       # BB#0:
191; X64-SSE-NEXT:    movdqa (%rdi), %xmm1
192; X64-SSE-NEXT:    insertq %xmm0, %xmm1
193; X64-SSE-NEXT:    movdqa %xmm1, %xmm0
194; X64-SSE-NEXT:    retq
195;
196; X64-AVX-LABEL: test_insertq_domain:
197; X64-AVX:       # BB#0:
198; X64-AVX-NEXT:    vmovdqa (%rdi), %xmm1
199; X64-AVX-NEXT:    insertq %xmm0, %xmm1
200; X64-AVX-NEXT:    vmovdqa %xmm1, %xmm0
201; X64-AVX-NEXT:    retq
202  %1 = load <2 x i64>, <2 x i64> *%p
203  %2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind
204  ret <2 x i64> %2
205}
206
207declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind
208