1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
3; rdar://7329206
4
5define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
6; CHECK-LABEL: t1:
7; CHECK:       ## %bb.0:
8; CHECK-NEXT:    xorl %eax, %eax
9; CHECK-NEXT:    cmpw $27, %di
10; CHECK-NEXT:    setae %al
11; CHECK-NEXT:    shll $5, %eax
12; CHECK-NEXT:    retq
13  %t0 = icmp ugt i16 %x, 26
14  %if = select i1 %t0, i16 32, i16 0
15  ret i16 %if
16}
17
18define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
19; CHECK-LABEL: t2:
20; CHECK:       ## %bb.0:
21; CHECK-NEXT:    xorl %eax, %eax
22; CHECK-NEXT:    cmpw $26, %di
23; CHECK-NEXT:    setb %al
24; CHECK-NEXT:    shll $5, %eax
25; CHECK-NEXT:    retq
26  %t0 = icmp ult i16 %x, 26
27  %if = select i1 %t0, i16 32, i16 0
28  ret i16 %if
29}
30
31define i64 @t3(i64 %x) nounwind readnone ssp {
32; CHECK-LABEL: t3:
33; CHECK:       ## %bb.0:
34; CHECK-NEXT:    xorl %eax, %eax
35; CHECK-NEXT:    cmpq $18, %rdi
36; CHECK-NEXT:    setb %al
37; CHECK-NEXT:    shlq $6, %rax
38; CHECK-NEXT:    retq
39  %t0 = icmp ult i64 %x, 18
40  %if = select i1 %t0, i64 64, i64 0
41  ret i64 %if
42}
43
44@v4 = common global i32 0, align 4
45
46define i32 @t4(i32 %a) {
47; CHECK-LABEL: t4:
48; CHECK:       ## %bb.0:
49; CHECK-NEXT:    movq _v4@GOTPCREL(%rip), %rax
50; CHECK-NEXT:    cmpl $1, (%rax)
51; CHECK-NEXT:    movw $1, %ax
52; CHECK-NEXT:    adcw $0, %ax
53; CHECK-NEXT:    shll $16, %eax
54; CHECK-NEXT:    retq
55  %t0 = load i32, i32* @v4, align 4
56  %not.tobool = icmp eq i32 %t0, 0
57  %conv.i = sext i1 %not.tobool to i16
58  %call.lobit = lshr i16 %conv.i, 15
59  %add.i.1 = add nuw nsw i16 %call.lobit, 1
60  %conv4.2 = zext i16 %add.i.1 to i32
61  %add = shl nuw nsw i32 %conv4.2, 16
62  ret i32 %add
63}
64
65define i8 @t5(i32 %a) #0 {
66; CHECK-LABEL: t5:
67; CHECK:       ## %bb.0:
68; CHECK-NEXT:    testl %edi, %edi
69; CHECK-NEXT:    setns %al
70; CHECK-NEXT:    retq
71  %.lobit = lshr i32 %a, 31
72  %trunc = trunc i32 %.lobit to i8
73  %.not = xor i8 %trunc, 1
74  ret i8 %.not
75}
76
77define zeroext i1 @t6(i32 %a) #0 {
78; CHECK-LABEL: t6:
79; CHECK:       ## %bb.0:
80; CHECK-NEXT:    testl %edi, %edi
81; CHECK-NEXT:    setns %al
82; CHECK-NEXT:    retq
83  %.lobit = lshr i32 %a, 31
84  %trunc = trunc i32 %.lobit to i1
85  %.not = xor i1 %trunc, 1
86  ret i1 %.not
87}
88
89define i16 @shift_and(i16 %a) {
90; CHECK-LABEL: shift_and:
91; CHECK:       ## %bb.0:
92; CHECK-NEXT:    movl %edi, %eax
93; CHECK-NEXT:    shrl $10, %eax
94; CHECK-NEXT:    andl $1, %eax
95; CHECK-NEXT:    ## kill: def $ax killed $ax killed $eax
96; CHECK-NEXT:    retq
97  %and = and i16 %a, 1024
98  %cmp = icmp ne i16 %and, 0
99  %conv = zext i1 %cmp to i16
100  ret i16 %conv
101}
102
103attributes #0 = { "target-cpu"="skylake-avx512" }
104