1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s --check-prefixes=X86
3; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s --check-prefixes=X64
4; rdar://7329206
5
6define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
7; X86-LABEL: t1:
8; X86:       ## %bb.0:
9; X86-NEXT:    xorl %eax, %eax
10; X86-NEXT:    cmpw $27, {{[0-9]+}}(%esp)
11; X86-NEXT:    setae %al
12; X86-NEXT:    shll $5, %eax
13; X86-NEXT:    retl
14;
15; X64-LABEL: t1:
16; X64:       ## %bb.0:
17; X64-NEXT:    xorl %eax, %eax
18; X64-NEXT:    cmpw $27, %di
19; X64-NEXT:    setae %al
20; X64-NEXT:    shll $5, %eax
21; X64-NEXT:    retq
22  %t0 = icmp ugt i16 %x, 26
23  %if = select i1 %t0, i16 32, i16 0
24  ret i16 %if
25}
26
27define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
28; X86-LABEL: t2:
29; X86:       ## %bb.0:
30; X86-NEXT:    xorl %eax, %eax
31; X86-NEXT:    cmpw $26, {{[0-9]+}}(%esp)
32; X86-NEXT:    setb %al
33; X86-NEXT:    shll $5, %eax
34; X86-NEXT:    retl
35;
36; X64-LABEL: t2:
37; X64:       ## %bb.0:
38; X64-NEXT:    xorl %eax, %eax
39; X64-NEXT:    cmpw $26, %di
40; X64-NEXT:    setb %al
41; X64-NEXT:    shll $5, %eax
42; X64-NEXT:    retq
43  %t0 = icmp ult i16 %x, 26
44  %if = select i1 %t0, i16 32, i16 0
45  ret i16 %if
46}
47
48define i64 @t3(i64 %x) nounwind readnone ssp {
49; X86-LABEL: t3:
50; X86:       ## %bb.0:
51; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
52; X86-NEXT:    cmpl $18, {{[0-9]+}}(%esp)
53; X86-NEXT:    sbbl $0, %eax
54; X86-NEXT:    setb %al
55; X86-NEXT:    movzbl %al, %eax
56; X86-NEXT:    shll $6, %eax
57; X86-NEXT:    xorl %edx, %edx
58; X86-NEXT:    retl
59;
60; X64-LABEL: t3:
61; X64:       ## %bb.0:
62; X64-NEXT:    xorl %eax, %eax
63; X64-NEXT:    cmpq $18, %rdi
64; X64-NEXT:    setb %al
65; X64-NEXT:    shlq $6, %rax
66; X64-NEXT:    retq
67  %t0 = icmp ult i64 %x, 18
68  %if = select i1 %t0, i64 64, i64 0
69  ret i64 %if
70}
71
72@v4 = common global i32 0, align 4
73
74define i32 @t4(i32 %a) {
75; X86-LABEL: t4:
76; X86:       ## %bb.0:
77; X86-NEXT:    movl L_v4$non_lazy_ptr, %ecx
78; X86-NEXT:    xorl %eax, %eax
79; X86-NEXT:    cmpl $1, (%ecx)
80; X86-NEXT:    adcw $1, %ax
81; X86-NEXT:    shll $16, %eax
82; X86-NEXT:    retl
83;
84; X64-LABEL: t4:
85; X64:       ## %bb.0:
86; X64-NEXT:    movq _v4@GOTPCREL(%rip), %rcx
87; X64-NEXT:    xorl %eax, %eax
88; X64-NEXT:    cmpl $1, (%rcx)
89; X64-NEXT:    adcw $1, %ax
90; X64-NEXT:    shll $16, %eax
91; X64-NEXT:    retq
92  %t0 = load i32, i32* @v4, align 4
93  %not.tobool = icmp eq i32 %t0, 0
94  %conv.i = sext i1 %not.tobool to i16
95  %call.lobit = lshr i16 %conv.i, 15
96  %add.i.1 = add nuw nsw i16 %call.lobit, 1
97  %conv4.2 = zext i16 %add.i.1 to i32
98  %add = shl nuw nsw i32 %conv4.2, 16
99  ret i32 %add
100}
101
102define i8 @t5(i32 %a) #0 {
103; X86-LABEL: t5:
104; X86:       ## %bb.0:
105; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
106; X86-NEXT:    setns %al
107; X86-NEXT:    retl
108;
109; X64-LABEL: t5:
110; X64:       ## %bb.0:
111; X64-NEXT:    testl %edi, %edi
112; X64-NEXT:    setns %al
113; X64-NEXT:    retq
114  %.lobit = lshr i32 %a, 31
115  %trunc = trunc i32 %.lobit to i8
116  %.not = xor i8 %trunc, 1
117  ret i8 %.not
118}
119
120define zeroext i1 @t6(i32 %a) #0 {
121; X86-LABEL: t6:
122; X86:       ## %bb.0:
123; X86-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
124; X86-NEXT:    setns %al
125; X86-NEXT:    retl
126;
127; X64-LABEL: t6:
128; X64:       ## %bb.0:
129; X64-NEXT:    testl %edi, %edi
130; X64-NEXT:    setns %al
131; X64-NEXT:    retq
132  %.lobit = lshr i32 %a, 31
133  %trunc = trunc i32 %.lobit to i1
134  %.not = xor i1 %trunc, 1
135  ret i1 %.not
136}
137
138; PR39174
139define zeroext i1 @t7(i32 %0) {
140; X86-LABEL: t7:
141; X86:       ## %bb.0:
142; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
143; X86-NEXT:    movl $19, %ecx
144; X86-NEXT:    btl %eax, %ecx
145; X86-NEXT:    setb %al
146; X86-NEXT:    retl
147;
148; X64-LABEL: t7:
149; X64:       ## %bb.0:
150; X64-NEXT:    movl $19, %eax
151; X64-NEXT:    btl %edi, %eax
152; X64-NEXT:    setb %al
153; X64-NEXT:    retq
154  %2 = trunc i32 %0 to i5
155  %3 = lshr i5 -13, %2
156  %4 = and i5 %3, 1
157  %5 = icmp ne i5 %4, 0
158  ret i1 %5
159}
160
161define zeroext i1 @t8(i8 %0, i8 %1) {
162; X86-LABEL: t8:
163; X86:       ## %bb.0:
164; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
165; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
166; X86-NEXT:    btl %eax, %ecx
167; X86-NEXT:    setb %al
168; X86-NEXT:    retl
169;
170; X64-LABEL: t8:
171; X64:       ## %bb.0:
172; X64-NEXT:    btl %esi, %edi
173; X64-NEXT:    setb %al
174; X64-NEXT:    retq
175  %3 = lshr i8 %0, %1
176  %4 = and i8 %3, 1
177  %5 = icmp ne i8 %4, 0
178  ret i1 %5
179}
180
181define i64 @t9(i32 %0, i32 %1) {
182; X86-LABEL: t9:
183; X86:       ## %bb.0:
184; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
185; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
186; X86-NEXT:    xorl %eax, %eax
187; X86-NEXT:    btl %edx, %ecx
188; X86-NEXT:    setb %al
189; X86-NEXT:    xorl %edx, %edx
190; X86-NEXT:    retl
191;
192; X64-LABEL: t9:
193; X64:       ## %bb.0:
194; X64-NEXT:    xorl %eax, %eax
195; X64-NEXT:    btl %esi, %edi
196; X64-NEXT:    setb %al
197; X64-NEXT:    retq
198  %3 = lshr i32 %0, %1
199  %4 = and i32 %3, 1
200  %5 = icmp ne i32 %4, 0
201  %6 = zext i1 %5 to i64
202  ret i64 %6
203}
204
205define i32 @t10(i32 %0, i32 %1) {
206; X86-LABEL: t10:
207; X86:       ## %bb.0:
208; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
209; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
210; X86-NEXT:    xorl %eax, %eax
211; X86-NEXT:    btl %edx, %ecx
212; X86-NEXT:    setae %al
213; X86-NEXT:    retl
214;
215; X64-LABEL: t10:
216; X64:       ## %bb.0:
217; X64-NEXT:    xorl %eax, %eax
218; X64-NEXT:    btl %esi, %edi
219; X64-NEXT:    setae %al
220; X64-NEXT:    retq
221  %3 = lshr i32 %0, %1
222  %4 = and i32 %3, 1
223  %5 = xor i32 %4, 1
224  ret i32 %5
225}
226
227define i32 @t11(i32 %0, i32 %1) {
228; X86-LABEL: t11:
229; X86:       ## %bb.0:
230; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
231; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
232; X86-NEXT:    xorl %eax, %eax
233; X86-NEXT:    btl %edx, %ecx
234; X86-NEXT:    setae %al
235; X86-NEXT:    retl
236;
237; X64-LABEL: t11:
238; X64:       ## %bb.0:
239; X64-NEXT:    xorl %eax, %eax
240; X64-NEXT:    btl %esi, %edi
241; X64-NEXT:    setae %al
242; X64-NEXT:    retq
243  %3 = xor i32 %0, -1
244  %4 = lshr i32 %3, %1
245  %5 = and i32 %4, 1
246  ret i32 %5
247}
248
249define i32 @t12(i32 %0, i32 %1) {
250; X86-LABEL: t12:
251; X86:       ## %bb.0:
252; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
253; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
254; X86-NEXT:    xorl %eax, %eax
255; X86-NEXT:    btl %edx, %ecx
256; X86-NEXT:    setb %al
257; X86-NEXT:    retl
258;
259; X64-LABEL: t12:
260; X64:       ## %bb.0:
261; X64-NEXT:    xorl %eax, %eax
262; X64-NEXT:    btl %esi, %edi
263; X64-NEXT:    setb %al
264; X64-NEXT:    retq
265  %3 = xor i32 %0, -1
266  %4 = lshr i32 %3, %1
267  %5 = and i32 %4, 1
268  %6 = xor i32 %5, 1
269  ret i32 %6
270}
271
272define i16 @shift_and(i16 %a) {
273; X86-LABEL: shift_and:
274; X86:       ## %bb.0:
275; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
276; X86-NEXT:    andb $4, %al
277; X86-NEXT:    shrb $2, %al
278; X86-NEXT:    movzbl %al, %eax
279; X86-NEXT:    ## kill: def $ax killed $ax killed $eax
280; X86-NEXT:    retl
281;
282; X64-LABEL: shift_and:
283; X64:       ## %bb.0:
284; X64-NEXT:    movl %edi, %eax
285; X64-NEXT:    shrl $10, %eax
286; X64-NEXT:    andl $1, %eax
287; X64-NEXT:    ## kill: def $ax killed $ax killed $eax
288; X64-NEXT:    retq
289  %and = and i16 %a, 1024
290  %cmp = icmp ne i16 %and, 0
291  %conv = zext i1 %cmp to i16
292  ret i16 %conv
293}
294
295attributes #0 = { "target-cpu"="skylake-avx512" }
296