1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
3; rdar://7329206
4
5; Use sbb x, x to materialize carry bit in a GPR. The value is either
6; all 1's or all 0's.
7
8define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
9; CHECK-LABEL: t1:
10; CHECK:       ## BB#0:
11; CHECK-NEXT:    xorl %eax, %eax
12; CHECK-NEXT:    cmpl $26, %edi
13; CHECK-NEXT:    seta %al
14; CHECK-NEXT:    shll $5, %eax
15; CHECK-NEXT:    retq
16;
17  %t0 = icmp ugt i16 %x, 26
18  %if = select i1 %t0, i16 32, i16 0
19  ret i16 %if
20}
21
22define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
23; CHECK-LABEL: t2:
24; CHECK:       ## BB#0:
25; CHECK-NEXT:    cmpl $26, %edi
26; CHECK-NEXT:    sbbl %eax, %eax
27; CHECK-NEXT:    andl $32, %eax
28; CHECK-NEXT:    retq
29;
30  %t0 = icmp ult i16 %x, 26
31  %if = select i1 %t0, i16 32, i16 0
32  ret i16 %if
33}
34
35define i64 @t3(i64 %x) nounwind readnone ssp {
36; CHECK-LABEL: t3:
37; CHECK:       ## BB#0:
38; CHECK-NEXT:    cmpq $18, %rdi
39; CHECK-NEXT:    sbbq %rax, %rax
40; CHECK-NEXT:    andl $64, %eax
41; CHECK-NEXT:    retq
42;
43  %t0 = icmp ult i64 %x, 18
44  %if = select i1 %t0, i64 64, i64 0
45  ret i64 %if
46}
47
48@v4 = common global i32 0, align 4
49
50define i32 @t4(i32 %a) {
51; CHECK-LABEL: t4:
52; CHECK:       ## BB#0:
53; CHECK-NEXT:    movq _v4@{{.*}}(%rip), %rax
54; CHECK-NEXT:    cmpl $1, (%rax)
55; CHECK-NEXT:    sbbl %eax, %eax
56; CHECK-NEXT:    andl $32768, %eax ## imm = 0x8000
57; CHECK-NEXT:    leal 65536(%rax,%rax), %eax
58; CHECK-NEXT:    retq
59;
60  %t0 = load i32, i32* @v4, align 4
61  %not.tobool = icmp eq i32 %t0, 0
62  %conv.i = sext i1 %not.tobool to i16
63  %call.lobit = lshr i16 %conv.i, 15
64  %add.i.1 = add nuw nsw i16 %call.lobit, 1
65  %conv4.2 = zext i16 %add.i.1 to i32
66  %add = shl nuw nsw i32 %conv4.2, 16
67  ret i32 %add
68}
69
70define i8 @t5(i32 %a) #0 {
71; CHECK-LABEL: t5:
72; CHECK:       ## BB#0:
73; CHECK-NEXT:    testl %edi, %edi
74; CHECK-NEXT:    setns %al
75; CHECK-NEXT:    retq
76;
77  %.lobit = lshr i32 %a, 31
78  %trunc = trunc i32 %.lobit to i8
79  %.not = xor i8 %trunc, 1
80  ret i8 %.not
81}
82
83define zeroext i1 @t6(i32 %a) #0 {
84; CHECK-LABEL: t6:
85; CHECK:       ## BB#0:
86; CHECK-NEXT:    testl %edi, %edi
87; CHECK-NEXT:    setns %al
88; CHECK-NEXT:    retq
89;
90  %.lobit = lshr i32 %a, 31
91  %trunc = trunc i32 %.lobit to i1
92  %.not = xor i1 %trunc, 1
93  ret i1 %.not
94}
95
96attributes #0 = { "target-cpu"="skylake-avx512" }
97