1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 3; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42 4; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 5; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-SLOW 6; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST 7; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512,AVX512-SLOW 8; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx512f,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512-FAST 9; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+xop | FileCheck %s --check-prefixes=AVX,XOP 10 11define void @insert_v7i8_v2i16_2(<7 x i8> *%a0, <2 x i16> *%a1) nounwind { 12; SSE2-LABEL: insert_v7i8_v2i16_2: 13; SSE2: # %bb.0: 14; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 15; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero 16; SSE2-NEXT: pextrw $3, %xmm1, %eax 17; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 18; SSE2-NEXT: movd %xmm1, (%rdi) 19; SSE2-NEXT: movb %al, 6(%rdi) 20; SSE2-NEXT: pextrw $1, %xmm0, %eax 21; SSE2-NEXT: movw %ax, 4(%rdi) 22; SSE2-NEXT: retq 23; 24; SSE42-LABEL: insert_v7i8_v2i16_2: 25; SSE42: # %bb.0: 26; SSE42-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 27; SSE42-NEXT: movq {{.*#+}} xmm1 = mem[0],zero 28; SSE42-NEXT: pextrb $6, %xmm1, 6(%rdi) 29; SSE42-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 30; SSE42-NEXT: pextrw $1, %xmm0, 4(%rdi) 31; SSE42-NEXT: movd %xmm1, (%rdi) 32; SSE42-NEXT: retq 33; 34; AVX1-LABEL: insert_v7i8_v2i16_2: 35; AVX1: # %bb.0: 36; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero 37; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero 38; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 39; AVX1-NEXT: vpextrb $6, %xmm1, 6(%rdi) 40; AVX1-NEXT: vpextrw $1, %xmm0, 4(%rdi) 41; AVX1-NEXT: vmovd %xmm2, (%rdi) 42; AVX1-NEXT: retq 43; 44; AVX2-LABEL: insert_v7i8_v2i16_2: 45; AVX2: # %bb.0: 46; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero 47; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero 48; AVX2-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 49; AVX2-NEXT: vpextrb $6, %xmm1, 6(%rdi) 50; AVX2-NEXT: vpextrw $1, %xmm0, 4(%rdi) 51; AVX2-NEXT: vmovd %xmm2, (%rdi) 52; AVX2-NEXT: retq 53; 54; AVX512-LABEL: insert_v7i8_v2i16_2: 55; AVX512: # %bb.0: 56; AVX512-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero 57; AVX512-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero 58; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 59; AVX512-NEXT: vpextrb $6, %xmm1, 6(%rdi) 60; AVX512-NEXT: vpextrw $1, %xmm0, 4(%rdi) 61; AVX512-NEXT: vmovd %xmm2, (%rdi) 62; AVX512-NEXT: retq 63; 64; XOP-LABEL: insert_v7i8_v2i16_2: 65; XOP: # %bb.0: 66; XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero 67; XOP-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero 68; XOP-NEXT: vpextrb $6, %xmm1, 6(%rdi) 69; XOP-NEXT: insertq {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,1,2,3],xmm1[6,7,u,u,u,u,u,u,u,u] 70; XOP-NEXT: vpextrw $1, %xmm0, 4(%rdi) 71; XOP-NEXT: vmovd %xmm1, (%rdi) 72; XOP-NEXT: retq 73 %1 = load <2 x i16>, <2 x i16> *%a1 74 %2 = bitcast <2 x i16> %1 to <4 x i8> 75 %3 = shufflevector <4 x i8> %2, <4 x i8> undef, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef> 76 %4 = load <7 x i8>, <7 x i8> *%a0 77 %5 = shufflevector <7 x i8> %4, <7 x i8> %3, <7 x i32> <i32 0, i32 1, i32 7, i32 8, i32 9, i32 10, i32 6> 78 store <7 x i8> %5, <7 x i8>* %a0 79 ret void 80} 81 82%struct.Mat4 = type { %struct.storage } 83%struct.storage = type { [16 x float] } 84 85define void @PR40815(%struct.Mat4* nocapture readonly dereferenceable(64), %struct.Mat4* nocapture dereferenceable(64)) { 86; SSE-LABEL: PR40815: 87; SSE: # %bb.0: 88; SSE-NEXT: movaps (%rdi), %xmm0 89; SSE-NEXT: movaps 16(%rdi), %xmm1 90; SSE-NEXT: movaps 32(%rdi), %xmm2 91; SSE-NEXT: movaps 48(%rdi), %xmm3 92; SSE-NEXT: movaps %xmm3, (%rsi) 93; SSE-NEXT: movaps %xmm2, 16(%rsi) 94; SSE-NEXT: movaps %xmm1, 32(%rsi) 95; SSE-NEXT: movaps %xmm0, 48(%rsi) 96; SSE-NEXT: retq 97; 98; AVX-LABEL: PR40815: 99; AVX: # %bb.0: 100; AVX-NEXT: vmovaps (%rdi), %xmm0 101; AVX-NEXT: vmovaps 16(%rdi), %xmm1 102; AVX-NEXT: vmovaps 32(%rdi), %xmm2 103; AVX-NEXT: vmovaps 48(%rdi), %xmm3 104; AVX-NEXT: vmovaps %xmm2, 16(%rsi) 105; AVX-NEXT: vmovaps %xmm3, (%rsi) 106; AVX-NEXT: vmovaps %xmm0, 48(%rsi) 107; AVX-NEXT: vmovaps %xmm1, 32(%rsi) 108; AVX-NEXT: retq 109; 110; AVX512-LABEL: PR40815: 111; AVX512: # %bb.0: 112; AVX512-NEXT: vmovaps 16(%rdi), %xmm0 113; AVX512-NEXT: vmovaps 48(%rdi), %xmm1 114; AVX512-NEXT: vinsertf128 $1, (%rdi), %ymm0, %ymm0 115; AVX512-NEXT: vinsertf128 $1, 32(%rdi), %ymm1, %ymm1 116; AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 117; AVX512-NEXT: vmovups %zmm0, (%rsi) 118; AVX512-NEXT: vzeroupper 119; AVX512-NEXT: retq 120 %3 = bitcast %struct.Mat4* %0 to <16 x float>* 121 %4 = load <16 x float>, <16 x float>* %3, align 64 122 %5 = shufflevector <16 x float> %4, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 123 %6 = getelementptr inbounds %struct.Mat4, %struct.Mat4* %1, i64 0, i32 0, i32 0, i64 4 124 %7 = bitcast <16 x float> %4 to <4 x i128> 125 %8 = extractelement <4 x i128> %7, i32 1 126 %9 = getelementptr inbounds %struct.Mat4, %struct.Mat4* %1, i64 0, i32 0, i32 0, i64 8 127 %10 = bitcast <16 x float> %4 to <4 x i128> 128 %11 = extractelement <4 x i128> %10, i32 2 129 %12 = getelementptr inbounds %struct.Mat4, %struct.Mat4* %1, i64 0, i32 0, i32 0, i64 12 130 %13 = bitcast float* %12 to <4 x float>* 131 %14 = bitcast <16 x float> %4 to <4 x i128> 132 %15 = extractelement <4 x i128> %14, i32 3 133 %16 = bitcast %struct.Mat4* %1 to i128* 134 store i128 %15, i128* %16, align 16 135 %17 = bitcast float* %6 to i128* 136 store i128 %11, i128* %17, align 16 137 %18 = bitcast float* %9 to i128* 138 store i128 %8, i128* %18, align 16 139 store <4 x float> %5, <4 x float>* %13, align 16 140 ret void 141} 142 143define <16 x i32> @PR42819(<8 x i32>* %a0) { 144; SSE-LABEL: PR42819: 145; SSE: # %bb.0: 146; SSE-NEXT: movdqu (%rdi), %xmm3 147; SSE-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7,8,9,10,11] 148; SSE-NEXT: xorps %xmm0, %xmm0 149; SSE-NEXT: xorps %xmm1, %xmm1 150; SSE-NEXT: xorps %xmm2, %xmm2 151; SSE-NEXT: retq 152; 153; AVX-LABEL: PR42819: 154; AVX: # %bb.0: 155; AVX-NEXT: vpermilps {{.*#+}} xmm0 = mem[0,0,1,2] 156; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 157; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 158; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm0[5,6,7] 159; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 160; AVX-NEXT: retq 161; 162; AVX512-LABEL: PR42819: 163; AVX512: # %bb.0: 164; AVX512-NEXT: vmovdqu (%rdi), %xmm0 165; AVX512-NEXT: movw $-8192, %ax # imm = 0xE000 166; AVX512-NEXT: kmovw %eax, %k1 167; AVX512-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z} 168; AVX512-NEXT: retq 169 %1 = load <8 x i32>, <8 x i32>* %a0, align 4 170 %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 171 %3 = shufflevector <16 x i32> zeroinitializer, <16 x i32> %2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> 172 ret <16 x i32> %3 173} 174 175@b = dso_local local_unnamed_addr global i32 0, align 4 176@c = dso_local local_unnamed_addr global [49 x i32] zeroinitializer, align 16 177@d = dso_local local_unnamed_addr global [49 x i32] zeroinitializer, align 16 178 179define void @PR42833() { 180; SSE2-LABEL: PR42833: 181; SSE2: # %bb.0: 182; SSE2-NEXT: movdqa c+{{.*}}(%rip), %xmm1 183; SSE2-NEXT: movdqa c+{{.*}}(%rip), %xmm0 184; SSE2-NEXT: movd %xmm0, %eax 185; SSE2-NEXT: addl {{.*}}(%rip), %eax 186; SSE2-NEXT: movd %eax, %xmm2 187; SSE2-NEXT: movaps {{.*#+}} xmm3 = <u,1,1,1> 188; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm2[0],xmm3[1,2,3] 189; SSE2-NEXT: movdqa %xmm0, %xmm4 190; SSE2-NEXT: paddd %xmm3, %xmm4 191; SSE2-NEXT: pslld $23, %xmm3 192; SSE2-NEXT: paddd {{.*}}(%rip), %xmm3 193; SSE2-NEXT: cvttps2dq %xmm3, %xmm3 194; SSE2-NEXT: movdqa %xmm0, %xmm5 195; SSE2-NEXT: pmuludq %xmm3, %xmm5 196; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] 197; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] 198; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3] 199; SSE2-NEXT: pmuludq %xmm3, %xmm6 200; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,2,2,3] 201; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1] 202; SSE2-NEXT: movss {{.*#+}} xmm5 = xmm4[0],xmm5[1,2,3] 203; SSE2-NEXT: movdqa d+{{.*}}(%rip), %xmm3 204; SSE2-NEXT: psubd %xmm1, %xmm3 205; SSE2-NEXT: paddd %xmm1, %xmm1 206; SSE2-NEXT: movdqa %xmm1, c+{{.*}}(%rip) 207; SSE2-NEXT: movaps %xmm5, c+{{.*}}(%rip) 208; SSE2-NEXT: movdqa c+{{.*}}(%rip), %xmm1 209; SSE2-NEXT: movdqa c+{{.*}}(%rip), %xmm4 210; SSE2-NEXT: movdqa d+{{.*}}(%rip), %xmm5 211; SSE2-NEXT: movdqa d+{{.*}}(%rip), %xmm6 212; SSE2-NEXT: movdqa d+{{.*}}(%rip), %xmm7 213; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3] 214; SSE2-NEXT: psubd %xmm0, %xmm7 215; SSE2-NEXT: psubd %xmm4, %xmm6 216; SSE2-NEXT: psubd %xmm1, %xmm5 217; SSE2-NEXT: movdqa %xmm5, d+{{.*}}(%rip) 218; SSE2-NEXT: movdqa %xmm6, d+{{.*}}(%rip) 219; SSE2-NEXT: movdqa %xmm3, d+{{.*}}(%rip) 220; SSE2-NEXT: movdqa %xmm7, d+{{.*}}(%rip) 221; SSE2-NEXT: paddd %xmm4, %xmm4 222; SSE2-NEXT: paddd %xmm1, %xmm1 223; SSE2-NEXT: movdqa %xmm1, c+{{.*}}(%rip) 224; SSE2-NEXT: movdqa %xmm4, c+{{.*}}(%rip) 225; SSE2-NEXT: retq 226; 227; SSE42-LABEL: PR42833: 228; SSE42: # %bb.0: 229; SSE42-NEXT: movdqa c+{{.*}}(%rip), %xmm1 230; SSE42-NEXT: movdqa c+{{.*}}(%rip), %xmm0 231; SSE42-NEXT: movd %xmm0, %eax 232; SSE42-NEXT: addl {{.*}}(%rip), %eax 233; SSE42-NEXT: movdqa {{.*#+}} xmm2 = <u,1,1,1> 234; SSE42-NEXT: pinsrd $0, %eax, %xmm2 235; SSE42-NEXT: movdqa %xmm0, %xmm3 236; SSE42-NEXT: paddd %xmm2, %xmm3 237; SSE42-NEXT: pslld $23, %xmm2 238; SSE42-NEXT: paddd {{.*}}(%rip), %xmm2 239; SSE42-NEXT: cvttps2dq %xmm2, %xmm2 240; SSE42-NEXT: pmulld %xmm0, %xmm2 241; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3,4,5,6,7] 242; SSE42-NEXT: movdqa d+{{.*}}(%rip), %xmm3 243; SSE42-NEXT: psubd %xmm1, %xmm3 244; SSE42-NEXT: paddd %xmm1, %xmm1 245; SSE42-NEXT: movdqa %xmm1, c+{{.*}}(%rip) 246; SSE42-NEXT: movdqa %xmm2, c+{{.*}}(%rip) 247; SSE42-NEXT: movdqa c+{{.*}}(%rip), %xmm1 248; SSE42-NEXT: movdqa c+{{.*}}(%rip), %xmm2 249; SSE42-NEXT: movdqa d+{{.*}}(%rip), %xmm4 250; SSE42-NEXT: movdqa d+{{.*}}(%rip), %xmm5 251; SSE42-NEXT: movdqa d+{{.*}}(%rip), %xmm6 252; SSE42-NEXT: pinsrd $0, %eax, %xmm0 253; SSE42-NEXT: psubd %xmm0, %xmm6 254; SSE42-NEXT: psubd %xmm2, %xmm5 255; SSE42-NEXT: psubd %xmm1, %xmm4 256; SSE42-NEXT: movdqa %xmm4, d+{{.*}}(%rip) 257; SSE42-NEXT: movdqa %xmm5, d+{{.*}}(%rip) 258; SSE42-NEXT: movdqa %xmm3, d+{{.*}}(%rip) 259; SSE42-NEXT: movdqa %xmm6, d+{{.*}}(%rip) 260; SSE42-NEXT: paddd %xmm2, %xmm2 261; SSE42-NEXT: paddd %xmm1, %xmm1 262; SSE42-NEXT: movdqa %xmm1, c+{{.*}}(%rip) 263; SSE42-NEXT: movdqa %xmm2, c+{{.*}}(%rip) 264; SSE42-NEXT: retq 265; 266; AVX1-LABEL: PR42833: 267; AVX1: # %bb.0: 268; AVX1-NEXT: vmovdqa c+{{.*}}(%rip), %xmm0 269; AVX1-NEXT: vmovd %xmm0, %eax 270; AVX1-NEXT: addl {{.*}}(%rip), %eax 271; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <u,1,1,1> 272; AVX1-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1 273; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm2 274; AVX1-NEXT: vmovdqa c+{{.*}}(%rip), %xmm3 275; AVX1-NEXT: vpslld $23, %xmm1, %xmm1 276; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1 277; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1 278; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm1 279; AVX1-NEXT: vpslld $1, %xmm3, %xmm3 280; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 281; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0],ymm1[1,2,3,4,5,6,7] 282; AVX1-NEXT: vmovdqa d+{{.*}}(%rip), %xmm2 283; AVX1-NEXT: vpsubd c+{{.*}}(%rip), %xmm2, %xmm2 284; AVX1-NEXT: vmovups %ymm1, c+{{.*}}(%rip) 285; AVX1-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0 286; AVX1-NEXT: vmovdqa d+{{.*}}(%rip), %xmm1 287; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0 288; AVX1-NEXT: vmovdqa d+{{.*}}(%rip), %xmm1 289; AVX1-NEXT: vmovdqa c+{{.*}}(%rip), %xmm3 290; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1 291; AVX1-NEXT: vmovdqa d+{{.*}}(%rip), %xmm4 292; AVX1-NEXT: vmovdqa c+{{.*}}(%rip), %xmm5 293; AVX1-NEXT: vpsubd %xmm5, %xmm4, %xmm4 294; AVX1-NEXT: vmovdqa %xmm2, d+{{.*}}(%rip) 295; AVX1-NEXT: vmovdqa %xmm4, d+{{.*}}(%rip) 296; AVX1-NEXT: vmovdqa %xmm1, d+{{.*}}(%rip) 297; AVX1-NEXT: vmovdqa %xmm0, d+{{.*}}(%rip) 298; AVX1-NEXT: vpaddd %xmm3, %xmm3, %xmm0 299; AVX1-NEXT: vpaddd %xmm5, %xmm5, %xmm1 300; AVX1-NEXT: vmovdqa %xmm1, c+{{.*}}(%rip) 301; AVX1-NEXT: vmovdqa %xmm0, c+{{.*}}(%rip) 302; AVX1-NEXT: vzeroupper 303; AVX1-NEXT: retq 304; 305; AVX2-LABEL: PR42833: 306; AVX2: # %bb.0: 307; AVX2-NEXT: movl {{.*}}(%rip), %eax 308; AVX2-NEXT: vmovdqu c+{{.*}}(%rip), %ymm0 309; AVX2-NEXT: addl c+{{.*}}(%rip), %eax 310; AVX2-NEXT: vmovd %eax, %xmm1 311; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm1[0],mem[1,2,3,4,5,6,7] 312; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm3 313; AVX2-NEXT: vpsllvd %ymm2, %ymm0, %ymm2 314; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0],ymm2[1,2,3,4,5,6,7] 315; AVX2-NEXT: vmovdqu %ymm2, c+{{.*}}(%rip) 316; AVX2-NEXT: vmovdqu c+{{.*}}(%rip), %ymm2 317; AVX2-NEXT: vmovdqu d+{{.*}}(%rip), %ymm3 318; AVX2-NEXT: vmovdqu d+{{.*}}(%rip), %ymm4 319; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3,4,5,6,7] 320; AVX2-NEXT: vpsubd %ymm0, %ymm4, %ymm0 321; AVX2-NEXT: vpsubd %ymm2, %ymm3, %ymm1 322; AVX2-NEXT: vmovdqu %ymm1, d+{{.*}}(%rip) 323; AVX2-NEXT: vmovdqu %ymm0, d+{{.*}}(%rip) 324; AVX2-NEXT: vpaddd %ymm2, %ymm2, %ymm0 325; AVX2-NEXT: vmovdqu %ymm0, c+{{.*}}(%rip) 326; AVX2-NEXT: vzeroupper 327; AVX2-NEXT: retq 328; 329; AVX512-LABEL: PR42833: 330; AVX512: # %bb.0: 331; AVX512-NEXT: movl {{.*}}(%rip), %eax 332; AVX512-NEXT: vmovdqu c+{{.*}}(%rip), %ymm0 333; AVX512-NEXT: vmovdqu64 c+{{.*}}(%rip), %zmm1 334; AVX512-NEXT: addl c+{{.*}}(%rip), %eax 335; AVX512-NEXT: vmovd %eax, %xmm2 336; AVX512-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],mem[1,2,3,4,5,6,7] 337; AVX512-NEXT: vpaddd %ymm2, %ymm0, %ymm3 338; AVX512-NEXT: vpsllvd %ymm2, %ymm0, %ymm0 339; AVX512-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0],ymm0[1,2,3,4,5,6,7] 340; AVX512-NEXT: vmovdqa c+{{.*}}(%rip), %xmm2 341; AVX512-NEXT: vmovdqu %ymm0, c+{{.*}}(%rip) 342; AVX512-NEXT: vmovdqu c+{{.*}}(%rip), %ymm0 343; AVX512-NEXT: vmovdqu64 d+{{.*}}(%rip), %zmm3 344; AVX512-NEXT: vpinsrd $0, %eax, %xmm2, %xmm2 345; AVX512-NEXT: vinserti32x4 $0, %xmm2, %zmm1, %zmm1 346; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm1 347; AVX512-NEXT: vpsubd %zmm1, %zmm3, %zmm1 348; AVX512-NEXT: vmovdqu64 %zmm1, d+{{.*}}(%rip) 349; AVX512-NEXT: vpaddd %ymm0, %ymm0, %ymm0 350; AVX512-NEXT: vmovdqu %ymm0, c+{{.*}}(%rip) 351; AVX512-NEXT: vzeroupper 352; AVX512-NEXT: retq 353; 354; XOP-LABEL: PR42833: 355; XOP: # %bb.0: 356; XOP-NEXT: vmovdqa c+{{.*}}(%rip), %xmm0 357; XOP-NEXT: vmovd %xmm0, %eax 358; XOP-NEXT: addl {{.*}}(%rip), %eax 359; XOP-NEXT: vmovdqa {{.*#+}} xmm1 = <u,1,1,1> 360; XOP-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1 361; XOP-NEXT: vpaddd %xmm1, %xmm0, %xmm2 362; XOP-NEXT: vmovdqa c+{{.*}}(%rip), %xmm3 363; XOP-NEXT: vpshld %xmm1, %xmm0, %xmm1 364; XOP-NEXT: vpslld $1, %xmm3, %xmm3 365; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 366; XOP-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0],ymm1[1,2,3,4,5,6,7] 367; XOP-NEXT: vmovdqa d+{{.*}}(%rip), %xmm2 368; XOP-NEXT: vpsubd c+{{.*}}(%rip), %xmm2, %xmm2 369; XOP-NEXT: vmovups %ymm1, c+{{.*}}(%rip) 370; XOP-NEXT: vpinsrd $0, %eax, %xmm0, %xmm0 371; XOP-NEXT: vmovdqa d+{{.*}}(%rip), %xmm1 372; XOP-NEXT: vpsubd %xmm0, %xmm1, %xmm0 373; XOP-NEXT: vmovdqa d+{{.*}}(%rip), %xmm1 374; XOP-NEXT: vmovdqa c+{{.*}}(%rip), %xmm3 375; XOP-NEXT: vpsubd %xmm3, %xmm1, %xmm1 376; XOP-NEXT: vmovdqa d+{{.*}}(%rip), %xmm4 377; XOP-NEXT: vmovdqa c+{{.*}}(%rip), %xmm5 378; XOP-NEXT: vpsubd %xmm5, %xmm4, %xmm4 379; XOP-NEXT: vmovdqa %xmm2, d+{{.*}}(%rip) 380; XOP-NEXT: vmovdqa %xmm4, d+{{.*}}(%rip) 381; XOP-NEXT: vmovdqa %xmm1, d+{{.*}}(%rip) 382; XOP-NEXT: vmovdqa %xmm0, d+{{.*}}(%rip) 383; XOP-NEXT: vpaddd %xmm3, %xmm3, %xmm0 384; XOP-NEXT: vpaddd %xmm5, %xmm5, %xmm1 385; XOP-NEXT: vmovdqa %xmm1, c+{{.*}}(%rip) 386; XOP-NEXT: vmovdqa %xmm0, c+{{.*}}(%rip) 387; XOP-NEXT: vzeroupper 388; XOP-NEXT: retq 389 %1 = load i32, i32* @b, align 4 390 %2 = load <8 x i32>, <8 x i32>* bitcast (i32* getelementptr inbounds ([49 x i32], [49 x i32]* @c, i64 0, i64 32) to <8 x i32>*), align 16 391 %3 = shufflevector <8 x i32> %2, <8 x i32> undef, <16 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 392 %4 = extractelement <8 x i32> %2, i32 0 393 %5 = add i32 %1, %4 394 %6 = insertelement <8 x i32> <i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i32 %5, i32 0 395 %7 = add <8 x i32> %2, %6 396 %8 = shl <8 x i32> %2, %6 397 %9 = shufflevector <8 x i32> %7, <8 x i32> %8, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 398 store <8 x i32> %9, <8 x i32>* bitcast (i32* getelementptr inbounds ([49 x i32], [49 x i32]* @c, i64 0, i64 32) to <8 x i32>*), align 16 399 %10 = load <8 x i32>, <8 x i32>* bitcast (i32* getelementptr inbounds ([49 x i32], [49 x i32]* @c, i64 0, i64 40) to <8 x i32>*), align 16 400 %11 = shufflevector <8 x i32> %10, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 401 %12 = load <16 x i32>, <16 x i32>* bitcast (i32* getelementptr inbounds ([49 x i32], [49 x i32]* @d, i64 0, i64 32) to <16 x i32>*), align 16 402 %13 = insertelement <16 x i32> %3, i32 %5, i32 0 403 %14 = shufflevector <16 x i32> %13, <16 x i32> %11, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23> 404 %15 = sub <16 x i32> %12, %14 405 store <16 x i32> %15, <16 x i32>* bitcast (i32* getelementptr inbounds ([49 x i32], [49 x i32]* @d, i64 0, i64 32) to <16 x i32>*), align 16 406 %16 = shl <8 x i32> %10, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> 407 store <8 x i32> %16, <8 x i32>* bitcast (i32* getelementptr inbounds ([49 x i32], [49 x i32]* @c, i64 0, i64 40) to <8 x i32>*), align 16 408 ret void 409} 410