1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
7
8;
9; Partial Vector Loads - PR16739
10;
11
12define <4 x float> @load_float4_float3(<4 x float>* nocapture readonly dereferenceable(16)) {
13; SSE-LABEL: load_float4_float3:
14; SSE:       # %bb.0:
15; SSE-NEXT:    movups (%rdi), %xmm0
16; SSE-NEXT:    retq
17;
18; AVX-LABEL: load_float4_float3:
19; AVX:       # %bb.0:
20; AVX-NEXT:    vmovups (%rdi), %xmm0
21; AVX-NEXT:    retq
22  %p0 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 0
23  %p1 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 1
24  %p2 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
25  %ld0 = load float, float* %p0, align 4
26  %ld1 = load float, float* %p1, align 4
27  %ld2 = load float, float* %p2, align 4
28  %r0 = insertelement <4 x float> undef, float %ld0, i32 0
29  %r1 = insertelement <4 x float> %r0,   float %ld1, i32 1
30  %r2 = insertelement <4 x float> %r1,   float %ld2, i32 2
31  ret <4 x float> %r2
32}
33
34define <8 x float> @load_float8_float3(<4 x float>* nocapture readonly dereferenceable(16)) {
35; SSE-LABEL: load_float8_float3:
36; SSE:       # %bb.0:
37; SSE-NEXT:    movups (%rdi), %xmm0
38; SSE-NEXT:    retq
39;
40; AVX-LABEL: load_float8_float3:
41; AVX:       # %bb.0:
42; AVX-NEXT:    vmovups (%rdi), %xmm0
43; AVX-NEXT:    retq
44  %p0 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 0
45  %p1 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 1
46  %p2 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
47  %ld0 = load float, float* %p0, align 4
48  %ld1 = load float, float* %p1, align 4
49  %ld2 = load float, float* %p2, align 4
50  %r0 = insertelement <8 x float> undef, float %ld0, i32 0
51  %r1 = insertelement <8 x float> %r0,   float %ld1, i32 1
52  %r2 = insertelement <8 x float> %r1,   float %ld2, i32 2
53  ret <8 x float> %r2
54}
55
56define <4 x float> @load_float4_float3_as_float2_float(<4 x float>* nocapture readonly dereferenceable(16)) {
57; SSE-LABEL: load_float4_float3_as_float2_float:
58; SSE:       # %bb.0:
59; SSE-NEXT:    movups (%rdi), %xmm0
60; SSE-NEXT:    retq
61;
62; AVX-LABEL: load_float4_float3_as_float2_float:
63; AVX:       # %bb.0:
64; AVX-NEXT:    vmovups (%rdi), %xmm0
65; AVX-NEXT:    retq
66  %2 = bitcast <4 x float>* %0 to <2 x float>*
67  %3 = load <2 x float>, <2 x float>* %2, align 4
68  %4 = extractelement <2 x float> %3, i32 0
69  %5 = insertelement <4 x float> undef, float %4, i32 0
70  %6 = extractelement <2 x float> %3, i32 1
71  %7 = insertelement <4 x float> %5, float %6, i32 1
72  %8 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
73  %9 = load float, float* %8, align 4
74  %10 = insertelement <4 x float> %7, float %9, i32 2
75  ret <4 x float> %10
76}
77
78define <4 x float> @load_float4_float3_trunc(<4 x float>* nocapture readonly dereferenceable(16)) {
79; SSE-LABEL: load_float4_float3_trunc:
80; SSE:       # %bb.0:
81; SSE-NEXT:    movaps (%rdi), %xmm0
82; SSE-NEXT:    retq
83;
84; AVX-LABEL: load_float4_float3_trunc:
85; AVX:       # %bb.0:
86; AVX-NEXT:    vmovaps (%rdi), %xmm0
87; AVX-NEXT:    retq
88  %2 = bitcast <4 x float>* %0 to i64*
89  %3 = load i64, i64* %2, align 16
90  %4 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
91  %5 = bitcast float* %4 to i64*
92  %6 = load i64, i64* %5, align 8
93  %7 = trunc i64 %3 to i32
94  %8 = bitcast i32 %7 to float
95  %9 = insertelement <4 x float> undef, float %8, i32 0
96  %10 = lshr i64 %3, 32
97  %11 = trunc i64 %10 to i32
98  %12 = bitcast i32 %11 to float
99  %13 = insertelement <4 x float> %9, float %12, i32 1
100  %14 = trunc i64 %6 to i32
101  %15 = bitcast i32 %14 to float
102  %16 = insertelement <4 x float> %13, float %15, i32 2
103  ret <4 x float> %16
104}
105
106; PR21780
107define <4 x double> @load_double4_0u2u(double* nocapture readonly dereferenceable(32)) {
108; SSE2-LABEL: load_double4_0u2u:
109; SSE2:       # %bb.0:
110; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
111; SSE2-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
112; SSE2-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0,0]
113; SSE2-NEXT:    movlhps {{.*#+}} xmm1 = xmm1[0,0]
114; SSE2-NEXT:    retq
115;
116; SSSE3-LABEL: load_double4_0u2u:
117; SSSE3:       # %bb.0:
118; SSSE3-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
119; SSSE3-NEXT:    movddup {{.*#+}} xmm1 = mem[0,0]
120; SSSE3-NEXT:    retq
121;
122; SSE41-LABEL: load_double4_0u2u:
123; SSE41:       # %bb.0:
124; SSE41-NEXT:    movddup {{.*#+}} xmm0 = mem[0,0]
125; SSE41-NEXT:    movddup {{.*#+}} xmm1 = mem[0,0]
126; SSE41-NEXT:    retq
127;
128; AVX-LABEL: load_double4_0u2u:
129; AVX:       # %bb.0:
130; AVX-NEXT:    vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
131; AVX-NEXT:    retq
132  %2 = load double, double* %0, align 8
133  %3 = insertelement <4 x double> undef, double %2, i32 0
134  %4 = getelementptr inbounds double, double* %0, i64 2
135  %5 = load double, double* %4, align 8
136  %6 = insertelement <4 x double> %3, double %5, i32 2
137  %7 = shufflevector <4 x double> %6, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
138  ret <4 x double> %7
139}
140
141; Test case identified in rL366501
142@h = local_unnamed_addr global i8 0, align 1
143define i32 @load_partial_illegal_type() {
144; SSE2-LABEL: load_partial_illegal_type:
145; SSE2:       # %bb.0:
146; SSE2-NEXT:    movzwl {{.*}}(%rip), %eax
147; SSE2-NEXT:    movd %eax, %xmm0
148; SSE2-NEXT:    pand {{.*}}(%rip), %xmm0
149; SSE2-NEXT:    por {{.*}}(%rip), %xmm0
150; SSE2-NEXT:    movd %xmm0, %eax
151; SSE2-NEXT:    retq
152;
153; SSSE3-LABEL: load_partial_illegal_type:
154; SSSE3:       # %bb.0:
155; SSSE3-NEXT:    movzwl {{.*}}(%rip), %eax
156; SSSE3-NEXT:    movd %eax, %xmm0
157; SSSE3-NEXT:    pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,xmm0[3,4,5,6,7,8,9,10,11,12,13,14,15]
158; SSSE3-NEXT:    por {{.*}}(%rip), %xmm0
159; SSSE3-NEXT:    movd %xmm0, %eax
160; SSSE3-NEXT:    retq
161;
162; SSE41-LABEL: load_partial_illegal_type:
163; SSE41:       # %bb.0:
164; SSE41-NEXT:    movzwl {{.*}}(%rip), %eax
165; SSE41-NEXT:    movd %eax, %xmm0
166; SSE41-NEXT:    movl $2, %eax
167; SSE41-NEXT:    pinsrb $2, %eax, %xmm0
168; SSE41-NEXT:    movd %xmm0, %eax
169; SSE41-NEXT:    retq
170;
171; AVX-LABEL: load_partial_illegal_type:
172; AVX:       # %bb.0:
173; AVX-NEXT:    movzwl {{.*}}(%rip), %eax
174; AVX-NEXT:    vmovd %eax, %xmm0
175; AVX-NEXT:    movl $2, %eax
176; AVX-NEXT:    vpinsrb $2, %eax, %xmm0, %xmm0
177; AVX-NEXT:    vmovd %xmm0, %eax
178; AVX-NEXT:    retq
179  %1 = load <2 x i8>, <2 x i8>* bitcast (i8* @h to <2 x i8>*), align 1
180  %2 = shufflevector <2 x i8> %1, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
181  %3 = insertelement <4 x i8> %2, i8 2, i32 2
182  %4 = bitcast <4 x i8> %3 to i32
183  ret i32 %4
184}
185
186