1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X86
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X64
4
5define <2 x double> @signbits_sext_v2i64_sitofp_v2f64(i32 %a0, i32 %a1) nounwind {
6; X86-LABEL: signbits_sext_v2i64_sitofp_v2f64:
7; X86:       # %bb.0:
8; X86-NEXT:    vcvtdq2pd {{[0-9]+}}(%esp), %xmm0
9; X86-NEXT:    retl
10;
11; X64-LABEL: signbits_sext_v2i64_sitofp_v2f64:
12; X64:       # %bb.0:
13; X64-NEXT:    vmovd %edi, %xmm0
14; X64-NEXT:    vpinsrd $1, %esi, %xmm0, %xmm0
15; X64-NEXT:    vcvtdq2pd %xmm0, %xmm0
16; X64-NEXT:    retq
17  %1 = sext i32 %a0 to i64
18  %2 = sext i32 %a1 to i64
19  %3 = insertelement <2 x i64> undef, i64 %1, i32 0
20  %4 = insertelement <2 x i64> %3, i64 %2, i32 1
21  %5 = sitofp <2 x i64> %4 to <2 x double>
22  ret <2 x double> %5
23}
24
25define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext %a1, i32 %a2, i32 %a3) nounwind {
26; X86-LABEL: signbits_sext_v4i64_sitofp_v4f32:
27; X86:       # %bb.0:
28; X86-NEXT:    movswl {{[0-9]+}}(%esp), %eax
29; X86-NEXT:    movsbl {{[0-9]+}}(%esp), %ecx
30; X86-NEXT:    vmovd %ecx, %xmm0
31; X86-NEXT:    vpinsrd $1, %eax, %xmm0, %xmm0
32; X86-NEXT:    vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
33; X86-NEXT:    vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
34; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
35; X86-NEXT:    retl
36;
37; X64-LABEL: signbits_sext_v4i64_sitofp_v4f32:
38; X64:       # %bb.0:
39; X64-NEXT:    vmovd %edi, %xmm0
40; X64-NEXT:    vpinsrd $1, %esi, %xmm0, %xmm0
41; X64-NEXT:    vpinsrd $2, %edx, %xmm0, %xmm0
42; X64-NEXT:    vpinsrd $3, %ecx, %xmm0, %xmm0
43; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
44; X64-NEXT:    retq
45  %1 = sext i8 %a0 to i64
46  %2 = sext i16 %a1 to i64
47  %3 = sext i32 %a2 to i64
48  %4 = sext i32 %a3 to i64
49  %5 = insertelement <4 x i64> undef, i64 %1, i32 0
50  %6 = insertelement <4 x i64> %5, i64 %2, i32 1
51  %7 = insertelement <4 x i64> %6, i64 %3, i32 2
52  %8 = insertelement <4 x i64> %7, i64 %4, i32 3
53  %9 = sitofp <4 x i64> %8 to <4 x float>
54  ret <4 x float> %9
55}
56
57define float @signbits_ashr_extract_sitofp_0(<2 x i64> %a0) nounwind {
58; X86-LABEL: signbits_ashr_extract_sitofp_0:
59; X86:       # %bb.0:
60; X86-NEXT:    pushl %eax
61; X86-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
62; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
63; X86-NEXT:    vmovss %xmm0, (%esp)
64; X86-NEXT:    flds (%esp)
65; X86-NEXT:    popl %eax
66; X86-NEXT:    retl
67;
68; X64-LABEL: signbits_ashr_extract_sitofp_0:
69; X64:       # %bb.0:
70; X64-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
71; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
72; X64-NEXT:    retq
73  %1 = ashr <2 x i64> %a0, <i64 32, i64 32>
74  %2 = extractelement <2 x i64> %1, i32 0
75  %3 = sitofp i64 %2 to float
76  ret float %3
77}
78
79define float @signbits_ashr_extract_sitofp_1(<2 x i64> %a0) nounwind {
80; X86-LABEL: signbits_ashr_extract_sitofp_1:
81; X86:       # %bb.0:
82; X86-NEXT:    pushl %eax
83; X86-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
84; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
85; X86-NEXT:    vmovss %xmm0, (%esp)
86; X86-NEXT:    flds (%esp)
87; X86-NEXT:    popl %eax
88; X86-NEXT:    retl
89;
90; X64-LABEL: signbits_ashr_extract_sitofp_1:
91; X64:       # %bb.0:
92; X64-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3]
93; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
94; X64-NEXT:    retq
95  %1 = ashr <2 x i64> %a0, <i64 32, i64 63>
96  %2 = extractelement <2 x i64> %1, i32 0
97  %3 = sitofp i64 %2 to float
98  ret float %3
99}
100
101define float @signbits_ashr_shl_extract_sitofp(<2 x i64> %a0) nounwind {
102; X86-LABEL: signbits_ashr_shl_extract_sitofp:
103; X86:       # %bb.0:
104; X86-NEXT:    pushl %eax
105; X86-NEXT:    vpsrad $29, %xmm0, %xmm0
106; X86-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
107; X86-NEXT:    vpsllq $20, %xmm0, %xmm0
108; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
109; X86-NEXT:    vmovss %xmm0, (%esp)
110; X86-NEXT:    flds (%esp)
111; X86-NEXT:    popl %eax
112; X86-NEXT:    retl
113;
114; X64-LABEL: signbits_ashr_shl_extract_sitofp:
115; X64:       # %bb.0:
116; X64-NEXT:    vpsrad $29, %xmm0, %xmm0
117; X64-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
118; X64-NEXT:    vpsllq $20, %xmm0, %xmm0
119; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
120; X64-NEXT:    retq
121  %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
122  %2 = shl <2 x i64> %1, <i64 20, i64 16>
123  %3 = extractelement <2 x i64> %2, i32 0
124  %4 = sitofp i64 %3 to float
125  ret float %4
126}
127
128define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwind {
129; X86-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
130; X86:       # %bb.0:
131; X86-NEXT:    pushl %eax
132; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
133; X86-NEXT:    movl %eax, %ecx
134; X86-NEXT:    sarl $30, %ecx
135; X86-NEXT:    shll $2, %eax
136; X86-NEXT:    vmovd %eax, %xmm0
137; X86-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
138; X86-NEXT:    vpsrlq $3, %xmm0, %xmm0
139; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
140; X86-NEXT:    vmovss %xmm0, (%esp)
141; X86-NEXT:    flds (%esp)
142; X86-NEXT:    popl %eax
143; X86-NEXT:    retl
144;
145; X64-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
146; X64:       # %bb.0:
147; X64-NEXT:    sarq $30, %rdi
148; X64-NEXT:    vmovq %rdi, %xmm0
149; X64-NEXT:    vpsrlq $3, %xmm0, %xmm0
150; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
151; X64-NEXT:    retq
152  %1 = ashr i64 %a0, 30
153  %2 = insertelement <2 x i64> undef, i64 %1, i32 0
154  %3 = insertelement <2 x i64> %2, i64 %a1, i32 1
155  %4 = ashr <2 x i64> %3, <i64 3, i64 3>
156  %5 = extractelement <2 x i64> %4, i32 0
157  %6 = sitofp i64 %5 to float
158  ret float %6
159}
160
161define <4 x double> @signbits_sext_shuffle_sitofp(<4 x i32> %a0, <4 x i64> %a1) nounwind {
162; CHECK-LABEL: signbits_sext_shuffle_sitofp:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    vpmovsxdq %xmm0, %xmm1
165; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
166; CHECK-NEXT:    vpmovsxdq %xmm0, %xmm0
167; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
168; CHECK-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
169; CHECK-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
170; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
171; CHECK-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
172; CHECK-NEXT:    vcvtdq2pd %xmm0, %ymm0
173; CHECK-NEXT:    ret{{[l|q]}}
174  %1 = sext <4 x i32> %a0 to <4 x i64>
175  %2 = shufflevector <4 x i64> %1, <4 x i64>%a1, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
176  %3 = sitofp <4 x i64> %2 to <4 x double>
177  ret <4 x double> %3
178}
179
180; TODO: Fix vpshufd+vpsrlq -> vpshufd/vpermilps
181define <2 x double> @signbits_ashr_concat_ashr_extract_sitofp(<2 x i64> %a0, <4 x i64> %a1) nounwind {
182; X86-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
183; X86:       # %bb.0:
184; X86-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3]
185; X86-NEXT:    vcvtdq2pd %xmm0, %xmm0
186; X86-NEXT:    retl
187;
188; X64-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
189; X64:       # %bb.0:
190; X64-NEXT:    vpsrlq $32, %xmm0, %xmm0
191; X64-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
192; X64-NEXT:    vcvtdq2pd %xmm0, %xmm0
193; X64-NEXT:    retq
194  %1 = ashr <2 x i64> %a0, <i64 16, i64 16>
195  %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
196  %3 = shufflevector <4 x i64> %a1, <4 x i64> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
197  %4 = ashr <4 x i64> %3, <i64 16, i64 16, i64 16, i64 16>
198  %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
199  %6 = sitofp <2 x i64> %5 to <2 x double>
200  ret <2 x double> %6
201}
202
203define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind {
204; X86-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
205; X86:       # %bb.0:
206; X86-NEXT:    pushl %eax
207; X86-NEXT:    vpsrad $29, %xmm0, %xmm0
208; X86-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
209; X86-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
210; X86-NEXT:    vpand %xmm1, %xmm0, %xmm0
211; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
212; X86-NEXT:    vmovss %xmm0, (%esp)
213; X86-NEXT:    flds (%esp)
214; X86-NEXT:    popl %eax
215; X86-NEXT:    retl
216;
217; X64-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
218; X64:       # %bb.0:
219; X64-NEXT:    vpsrad $29, %xmm0, %xmm0
220; X64-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
221; X64-NEXT:    vmovd %edi, %xmm1
222; X64-NEXT:    vpand %xmm1, %xmm0, %xmm0
223; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
224; X64-NEXT:    retq
225  %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
226  %2 = sext i32 %a2 to i64
227  %3 = insertelement <2 x i64> %a1, i64 %2, i32 0
228  %4 = shl <2 x i64> %3, <i64 20, i64 20>
229  %5 = ashr <2 x i64> %4, <i64 20, i64 20>
230  %6 = and <2 x i64> %1, %5
231  %7 = extractelement <2 x i64> %6, i32 0
232  %8 = sitofp i64 %7 to float
233  ret float %8
234}
235
236define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind {
237; X86-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
238; X86:       # %bb.0:
239; X86-NEXT:    pushl %eax
240; X86-NEXT:    vpsrlq $60, %xmm0, %xmm2
241; X86-NEXT:    vpsrlq $61, %xmm0, %xmm0
242; X86-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
243; X86-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,0,8,0]
244; X86-NEXT:    vpxor %xmm2, %xmm0, %xmm0
245; X86-NEXT:    vpsubq %xmm2, %xmm0, %xmm0
246; X86-NEXT:    vpmovsxdq %xmm1, %xmm1
247; X86-NEXT:    vpand %xmm1, %xmm0, %xmm2
248; X86-NEXT:    vpor %xmm1, %xmm2, %xmm1
249; X86-NEXT:    vpxor %xmm0, %xmm1, %xmm0
250; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
251; X86-NEXT:    vmovss %xmm0, (%esp)
252; X86-NEXT:    flds (%esp)
253; X86-NEXT:    popl %eax
254; X86-NEXT:    retl
255;
256; X64-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
257; X64:       # %bb.0:
258; X64-NEXT:    vpsrlq $60, %xmm0, %xmm2
259; X64-NEXT:    vpsrlq $61, %xmm0, %xmm0
260; X64-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
261; X64-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,8]
262; X64-NEXT:    vpxor %xmm2, %xmm0, %xmm0
263; X64-NEXT:    vpsubq %xmm2, %xmm0, %xmm0
264; X64-NEXT:    vpmovsxdq %xmm1, %xmm1
265; X64-NEXT:    vpand %xmm1, %xmm0, %xmm2
266; X64-NEXT:    vpor %xmm1, %xmm2, %xmm1
267; X64-NEXT:    vpxor %xmm0, %xmm1, %xmm0
268; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
269; X64-NEXT:    retq
270  %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
271  %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
272  %3 = sext <2 x i32> %2 to <2 x i64>
273  %4 = and <2 x i64> %1, %3
274  %5 = or <2 x i64> %4, %3
275  %6 = xor <2 x i64> %5, %1
276  %7 = extractelement <2 x i64> %6, i32 0
277  %8 = sitofp i64 %7 to float
278  ret float %8
279}
280
281define <4 x float> @signbits_ashr_sext_select_shuffle_sitofp(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2, <4 x i32> %a3) nounwind {
282; X86-LABEL: signbits_ashr_sext_select_shuffle_sitofp:
283; X86:       # %bb.0:
284; X86-NEXT:    pushl %ebp
285; X86-NEXT:    movl %esp, %ebp
286; X86-NEXT:    andl $-16, %esp
287; X86-NEXT:    subl $16, %esp
288; X86-NEXT:    vpmovsxdq 8(%ebp), %xmm3
289; X86-NEXT:    vpmovsxdq 16(%ebp), %xmm4
290; X86-NEXT:    vpsrad $31, %xmm2, %xmm5
291; X86-NEXT:    vpsrad $1, %xmm2, %xmm6
292; X86-NEXT:    vpshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
293; X86-NEXT:    vpblendw {{.*#+}} xmm5 = xmm6[0,1],xmm5[2,3],xmm6[4,5],xmm5[6,7]
294; X86-NEXT:    vextractf128 $1, %ymm2, %xmm2
295; X86-NEXT:    vpsrad $31, %xmm2, %xmm6
296; X86-NEXT:    vpsrad $1, %xmm2, %xmm2
297; X86-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
298; X86-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3],xmm2[4,5],xmm6[6,7]
299; X86-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm6
300; X86-NEXT:    vblendvpd %xmm6, %xmm5, %xmm3, %xmm3
301; X86-NEXT:    vextractf128 $1, %ymm1, %xmm1
302; X86-NEXT:    vextractf128 $1, %ymm0, %xmm0
303; X86-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0
304; X86-NEXT:    vblendvpd %xmm0, %xmm2, %xmm4, %xmm0
305; X86-NEXT:    vinsertf128 $1, %xmm0, %ymm3, %ymm0
306; X86-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
307; X86-NEXT:    vextractf128 $1, %ymm0, %xmm1
308; X86-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
309; X86-NEXT:    vcvtdq2ps %xmm0, %xmm0
310; X86-NEXT:    movl %ebp, %esp
311; X86-NEXT:    popl %ebp
312; X86-NEXT:    vzeroupper
313; X86-NEXT:    retl
314;
315; X64-LABEL: signbits_ashr_sext_select_shuffle_sitofp:
316; X64:       # %bb.0:
317; X64-NEXT:    vpsrad $31, %xmm2, %xmm4
318; X64-NEXT:    vpsrad $1, %xmm2, %xmm5
319; X64-NEXT:    vpshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
320; X64-NEXT:    vpblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
321; X64-NEXT:    vextractf128 $1, %ymm2, %xmm2
322; X64-NEXT:    vpsrad $31, %xmm2, %xmm5
323; X64-NEXT:    vpsrad $1, %xmm2, %xmm2
324; X64-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
325; X64-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5],xmm5[6,7]
326; X64-NEXT:    vpmovsxdq %xmm3, %xmm5
327; X64-NEXT:    vpshufd {{.*#+}} xmm3 = xmm3[2,3,0,1]
328; X64-NEXT:    vpmovsxdq %xmm3, %xmm3
329; X64-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm6
330; X64-NEXT:    vblendvpd %xmm6, %xmm4, %xmm5, %xmm4
331; X64-NEXT:    vextractf128 $1, %ymm1, %xmm1
332; X64-NEXT:    vextractf128 $1, %ymm0, %xmm0
333; X64-NEXT:    vpcmpeqq %xmm1, %xmm0, %xmm0
334; X64-NEXT:    vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
335; X64-NEXT:    vinsertf128 $1, %xmm0, %ymm4, %ymm0
336; X64-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
337; X64-NEXT:    vextractf128 $1, %ymm0, %xmm1
338; X64-NEXT:    vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
339; X64-NEXT:    vcvtdq2ps %xmm0, %xmm0
340; X64-NEXT:    vzeroupper
341; X64-NEXT:    retq
342  %1 = ashr <4 x i64> %a2, <i64 33, i64 63, i64 33, i64 63>
343  %2 = sext <4 x i32> %a3 to <4 x i64>
344  %3 = icmp eq <4 x i64> %a0, %a1
345  %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
346  %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
347  %6 = sitofp <4 x i64> %5 to <4 x float>
348  ret <4 x float> %6
349}
350
351; Make sure we can preserve sign bit information into the second basic block
352; so we can avoid having to shift bit 0 into bit 7 for each element due to
353; v32i1->v32i8 promotion and the splitting of v32i8 into 2xv16i8. This requires
354; ComputeNumSignBits handling for insert_subvector.
355define void @cross_bb_signbits_insert_subvec(<32 x i8>* %ptr, <32 x i8> %x, <32 x i8> %z) {
356; X86-LABEL: cross_bb_signbits_insert_subvec:
357; X86:       # %bb.0:
358; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
359; X86-NEXT:    vextractf128 $1, %ymm0, %xmm2
360; X86-NEXT:    vpxor %xmm3, %xmm3, %xmm3
361; X86-NEXT:    vpcmpeqb %xmm3, %xmm2, %xmm2
362; X86-NEXT:    vpcmpeqb %xmm3, %xmm0, %xmm0
363; X86-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
364; X86-NEXT:    vandnps %ymm1, %ymm0, %ymm1
365; X86-NEXT:    vandps {{\.LCPI.*}}, %ymm0, %ymm0
366; X86-NEXT:    vorps %ymm1, %ymm0, %ymm0
367; X86-NEXT:    vmovaps %ymm0, (%eax)
368; X86-NEXT:    vzeroupper
369; X86-NEXT:    retl
370;
371; X64-LABEL: cross_bb_signbits_insert_subvec:
372; X64:       # %bb.0:
373; X64-NEXT:    vextractf128 $1, %ymm0, %xmm2
374; X64-NEXT:    vpxor %xmm3, %xmm3, %xmm3
375; X64-NEXT:    vpcmpeqb %xmm3, %xmm2, %xmm2
376; X64-NEXT:    vpcmpeqb %xmm3, %xmm0, %xmm0
377; X64-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
378; X64-NEXT:    vandnps %ymm1, %ymm0, %ymm1
379; X64-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
380; X64-NEXT:    vorps %ymm1, %ymm0, %ymm0
381; X64-NEXT:    vmovaps %ymm0, (%rdi)
382; X64-NEXT:    vzeroupper
383; X64-NEXT:    retq
384  %a = icmp eq <32 x i8> %x, zeroinitializer
385  %b = icmp eq <32 x i8> %x, zeroinitializer
386  %c = and <32 x i1> %a, %b
387  br label %block
388
389block:
390  %d = select <32 x i1> %c, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> %z
391  store <32 x i8> %d, <32 x i8>* %ptr, align 32
392  br label %exit
393
394exit:
395  ret void
396}
397
398