1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 4 5define i32 @knownbits_mask_extract_sext(<8 x i16> %a0) nounwind { 6; X32-LABEL: knownbits_mask_extract_sext: 7; X32: # %bb.0: 8; X32-NEXT: vmovd %xmm0, %eax 9; X32-NEXT: andl $15, %eax 10; X32-NEXT: retl 11; 12; X64-LABEL: knownbits_mask_extract_sext: 13; X64: # %bb.0: 14; X64-NEXT: vmovd %xmm0, %eax 15; X64-NEXT: andl $15, %eax 16; X64-NEXT: retq 17 %1 = and <8 x i16> %a0, <i16 15, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 18 %2 = extractelement <8 x i16> %1, i32 0 19 %3 = sext i16 %2 to i32 20 ret i32 %3 21} 22 23define float @knownbits_mask_extract_uitofp(<2 x i64> %a0) nounwind { 24; X32-LABEL: knownbits_mask_extract_uitofp: 25; X32: # %bb.0: 26; X32-NEXT: pushl %eax 27; X32-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero 28; X32-NEXT: vmovd %xmm0, %eax 29; X32-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0 30; X32-NEXT: vmovss %xmm0, (%esp) 31; X32-NEXT: flds (%esp) 32; X32-NEXT: popl %eax 33; X32-NEXT: retl 34; 35; X64-LABEL: knownbits_mask_extract_uitofp: 36; X64: # %bb.0: 37; X64-NEXT: vmovq %xmm0, %rax 38; X64-NEXT: movzwl %ax, %eax 39; X64-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0 40; X64-NEXT: retq 41 %1 = and <2 x i64> %a0, <i64 65535, i64 -1> 42 %2 = extractelement <2 x i64> %1, i32 0 43 %3 = uitofp i64 %2 to float 44 ret float %3 45} 46 47define <4 x float> @knownbits_insert_uitofp(<4 x i32> %a0, i16 %a1, i16 %a2) nounwind { 48; X32-LABEL: knownbits_insert_uitofp: 49; X32: # %bb.0: 50; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax 51; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx 52; X32-NEXT: vmovd %ecx, %xmm0 53; X32-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0 54; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] 55; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 56; X32-NEXT: retl 57; 58; X64-LABEL: knownbits_insert_uitofp: 59; X64: # %bb.0: 60; X64-NEXT: movzwl %di, %eax 61; X64-NEXT: movzwl %si, %ecx 62; X64-NEXT: vmovd %eax, %xmm0 63; X64-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0 64; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2] 65; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 66; X64-NEXT: retq 67 %1 = zext i16 %a1 to i32 68 %2 = zext i16 %a2 to i32 69 %3 = insertelement <4 x i32> %a0, i32 %1, i32 0 70 %4 = insertelement <4 x i32> %3, i32 %2, i32 2 71 %5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> 72 %6 = uitofp <4 x i32> %5 to <4 x float> 73 ret <4 x float> %6 74} 75 76define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind { 77; X32-LABEL: knownbits_mask_shuffle_sext: 78; X32: # %bb.0: 79; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 80; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 81; X32-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 82; X32-NEXT: retl 83; 84; X64-LABEL: knownbits_mask_shuffle_sext: 85; X64: # %bb.0: 86; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 87; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 88; X64-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 89; X64-NEXT: retq 90 %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15> 91 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 92 %3 = sext <4 x i16> %2 to <4 x i32> 93 ret <4 x i32> %3 94} 95 96define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind { 97; X32-LABEL: knownbits_mask_shuffle_shuffle_sext: 98; X32: # %bb.0: 99; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 100; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 101; X32-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 102; X32-NEXT: retl 103; 104; X64-LABEL: knownbits_mask_shuffle_shuffle_sext: 105; X64: # %bb.0: 106; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 107; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 108; X64-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 109; X64-NEXT: retq 110 %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15> 111 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> 112 %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 113 %4 = sext <4 x i16> %3 to <4 x i32> 114 ret <4 x i32> %4 115} 116 117define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounwind { 118; X32-LABEL: knownbits_mask_shuffle_shuffle_undef_sext: 119; X32: # %bb.0: 120; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 121; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 122; X32-NEXT: vpmovsxwd %xmm0, %xmm0 123; X32-NEXT: retl 124; 125; X64-LABEL: knownbits_mask_shuffle_shuffle_undef_sext: 126; X64: # %bb.0: 127; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 128; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] 129; X64-NEXT: vpmovsxwd %xmm0, %xmm0 130; X64-NEXT: retq 131 %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15> 132 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 133 %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 134 %4 = sext <4 x i16> %3 to <4 x i32> 135 ret <4 x i32> %4 136} 137 138define <4 x float> @knownbits_mask_shuffle_uitofp(<4 x i32> %a0) nounwind { 139; X32-LABEL: knownbits_mask_shuffle_uitofp: 140; X32: # %bb.0: 141; X32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 142; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] 143; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 144; X32-NEXT: retl 145; 146; X64-LABEL: knownbits_mask_shuffle_uitofp: 147; X64: # %bb.0: 148; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 149; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] 150; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 151; X64-NEXT: retq 152 %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085> 153 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> 154 %3 = uitofp <4 x i32> %2 to <4 x float> 155 ret <4 x float> %3 156} 157 158define <4 x float> @knownbits_mask_or_shuffle_uitofp(<4 x i32> %a0) nounwind { 159; X32-LABEL: knownbits_mask_or_shuffle_uitofp: 160; X32: # %bb.0: 161; X32-NEXT: vmovaps {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4] 162; X32-NEXT: retl 163; 164; X64-LABEL: knownbits_mask_or_shuffle_uitofp: 165; X64: # %bb.0: 166; X64-NEXT: vmovaps {{.*#+}} xmm0 = [6.5535E+4,6.5535E+4,6.5535E+4,6.5535E+4] 167; X64-NEXT: retq 168 %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085> 169 %2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535> 170 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> 171 %4 = uitofp <4 x i32> %3 to <4 x float> 172 ret <4 x float> %4 173} 174 175define <4 x float> @knownbits_mask_xor_shuffle_uitofp(<4 x i32> %a0) nounwind { 176; X32-LABEL: knownbits_mask_xor_shuffle_uitofp: 177; X32: # %bb.0: 178; X32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 179; X32-NEXT: vxorps {{\.LCPI.*}}, %xmm0, %xmm0 180; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] 181; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 182; X32-NEXT: retl 183; 184; X64-LABEL: knownbits_mask_xor_shuffle_uitofp: 185; X64: # %bb.0: 186; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 187; X64-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0 188; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] 189; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 190; X64-NEXT: retq 191 %1 = and <4 x i32> %a0, <i32 -1, i32 -1, i32 255, i32 4085> 192 %2 = xor <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535> 193 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> 194 %4 = uitofp <4 x i32> %3 to <4 x float> 195 ret <4 x float> %4 196} 197 198define <4 x i32> @knownbits_mask_shl_shuffle_lshr(<4 x i32> %a0) nounwind { 199; X32-LABEL: knownbits_mask_shl_shuffle_lshr: 200; X32: # %bb.0: 201; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 202; X32-NEXT: retl 203; 204; X64-LABEL: knownbits_mask_shl_shuffle_lshr: 205; X64: # %bb.0: 206; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 207; X64-NEXT: retq 208 %1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536> 209 %2 = shl <4 x i32> %1, <i32 17, i32 17, i32 17, i32 17> 210 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 211 %4 = lshr <4 x i32> %3, <i32 15, i32 15, i32 15, i32 15> 212 ret <4 x i32> %4 213} 214 215define <4 x i32> @knownbits_mask_ashr_shuffle_lshr(<4 x i32> %a0) nounwind { 216; X32-LABEL: knownbits_mask_ashr_shuffle_lshr: 217; X32: # %bb.0: 218; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 219; X32-NEXT: retl 220; 221; X64-LABEL: knownbits_mask_ashr_shuffle_lshr: 222; X64: # %bb.0: 223; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 224; X64-NEXT: retq 225 %1 = and <4 x i32> %a0, <i32 131071, i32 -1, i32 -1, i32 131071> 226 %2 = ashr <4 x i32> %1, <i32 15, i32 15, i32 15, i32 15> 227 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 228 %4 = lshr <4 x i32> %3, <i32 30, i32 30, i32 30, i32 30> 229 ret <4 x i32> %4 230} 231 232define <4 x i32> @knownbits_mask_mul_shuffle_shl(<4 x i32> %a0, <4 x i32> %a1) nounwind { 233; X32-LABEL: knownbits_mask_mul_shuffle_shl: 234; X32: # %bb.0: 235; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 236; X32-NEXT: retl 237; 238; X64-LABEL: knownbits_mask_mul_shuffle_shl: 239; X64: # %bb.0: 240; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 241; X64-NEXT: retq 242 %1 = and <4 x i32> %a0, <i32 -65536, i32 -7, i32 -7, i32 -65536> 243 %2 = mul <4 x i32> %a1, %1 244 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 245 %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> 246 ret <4 x i32> %4 247} 248 249define <4 x i32> @knownbits_mask_trunc_shuffle_shl(<4 x i64> %a0) nounwind { 250; X32-LABEL: knownbits_mask_trunc_shuffle_shl: 251; X32: # %bb.0: 252; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 253; X32-NEXT: retl 254; 255; X64-LABEL: knownbits_mask_trunc_shuffle_shl: 256; X64: # %bb.0: 257; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 258; X64-NEXT: retq 259 %1 = and <4 x i64> %a0, <i64 -65536, i64 -7, i64 7, i64 -65536> 260 %2 = trunc <4 x i64> %1 to <4 x i32> 261 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 262 %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> 263 ret <4 x i32> %4 264} 265 266define <4 x i32> @knownbits_mask_add_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind { 267; X32-LABEL: knownbits_mask_add_shuffle_lshr: 268; X32: # %bb.0: 269; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 270; X32-NEXT: retl 271; 272; X64-LABEL: knownbits_mask_add_shuffle_lshr: 273; X64: # %bb.0: 274; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 275; X64-NEXT: retq 276 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767> 277 %2 = and <4 x i32> %a1, <i32 32767, i32 -1, i32 -1, i32 32767> 278 %3 = add <4 x i32> %1, %2 279 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 280 %5 = lshr <4 x i32> %4, <i32 17, i32 17, i32 17, i32 17> 281 ret <4 x i32> %5 282} 283 284define <4 x i32> @knownbits_mask_sub_shuffle_lshr(<4 x i32> %a0) nounwind { 285; X32-LABEL: knownbits_mask_sub_shuffle_lshr: 286; X32: # %bb.0: 287; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 288; X32-NEXT: retl 289; 290; X64-LABEL: knownbits_mask_sub_shuffle_lshr: 291; X64: # %bb.0: 292; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 293; X64-NEXT: retq 294 %1 = and <4 x i32> %a0, <i32 15, i32 -1, i32 -1, i32 15> 295 %2 = sub <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %1 296 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 297 %4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> 298 ret <4 x i32> %4 299} 300 301define <4 x i32> @knownbits_mask_udiv_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind { 302; X32-LABEL: knownbits_mask_udiv_shuffle_lshr: 303; X32: # %bb.0: 304; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 305; X32-NEXT: retl 306; 307; X64-LABEL: knownbits_mask_udiv_shuffle_lshr: 308; X64: # %bb.0: 309; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 310; X64-NEXT: retq 311 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767> 312 %2 = udiv <4 x i32> %1, %a1 313 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 314 %4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> 315 ret <4 x i32> %4 316} 317 318define <4 x i32> @knownbits_urem_lshr(<4 x i32> %a0) nounwind { 319; X32-LABEL: knownbits_urem_lshr: 320; X32: # %bb.0: 321; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 322; X32-NEXT: retl 323; 324; X64-LABEL: knownbits_urem_lshr: 325; X64: # %bb.0: 326; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 327; X64-NEXT: retq 328 %1 = urem <4 x i32> %a0, <i32 16, i32 16, i32 16, i32 16> 329 %2 = lshr <4 x i32> %1, <i32 22, i32 22, i32 22, i32 22> 330 ret <4 x i32> %2 331} 332 333define <4 x i32> @knownbits_mask_urem_shuffle_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind { 334; X32-LABEL: knownbits_mask_urem_shuffle_lshr: 335; X32: # %bb.0: 336; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 337; X32-NEXT: retl 338; 339; X64-LABEL: knownbits_mask_urem_shuffle_lshr: 340; X64: # %bb.0: 341; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 342; X64-NEXT: retq 343 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767> 344 %2 = and <4 x i32> %a1, <i32 32767, i32 -1, i32 -1, i32 32767> 345 %3 = urem <4 x i32> %1, %2 346 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 347 %5 = lshr <4 x i32> %4, <i32 22, i32 22, i32 22, i32 22> 348 ret <4 x i32> %5 349} 350 351define <4 x i32> @knownbits_mask_srem_shuffle_lshr(<4 x i32> %a0) nounwind { 352; X32-LABEL: knownbits_mask_srem_shuffle_lshr: 353; X32: # %bb.0: 354; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 355; X32-NEXT: retl 356; 357; X64-LABEL: knownbits_mask_srem_shuffle_lshr: 358; X64: # %bb.0: 359; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 360; X64-NEXT: retq 361 %1 = and <4 x i32> %a0, <i32 -32768, i32 -1, i32 -1, i32 -32768> 362 %2 = srem <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16> 363 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 364 %4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> 365 ret <4 x i32> %4 366} 367 368define <4 x i32> @knownbits_mask_bswap_shuffle_shl(<4 x i32> %a0) nounwind { 369; X32-LABEL: knownbits_mask_bswap_shuffle_shl: 370; X32: # %bb.0: 371; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 372; X32-NEXT: retl 373; 374; X64-LABEL: knownbits_mask_bswap_shuffle_shl: 375; X64: # %bb.0: 376; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 377; X64-NEXT: retq 378 %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767> 379 %2 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %1) 380 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 381 %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> 382 ret <4 x i32> %4 383} 384declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) 385 386define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) nounwind { 387; X32-LABEL: knownbits_mask_concat_uitofp: 388; X32: # %bb.0: 389; X32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 390; X32-NEXT: vandps {{\.LCPI.*}}, %xmm1, %xmm1 391; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2] 392; X32-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3] 393; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 394; X32-NEXT: vcvtdq2ps %ymm0, %ymm0 395; X32-NEXT: retl 396; 397; X64-LABEL: knownbits_mask_concat_uitofp: 398; X64: # %bb.0: 399; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 400; X64-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1 401; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2] 402; X64-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3] 403; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 404; X64-NEXT: vcvtdq2ps %ymm0, %ymm0 405; X64-NEXT: retq 406 %1 = and <4 x i32> %a0, <i32 131071, i32 -1, i32 131071, i32 -1> 407 %2 = and <4 x i32> %a1, <i32 -1, i32 131071, i32 -1, i32 131071> 408 %3 = shufflevector <4 x i32> %1, <4 x i32> %2, <8 x i32> <i32 0, i32 2, i32 0, i32 2, i32 5, i32 7, i32 5, i32 7> 409 %4 = uitofp <8 x i32> %3 to <8 x float> 410 ret <8 x float> %4 411} 412 413define <4 x float> @knownbits_lshr_bitcast_shuffle_uitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind { 414; X32-LABEL: knownbits_lshr_bitcast_shuffle_uitofp: 415; X32: # %bb.0: 416; X32-NEXT: vpsrlq $1, %xmm0, %xmm0 417; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 418; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 419; X32-NEXT: retl 420; 421; X64-LABEL: knownbits_lshr_bitcast_shuffle_uitofp: 422; X64: # %bb.0: 423; X64-NEXT: vpsrlq $1, %xmm0, %xmm0 424; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] 425; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 426; X64-NEXT: retq 427 %1 = lshr <2 x i64> %a0, <i64 1, i64 1> 428 %2 = bitcast <2 x i64> %1 to <4 x i32> 429 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3> 430 %4 = uitofp <4 x i32> %3 to <4 x float> 431 ret <4 x float> %4 432} 433 434define <4 x float> @knownbits_smax_smin_shuffle_uitofp(<4 x i32> %a0) { 435; X32-LABEL: knownbits_smax_smin_shuffle_uitofp: 436; X32: # %bb.0: 437; X32-NEXT: vpminsd {{\.LCPI.*}}, %xmm0, %xmm0 438; X32-NEXT: vpmaxsd {{\.LCPI.*}}, %xmm0, %xmm0 439; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] 440; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 441; X32-NEXT: vpsrld $16, %xmm0, %xmm0 442; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 443; X32-NEXT: vaddps {{\.LCPI.*}}, %xmm0, %xmm0 444; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0 445; X32-NEXT: retl 446; 447; X64-LABEL: knownbits_smax_smin_shuffle_uitofp: 448; X64: # %bb.0: 449; X64-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0 450; X64-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0 451; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] 452; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 453; X64-NEXT: vpsrld $16, %xmm0, %xmm0 454; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 455; X64-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0 456; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0 457; X64-NEXT: retq 458 %1 = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> <i32 0, i32 -65535, i32 -65535, i32 0>) 459 %2 = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %1, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 131071>) 460 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 461 %4 = uitofp <4 x i32> %3 to <4 x float> 462 ret <4 x float> %4 463} 464declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone 465declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone 466 467define <4 x float> @knownbits_umin_shuffle_uitofp(<4 x i32> %a0) { 468; X32-LABEL: knownbits_umin_shuffle_uitofp: 469; X32: # %bb.0: 470; X32-NEXT: vpminud {{\.LCPI.*}}, %xmm0, %xmm0 471; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] 472; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 473; X32-NEXT: retl 474; 475; X64-LABEL: knownbits_umin_shuffle_uitofp: 476; X64: # %bb.0: 477; X64-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0 478; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] 479; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 480; X64-NEXT: retq 481 %1 = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 262143>) 482 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 483 %3 = uitofp <4 x i32> %2 to <4 x float> 484 ret <4 x float> %3 485} 486declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone 487declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone 488 489define <4 x i32> @knownbits_umax_shuffle_ashr(<4 x i32> %a0) { 490; X32-LABEL: knownbits_umax_shuffle_ashr: 491; X32: # %bb.0: 492; X32-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 493; X32-NEXT: retl 494; 495; X64-LABEL: knownbits_umax_shuffle_ashr: 496; X64: # %bb.0: 497; X64-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 498; X64-NEXT: retq 499 %1 = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 262143>) 500 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 2> 501 %3 = ashr <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31> 502 ret <4 x i32> %3 503} 504 505define <4 x float> @knownbits_mask_umax_shuffle_uitofp(<4 x i32> %a0) { 506; X32-LABEL: knownbits_mask_umax_shuffle_uitofp: 507; X32: # %bb.0: 508; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 509; X32-NEXT: vpmaxud {{\.LCPI.*}}, %xmm0, %xmm0 510; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] 511; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 512; X32-NEXT: retl 513; 514; X64-LABEL: knownbits_mask_umax_shuffle_uitofp: 515; X64: # %bb.0: 516; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 517; X64-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0 518; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] 519; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 520; X64-NEXT: retq 521 %1 = and <4 x i32> %a0, <i32 65535, i32 -1, i32 -1, i32 262143> 522 %2 = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %1, <4 x i32> <i32 255, i32 -1, i32 -1, i32 1023>) 523 %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> 524 %4 = uitofp <4 x i32> %3 to <4 x float> 525 ret <4 x float> %4 526} 527 528define <4 x i32> @knownbits_mask_bitreverse_ashr(<4 x i32> %a0) { 529; X32-LABEL: knownbits_mask_bitreverse_ashr: 530; X32: # %bb.0: 531; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0 532; X32-NEXT: retl 533; 534; X64-LABEL: knownbits_mask_bitreverse_ashr: 535; X64: # %bb.0: 536; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0 537; X64-NEXT: retq 538 %1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 -2, i32 -2> 539 %2 = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %1) 540 %3 = ashr <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31> 541 ret <4 x i32> %3 542} 543declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) nounwind readnone 544 545; If we don't know that the input isn't INT_MIN we can't combine to sitofp 546define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) { 547; X32-LABEL: knownbits_abs_uitofp: 548; X32: # %bb.0: 549; X32-NEXT: vpabsd %xmm0, %xmm0 550; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 551; X32-NEXT: vpsrld $16, %xmm0, %xmm0 552; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 553; X32-NEXT: vaddps {{\.LCPI.*}}, %xmm0, %xmm0 554; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0 555; X32-NEXT: retl 556; 557; X64-LABEL: knownbits_abs_uitofp: 558; X64: # %bb.0: 559; X64-NEXT: vpabsd %xmm0, %xmm0 560; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 561; X64-NEXT: vpsrld $16, %xmm0, %xmm0 562; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] 563; X64-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0 564; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0 565; X64-NEXT: retq 566 %1 = sub <4 x i32> zeroinitializer, %a0 567 %2 = icmp slt <4 x i32> %a0, zeroinitializer 568 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> %a0 569 %4 = uitofp <4 x i32> %3 to <4 x float> 570 ret <4 x float> %4 571} 572 573define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) { 574; X32-LABEL: knownbits_or_abs_uitofp: 575; X32: # %bb.0: 576; X32-NEXT: vpor {{\.LCPI.*}}, %xmm0, %xmm0 577; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2] 578; X32-NEXT: vpabsd %xmm0, %xmm0 579; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 580; X32-NEXT: retl 581; 582; X64-LABEL: knownbits_or_abs_uitofp: 583; X64: # %bb.0: 584; X64-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 585; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2] 586; X64-NEXT: vpabsd %xmm0, %xmm0 587; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 588; X64-NEXT: retq 589 %1 = or <4 x i32> %a0, <i32 1, i32 0, i32 3, i32 0> 590 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 0, i32 2> 591 %3 = sub <4 x i32> zeroinitializer, %2 592 %4 = icmp slt <4 x i32> %2, zeroinitializer 593 %5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> %2 594 %6 = uitofp <4 x i32> %5 to <4 x float> 595 ret <4 x float> %6 596} 597 598define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind { 599; X32-LABEL: knownbits_and_select_shuffle_uitofp: 600; X32: # %bb.0: 601; X32-NEXT: pushl %ebp 602; X32-NEXT: movl %esp, %ebp 603; X32-NEXT: andl $-16, %esp 604; X32-NEXT: subl $16, %esp 605; X32-NEXT: vmovaps 8(%ebp), %xmm3 606; X32-NEXT: vandps {{\.LCPI.*}}, %xmm2, %xmm2 607; X32-NEXT: vandps {{\.LCPI.*}}, %xmm3, %xmm3 608; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 609; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 610; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2] 611; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 612; X32-NEXT: movl %ebp, %esp 613; X32-NEXT: popl %ebp 614; X32-NEXT: retl 615; 616; X64-LABEL: knownbits_and_select_shuffle_uitofp: 617; X64: # %bb.0: 618; X64-NEXT: vandps {{.*}}(%rip), %xmm2, %xmm2 619; X64-NEXT: vandps {{.*}}(%rip), %xmm3, %xmm3 620; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 621; X64-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 622; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2] 623; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 624; X64-NEXT: retq 625 %1 = and <4 x i32> %a2, <i32 65535, i32 -1, i32 255, i32 -1> 626 %2 = and <4 x i32> %a3, <i32 255, i32 -1, i32 65535, i32 -1> 627 %3 = icmp eq <4 x i32> %a0, %a1 628 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 629 %5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> 630 %6 = uitofp <4 x i32> %5 to <4 x float> 631 ret <4 x float> %6 632} 633 634define <4 x float> @knownbits_lshr_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind { 635; X32-LABEL: knownbits_lshr_and_select_shuffle_uitofp: 636; X32: # %bb.0: 637; X32-NEXT: pushl %ebp 638; X32-NEXT: movl %esp, %ebp 639; X32-NEXT: andl $-16, %esp 640; X32-NEXT: subl $16, %esp 641; X32-NEXT: vmovaps 8(%ebp), %xmm3 642; X32-NEXT: vpsrld $5, %xmm2, %xmm2 643; X32-NEXT: vandps {{\.LCPI.*}}, %xmm3, %xmm3 644; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 645; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 646; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2] 647; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 648; X32-NEXT: movl %ebp, %esp 649; X32-NEXT: popl %ebp 650; X32-NEXT: retl 651; 652; X64-LABEL: knownbits_lshr_and_select_shuffle_uitofp: 653; X64: # %bb.0: 654; X64-NEXT: vpsrld $5, %xmm2, %xmm2 655; X64-NEXT: vandps {{.*}}(%rip), %xmm3, %xmm3 656; X64-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 657; X64-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 658; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2] 659; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 660; X64-NEXT: retq 661 %1 = lshr <4 x i32> %a2, <i32 5, i32 1, i32 5, i32 1> 662 %2 = and <4 x i32> %a3, <i32 255, i32 -1, i32 65535, i32 -1> 663 %3 = icmp eq <4 x i32> %a0, %a1 664 %4 = select <4 x i1> %3, <4 x i32> %1, <4 x i32> %2 665 %5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> 666 %6 = uitofp <4 x i32> %5 to <4 x float> 667 ret <4 x float> %6 668} 669