1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
5
6define <4 x float> @shuffle_v4f32_0z27(<4 x float> %x, <4 x float> %a) {
7; SSE-LABEL: shuffle_v4f32_0z27:
8; SSE:       # BB#0:
9; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]
10; SSE-NEXT:    retq
11;
12; AVX-LABEL: shuffle_v4f32_0z27:
13; AVX:       # BB#0:
14; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]
15; AVX-NEXT:    retq
16  %vecext = extractelement <4 x float> %x, i32 0
17  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
18  %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
19  %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
20  %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
21  ret <4 x float> %vecinit5
22}
23
24define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %xyzw, <4 x float> %abcd) {
25; SSE-LABEL: shuffle_v4f32_0zz4:
26; SSE:       # BB#0:
27; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
28; SSE-NEXT:    retq
29;
30; AVX-LABEL: shuffle_v4f32_0zz4:
31; AVX:       # BB#0:
32; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
33; AVX-NEXT:    retq
34  %vecext = extractelement <4 x float> %xyzw, i32 0
35  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
36  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
37  %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
38  %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
39  ret <4 x float> %vecinit4
40}
41
42define <4 x float> @shuffle_v4f32_0z24(<4 x float> %xyzw, <4 x float> %abcd) {
43; SSE-LABEL: shuffle_v4f32_0z24:
44; SSE:       # BB#0:
45; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
46; SSE-NEXT:    retq
47;
48; AVX-LABEL: shuffle_v4f32_0z24:
49; AVX:       # BB#0:
50; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
51; AVX-NEXT:    retq
52  %vecext = extractelement <4 x float> %xyzw, i32 0
53  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
54  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
55  %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %xyzw, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
56  %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
57  ret <4 x float> %vecinit5
58}
59
60define <4 x float> @shuffle_v4f32_0zz0(float %a) {
61; SSE-LABEL: shuffle_v4f32_0zz0:
62; SSE:       # BB#0:
63; SSE-NEXT:    xorps %xmm1, %xmm1
64; SSE-NEXT:    blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
65; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1,1,0]
66; SSE-NEXT:    movaps %xmm1, %xmm0
67; SSE-NEXT:    retq
68;
69; AVX-LABEL: shuffle_v4f32_0zz0:
70; AVX:       # BB#0:
71; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
72; AVX-NEXT:    vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
73; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,0]
74; AVX-NEXT:    retq
75  %vecinit = insertelement <4 x float> undef, float %a, i32 0
76  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
77  %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
78  %vecinit3 = insertelement <4 x float> %vecinit2, float %a, i32 3
79  ret <4 x float> %vecinit3
80}
81
82define <4 x float> @shuffle_v4f32_0z6z(<4 x float> %A, <4 x float> %B) {
83; SSE-LABEL: shuffle_v4f32_0z6z:
84; SSE:       # BB#0:
85; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
86; SSE-NEXT:    retq
87;
88; AVX-LABEL: shuffle_v4f32_0z6z:
89; AVX:       # BB#0:
90; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
91; AVX-NEXT:    retq
92  %vecext = extractelement <4 x float> %A, i32 0
93  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
94  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
95  %vecext2 = extractelement <4 x float> %B, i32 2
96  %vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
97  %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
98  ret <4 x float> %vecinit4
99}
100
101define <4 x float> @insertps_undef_input0(<4 x float> %a0, <4 x float> %a1) {
102; SSE-LABEL: insertps_undef_input0:
103; SSE:       # BB#0:
104; SSE-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero
105; SSE-NEXT:    retq
106;
107; AVX-LABEL: insertps_undef_input0:
108; AVX:       # BB#0:
109; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero
110; AVX-NEXT:    retq
111  %res0 = fadd <4 x float> %a0, <float 1.0, float 1.0, float 1.0, float 1.0>
112  %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %res0, <4 x float> %a1, i8 21)
113  %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
114  ret <4 x float> %res2
115}
116
117define <4 x float> @insertps_undef_input1(<4 x float> %a0, <4 x float> %a1) {
118; SSE-LABEL: insertps_undef_input1:
119; SSE:       # BB#0:
120; SSE-NEXT:    xorps %xmm1, %xmm1
121; SSE-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
122; SSE-NEXT:    retq
123;
124; AVX-LABEL: insertps_undef_input1:
125; AVX:       # BB#0:
126; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
127; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
128; AVX-NEXT:    retq
129  %res0 = fadd <4 x float> %a1, <float 1.0, float 1.0, float 1.0, float 1.0>
130  %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %res0, i8 21)
131  %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
132  ret <4 x float> %res2
133}
134
135define <4 x float> @insertps_zero_from_v2f64(<4 x float> %a0, <2 x double>* %a1) nounwind {
136; SSE-LABEL: insertps_zero_from_v2f64:
137; SSE:       # BB#0:
138; SSE-NEXT:    movapd (%rdi), %xmm1
139; SSE-NEXT:    addpd {{.*}}(%rip), %xmm1
140; SSE-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
141; SSE-NEXT:    movapd %xmm1, (%rdi)
142; SSE-NEXT:    retq
143;
144; AVX-LABEL: insertps_zero_from_v2f64:
145; AVX:       # BB#0:
146; AVX-NEXT:    vmovapd (%rdi), %xmm1
147; AVX-NEXT:    vaddpd {{.*}}(%rip), %xmm1, %xmm1
148; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
149; AVX-NEXT:    vmovapd %xmm1, (%rdi)
150; AVX-NEXT:    retq
151  %1 = load <2 x double>, <2 x double>* %a1
152  %2 = bitcast <2 x double> <double 1.0, double 2.0> to <4 x float>
153  %3 = fadd <2 x double> %1, <double 1.0, double 2.0>
154  %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 6, i32 2, i32 2, i32 3>
155  store <2 x double> %3, <2 x double> *%a1
156  ret <4 x float> %4
157}
158
159define <4 x float> @insertps_zero_from_v2i64(<4 x float> %a0, <2 x i64>* %a1) nounwind {
160; SSE-LABEL: insertps_zero_from_v2i64:
161; SSE:       # BB#0:
162; SSE-NEXT:    movdqa (%rdi), %xmm1
163; SSE-NEXT:    paddq {{.*}}(%rip), %xmm1
164; SSE-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
165; SSE-NEXT:    movdqa %xmm1, (%rdi)
166; SSE-NEXT:    retq
167;
168; AVX-LABEL: insertps_zero_from_v2i64:
169; AVX:       # BB#0:
170; AVX-NEXT:    vmovdqa (%rdi), %xmm1
171; AVX-NEXT:    vpaddq {{.*}}(%rip), %xmm1, %xmm1
172; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
173; AVX-NEXT:    vmovdqa %xmm1, (%rdi)
174; AVX-NEXT:    retq
175  %1 = load <2 x i64>, <2 x i64>* %a1
176  %2 = bitcast <2 x i64> <i64 1, i64 -2> to <4 x float>
177  %3 = add <2 x i64> %1, <i64 1, i64 -2>
178  %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 5, i32 2, i32 2, i32 3>
179  store <2 x i64> %3, <2 x i64> *%a1
180  ret <4 x float> %4
181}
182
183define <4 x float> @insertps_zero_from_v8i16(<4 x float> %a0, <8 x i16>* %a1) nounwind {
184; SSE-LABEL: insertps_zero_from_v8i16:
185; SSE:       # BB#0:
186; SSE-NEXT:    movdqa (%rdi), %xmm1
187; SSE-NEXT:    paddw {{.*}}(%rip), %xmm1
188; SSE-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
189; SSE-NEXT:    movdqa %xmm1, (%rdi)
190; SSE-NEXT:    retq
191;
192; AVX-LABEL: insertps_zero_from_v8i16:
193; AVX:       # BB#0:
194; AVX-NEXT:    vmovdqa (%rdi), %xmm1
195; AVX-NEXT:    vpaddw {{.*}}(%rip), %xmm1, %xmm1
196; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
197; AVX-NEXT:    vmovdqa %xmm1, (%rdi)
198; AVX-NEXT:    retq
199  %1 = load <8 x i16>, <8 x i16>* %a1
200  %2 = bitcast <8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3> to <4 x float>
201  %3 = add <8 x i16> %1, <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3>
202  %4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 4, i32 2, i32 2, i32 3>
203  store <8 x i16> %3, <8 x i16> *%a1
204  ret <4 x float> %4
205}
206
207define <4 x float> @consecutive_load_insertps_04zz(float* %p) {
208; SSE-LABEL: consecutive_load_insertps_04zz:
209; SSE:       # BB#0:
210; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
211; SSE-NEXT:    retq
212;
213; AVX-LABEL: consecutive_load_insertps_04zz:
214; AVX:       # BB#0:
215; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
216; AVX-NEXT:    retq
217  %p0 = getelementptr inbounds float, float* %p, i64 1
218  %p1 = getelementptr inbounds float, float* %p, i64 2
219  %s0 = load float, float* %p0
220  %s1 = load float, float* %p1
221  %v0 = insertelement <4 x float> undef, float %s0, i32 0
222  %v1 = insertelement <4 x float> undef, float %s1, i32 0
223  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v0, <4 x float> %v1, i8 28)
224  ret <4 x float> %res
225}
226
227define float @extract_zero_insertps_z0z7(<4 x float> %a0, <4 x float> %a1) {
228; SSE-LABEL: extract_zero_insertps_z0z7:
229; SSE:       # BB#0:
230; SSE-NEXT:    xorps %xmm0, %xmm0
231; SSE-NEXT:    retq
232;
233; AVX-LABEL: extract_zero_insertps_z0z7:
234; AVX:       # BB#0:
235; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
236; AVX-NEXT:    retq
237  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 21)
238  %ext = extractelement <4 x float> %res, i32 0
239  ret float %ext
240}
241
242define float @extract_lane_insertps_5123(<4 x float> %a0, <4 x float> *%p1) {
243; SSE-LABEL: extract_lane_insertps_5123:
244; SSE:       # BB#0:
245; SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
246; SSE-NEXT:    retq
247;
248; AVX-LABEL: extract_lane_insertps_5123:
249; AVX:       # BB#0:
250; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
251; AVX-NEXT:    retq
252  %a1 = load <4 x float>, <4 x float> *%p1
253  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 128)
254  %ext = extractelement <4 x float> %res, i32 0
255  ret float %ext
256}
257
258declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
259