1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
5
6define <4 x float> @shuffle_v4f32_0z27(<4 x float> %x, <4 x float> %a) {
7; SSE-LABEL: shuffle_v4f32_0z27:
8; SSE:       # BB#0:
9; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]
10; SSE-NEXT:    retq
11;
12; AVX-LABEL: shuffle_v4f32_0z27:
13; AVX:       # BB#0:
14; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]
15; AVX-NEXT:    retq
16  %vecext = extractelement <4 x float> %x, i32 0
17  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
18  %vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
19  %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
20  %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
21  ret <4 x float> %vecinit5
22}
23
24define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %xyzw, <4 x float> %abcd) {
25; SSE-LABEL: shuffle_v4f32_0zz4:
26; SSE:       # BB#0:
27; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
28; SSE-NEXT:    retq
29;
30; AVX-LABEL: shuffle_v4f32_0zz4:
31; AVX:       # BB#0:
32; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
33; AVX-NEXT:    retq
34  %vecext = extractelement <4 x float> %xyzw, i32 0
35  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
36  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
37  %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
38  %vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
39  ret <4 x float> %vecinit4
40}
41
42define <4 x float> @shuffle_v4f32_0z24(<4 x float> %xyzw, <4 x float> %abcd) {
43; SSE-LABEL: shuffle_v4f32_0z24:
44; SSE:       # BB#0:
45; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
46; SSE-NEXT:    retq
47;
48; AVX-LABEL: shuffle_v4f32_0z24:
49; AVX:       # BB#0:
50; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
51; AVX-NEXT:    retq
52  %vecext = extractelement <4 x float> %xyzw, i32 0
53  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
54  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
55  %vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %xyzw, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
56  %vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
57  ret <4 x float> %vecinit5
58}
59
60define <4 x float> @shuffle_v4f32_0zz0(float %a) {
61; SSE-LABEL: shuffle_v4f32_0zz0:
62; SSE:       # BB#0:
63; SSE-NEXT:    xorps %xmm1, %xmm1
64; SSE-NEXT:    blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
65; SSE-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1,1,0]
66; SSE-NEXT:    movaps %xmm1, %xmm0
67; SSE-NEXT:    retq
68;
69; AVX-LABEL: shuffle_v4f32_0zz0:
70; AVX:       # BB#0:
71; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
72; AVX-NEXT:    vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
73; AVX-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,0]
74; AVX-NEXT:    retq
75  %vecinit = insertelement <4 x float> undef, float %a, i32 0
76  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
77  %vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
78  %vecinit3 = insertelement <4 x float> %vecinit2, float %a, i32 3
79  ret <4 x float> %vecinit3
80}
81
82define <4 x float> @shuffle_v4f32_0z6z(<4 x float> %A, <4 x float> %B) {
83; SSE-LABEL: shuffle_v4f32_0z6z:
84; SSE:       # BB#0:
85; SSE-NEXT:    insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
86; SSE-NEXT:    retq
87;
88; AVX-LABEL: shuffle_v4f32_0z6z:
89; AVX:       # BB#0:
90; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
91; AVX-NEXT:    retq
92  %vecext = extractelement <4 x float> %A, i32 0
93  %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
94  %vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
95  %vecext2 = extractelement <4 x float> %B, i32 2
96  %vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
97  %vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
98  ret <4 x float> %vecinit4
99}
100
101define <4 x float> @insertps_undef_input0(<4 x float> %a0, <4 x float> %a1) {
102; SSE-LABEL: insertps_undef_input0:
103; SSE:       # BB#0:
104; SSE-NEXT:    insertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero
105; SSE-NEXT:    retq
106;
107; AVX-LABEL: insertps_undef_input0:
108; AVX:       # BB#0:
109; AVX-NEXT:    vinsertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero
110; AVX-NEXT:    retq
111  %res0 = fadd <4 x float> %a0, <float 1.0, float 1.0, float 1.0, float 1.0>
112  %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %res0, <4 x float> %a1, i8 21)
113  %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
114  ret <4 x float> %res2
115}
116
117define <4 x float> @insertps_undef_input1(<4 x float> %a0, <4 x float> %a1) {
118; SSE-LABEL: insertps_undef_input1:
119; SSE:       # BB#0:
120; SSE-NEXT:    xorps %xmm1, %xmm1
121; SSE-NEXT:    blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
122; SSE-NEXT:    retq
123;
124; AVX-LABEL: insertps_undef_input1:
125; AVX:       # BB#0:
126; AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
127; AVX-NEXT:    vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
128; AVX-NEXT:    retq
129  %res0 = fadd <4 x float> %a1, <float 1.0, float 1.0, float 1.0, float 1.0>
130  %res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %res0, i8 21)
131  %res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
132  ret <4 x float> %res2
133}
134
135define <4 x float> @consecutive_load_insertps_04zz(float* %p) {
136; SSE-LABEL: consecutive_load_insertps_04zz:
137; SSE:       # BB#0:
138; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
139; SSE-NEXT:    retq
140;
141; AVX-LABEL: consecutive_load_insertps_04zz:
142; AVX:       # BB#0:
143; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
144; AVX-NEXT:    retq
145  %p0 = getelementptr inbounds float, float* %p, i64 1
146  %p1 = getelementptr inbounds float, float* %p, i64 2
147  %s0 = load float, float* %p0
148  %s1 = load float, float* %p1
149  %v0 = insertelement <4 x float> undef, float %s0, i32 0
150  %v1 = insertelement <4 x float> undef, float %s1, i32 0
151  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v0, <4 x float> %v1, i8 28)
152  ret <4 x float> %res
153}
154
155define float @extract_zero_insertps_z0z7(<4 x float> %a0, <4 x float> %a1) {
156; SSE-LABEL: extract_zero_insertps_z0z7:
157; SSE:       # BB#0:
158; SSE-NEXT:    xorps %xmm0, %xmm0
159; SSE-NEXT:    retq
160;
161; AVX-LABEL: extract_zero_insertps_z0z7:
162; AVX:       # BB#0:
163; AVX-NEXT:    vxorps %xmm0, %xmm0, %xmm0
164; AVX-NEXT:    retq
165  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 21)
166  %ext = extractelement <4 x float> %res, i32 0
167  ret float %ext
168}
169
170define float @extract_lane_insertps_5123(<4 x float> %a0, <4 x float> *%p1) {
171; SSE-LABEL: extract_lane_insertps_5123:
172; SSE:       # BB#0:
173; SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
174; SSE-NEXT:    retq
175;
176; AVX-LABEL: extract_lane_insertps_5123:
177; AVX:       # BB#0:
178; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
179; AVX-NEXT:    retq
180  %a1 = load <4 x float>, <4 x float> *%p1
181  %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 128)
182  %ext = extractelement <4 x float> %res, i32 0
183  ret float %ext
184}
185
186declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
187