1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32SSE --check-prefix=X32SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64SSE --check-prefix=X64SSE2 4; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32SSE --check-prefix=X32SSE4 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64SSE --check-prefix=X64SSE4 6; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32AVX --check-prefix=X32AVX2 7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64AVX --check-prefix=X64AVX2 8; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32AVX --check-prefix=X32AVX512F 9; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64AVX --check-prefix=X64AVX512F 10 11define <16 x i8> @elt0_v16i8(i8 %x) { 12; X32SSE2-LABEL: elt0_v16i8: 13; X32SSE2: # BB#0: 14; X32SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero 15; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] 16; X32SSE2-NEXT: andnps %xmm1, %xmm0 17; X32SSE2-NEXT: orps {{\.LCPI.*}}, %xmm0 18; X32SSE2-NEXT: retl 19; 20; X64SSE2-LABEL: elt0_v16i8: 21; X64SSE2: # BB#0: 22; X64SSE2-NEXT: movd %edi, %xmm1 23; X64SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] 24; X64SSE2-NEXT: pandn %xmm1, %xmm0 25; X64SSE2-NEXT: por {{.*}}(%rip), %xmm0 26; X64SSE2-NEXT: retq 27; 28; X32SSE4-LABEL: elt0_v16i8: 29; X32SSE4: # BB#0: 30; X32SSE4-NEXT: movdqa {{.*#+}} xmm0 = <u,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15> 31; X32SSE4-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0 32; X32SSE4-NEXT: retl 33; 34; X64SSE4-LABEL: elt0_v16i8: 35; X64SSE4: # BB#0: 36; X64SSE4-NEXT: movdqa {{.*#+}} xmm0 = <u,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15> 37; X64SSE4-NEXT: pinsrb $0, %edi, %xmm0 38; X64SSE4-NEXT: retq 39; 40; X32AVX-LABEL: elt0_v16i8: 41; X32AVX: # BB#0: 42; X32AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <u,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15> 43; X32AVX-NEXT: vpinsrb $0, {{[0-9]+}}(%esp), %xmm0, %xmm0 44; X32AVX-NEXT: retl 45; 46; X64AVX-LABEL: elt0_v16i8: 47; X64AVX: # BB#0: 48; X64AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <u,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15> 49; X64AVX-NEXT: vpinsrb $0, %edi, %xmm0, %xmm0 50; X64AVX-NEXT: retq 51 %ins = insertelement <16 x i8> <i8 42, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, i8 %x, i32 0 52 ret <16 x i8> %ins 53} 54 55define <8 x i16> @elt5_v8i16(i16 %x) { 56; X32SSE-LABEL: elt5_v8i16: 57; X32SSE: # BB#0: 58; X32SSE-NEXT: movdqa {{.*#+}} xmm0 = <42,1,2,3,4,u,6,7> 59; X32SSE-NEXT: pinsrw $5, {{[0-9]+}}(%esp), %xmm0 60; X32SSE-NEXT: retl 61; 62; X64SSE-LABEL: elt5_v8i16: 63; X64SSE: # BB#0: 64; X64SSE-NEXT: movdqa {{.*#+}} xmm0 = <42,1,2,3,4,u,6,7> 65; X64SSE-NEXT: pinsrw $5, %edi, %xmm0 66; X64SSE-NEXT: retq 67; 68; X32AVX-LABEL: elt5_v8i16: 69; X32AVX: # BB#0: 70; X32AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <42,1,2,3,4,u,6,7> 71; X32AVX-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0 72; X32AVX-NEXT: retl 73; 74; X64AVX-LABEL: elt5_v8i16: 75; X64AVX: # BB#0: 76; X64AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <42,1,2,3,4,u,6,7> 77; X64AVX-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0 78; X64AVX-NEXT: retq 79 %ins = insertelement <8 x i16> <i16 42, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 %x, i32 5 80 ret <8 x i16> %ins 81} 82 83define <4 x i32> @elt3_v4i32(i32 %x) { 84; X32SSE2-LABEL: elt3_v4i32: 85; X32SSE2: # BB#0: 86; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = <42,1,2,u> 87; X32SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero 88; X32SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] 89; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] 90; X32SSE2-NEXT: retl 91; 92; X64SSE2-LABEL: elt3_v4i32: 93; X64SSE2: # BB#0: 94; X64SSE2-NEXT: movd %edi, %xmm1 95; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = <42,1,2,u> 96; X64SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] 97; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] 98; X64SSE2-NEXT: retq 99; 100; X32SSE4-LABEL: elt3_v4i32: 101; X32SSE4: # BB#0: 102; X32SSE4-NEXT: movdqa {{.*#+}} xmm0 = <42,1,2,u> 103; X32SSE4-NEXT: pinsrd $3, {{[0-9]+}}(%esp), %xmm0 104; X32SSE4-NEXT: retl 105; 106; X64SSE4-LABEL: elt3_v4i32: 107; X64SSE4: # BB#0: 108; X64SSE4-NEXT: movdqa {{.*#+}} xmm0 = <42,1,2,u> 109; X64SSE4-NEXT: pinsrd $3, %edi, %xmm0 110; X64SSE4-NEXT: retq 111; 112; X32AVX-LABEL: elt3_v4i32: 113; X32AVX: # BB#0: 114; X32AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <42,1,2,u> 115; X32AVX-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0 116; X32AVX-NEXT: retl 117; 118; X64AVX-LABEL: elt3_v4i32: 119; X64AVX: # BB#0: 120; X64AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <42,1,2,u> 121; X64AVX-NEXT: vpinsrd $3, %edi, %xmm0, %xmm0 122; X64AVX-NEXT: retq 123 %ins = insertelement <4 x i32> <i32 42, i32 1, i32 2, i32 3>, i32 %x, i32 3 124 ret <4 x i32> %ins 125} 126 127define <2 x i64> @elt0_v2i64(i64 %x) { 128; X32SSE-LABEL: elt0_v2i64: 129; X32SSE: # BB#0: 130; X32SSE-NEXT: movl $1, %eax 131; X32SSE-NEXT: movd %eax, %xmm1 132; X32SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 133; X32SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 134; X32SSE-NEXT: retl 135; 136; X64SSE2-LABEL: elt0_v2i64: 137; X64SSE2: # BB#0: 138; X64SSE2-NEXT: movq %rdi, %xmm1 139; X64SSE2-NEXT: movapd {{.*#+}} xmm0 = <u,1> 140; X64SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] 141; X64SSE2-NEXT: retq 142; 143; X64SSE4-LABEL: elt0_v2i64: 144; X64SSE4: # BB#0: 145; X64SSE4-NEXT: movdqa {{.*#+}} xmm0 = <u,1> 146; X64SSE4-NEXT: pinsrq $0, %rdi, %xmm0 147; X64SSE4-NEXT: retq 148; 149; X32AVX-LABEL: elt0_v2i64: 150; X32AVX: # BB#0: 151; X32AVX-NEXT: movl $1, %eax 152; X32AVX-NEXT: vmovd %eax, %xmm0 153; X32AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero 154; X32AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] 155; X32AVX-NEXT: retl 156; 157; X64AVX-LABEL: elt0_v2i64: 158; X64AVX: # BB#0: 159; X64AVX-NEXT: vmovdqa {{.*#+}} xmm0 = <u,1> 160; X64AVX-NEXT: vpinsrq $0, %rdi, %xmm0, %xmm0 161; X64AVX-NEXT: retq 162 %ins = insertelement <2 x i64> <i64 42, i64 1>, i64 %x, i32 0 163 ret <2 x i64> %ins 164} 165 166define <4 x float> @elt1_v4f32(float %x) { 167; X32SSE2-LABEL: elt1_v4f32: 168; X32SSE2: # BB#0: 169; X32SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 170; X32SSE2-NEXT: movaps {{.*#+}} xmm1 = <42,u,2,3> 171; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] 172; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] 173; X32SSE2-NEXT: retl 174; 175; X64SSE2-LABEL: elt1_v4f32: 176; X64SSE2: # BB#0: 177; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = <42,u,2,3> 178; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] 179; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] 180; X64SSE2-NEXT: retq 181; 182; X32SSE4-LABEL: elt1_v4f32: 183; X32SSE4: # BB#0: 184; X32SSE4-NEXT: movaps {{.*#+}} xmm0 = <42,u,2,3> 185; X32SSE4-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] 186; X32SSE4-NEXT: retl 187; 188; X64SSE4-LABEL: elt1_v4f32: 189; X64SSE4: # BB#0: 190; X64SSE4-NEXT: movaps {{.*#+}} xmm1 = <42,u,2,3> 191; X64SSE4-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[2,3] 192; X64SSE4-NEXT: movaps %xmm1, %xmm0 193; X64SSE4-NEXT: retq 194; 195; X32AVX-LABEL: elt1_v4f32: 196; X32AVX: # BB#0: 197; X32AVX-NEXT: vmovaps {{.*#+}} xmm0 = <42,u,2,3> 198; X32AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] 199; X32AVX-NEXT: retl 200; 201; X64AVX-LABEL: elt1_v4f32: 202; X64AVX: # BB#0: 203; X64AVX-NEXT: vmovaps {{.*#+}} xmm1 = <42,u,2,3> 204; X64AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] 205; X64AVX-NEXT: retq 206 %ins = insertelement <4 x float> <float 42.0, float 1.0, float 2.0, float 3.0>, float %x, i32 1 207 ret <4 x float> %ins 208} 209 210define <2 x double> @elt1_v2f64(double %x) { 211; X32SSE-LABEL: elt1_v2f64: 212; X32SSE: # BB#0: 213; X32SSE-NEXT: movapd {{.*#+}} xmm0 = <42,u> 214; X32SSE-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0] 215; X32SSE-NEXT: retl 216; 217; X64SSE-LABEL: elt1_v2f64: 218; X64SSE: # BB#0: 219; X64SSE-NEXT: movaps {{.*#+}} xmm1 = <42,u> 220; X64SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] 221; X64SSE-NEXT: movaps %xmm1, %xmm0 222; X64SSE-NEXT: retq 223; 224; X32AVX-LABEL: elt1_v2f64: 225; X32AVX: # BB#0: 226; X32AVX-NEXT: vmovapd {{.*#+}} xmm0 = <42,u> 227; X32AVX-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0] 228; X32AVX-NEXT: retl 229; 230; X64AVX-LABEL: elt1_v2f64: 231; X64AVX: # BB#0: 232; X64AVX-NEXT: vmovaps {{.*#+}} xmm1 = <42,u> 233; X64AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] 234; X64AVX-NEXT: retq 235 %ins = insertelement <2 x double> <double 42.0, double 1.0>, double %x, i32 1 236 ret <2 x double> %ins 237} 238 239define <8 x i32> @elt7_v8i32(i32 %x) { 240; X32SSE2-LABEL: elt7_v8i32: 241; X32SSE2: # BB#0: 242; X32SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,6,u> 243; X32SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 244; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] 245; X32SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] 246; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3] 247; X32SSE2-NEXT: retl 248; 249; X64SSE2-LABEL: elt7_v8i32: 250; X64SSE2: # BB#0: 251; X64SSE2-NEXT: movd %edi, %xmm0 252; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,6,u> 253; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] 254; X64SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] 255; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3] 256; X64SSE2-NEXT: retq 257; 258; X32SSE4-LABEL: elt7_v8i32: 259; X32SSE4: # BB#0: 260; X32SSE4-NEXT: movdqa {{.*#+}} xmm1 = <4,5,6,u> 261; X32SSE4-NEXT: pinsrd $3, {{[0-9]+}}(%esp), %xmm1 262; X32SSE4-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3] 263; X32SSE4-NEXT: retl 264; 265; X64SSE4-LABEL: elt7_v8i32: 266; X64SSE4: # BB#0: 267; X64SSE4-NEXT: movdqa {{.*#+}} xmm1 = <4,5,6,u> 268; X64SSE4-NEXT: pinsrd $3, %edi, %xmm1 269; X64SSE4-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3] 270; X64SSE4-NEXT: retq 271; 272; X32AVX-LABEL: elt7_v8i32: 273; X32AVX: # BB#0: 274; X32AVX-NEXT: vmovdqa {{.*#+}} ymm0 = <42,1,2,3,4,5,6,u> 275; X32AVX-NEXT: vextracti128 $1, %ymm0, %xmm1 276; X32AVX-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1 277; X32AVX-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 278; X32AVX-NEXT: retl 279; 280; X64AVX-LABEL: elt7_v8i32: 281; X64AVX: # BB#0: 282; X64AVX-NEXT: vmovdqa {{.*#+}} ymm0 = <42,1,2,3,4,5,6,u> 283; X64AVX-NEXT: vextracti128 $1, %ymm0, %xmm1 284; X64AVX-NEXT: vpinsrd $3, %edi, %xmm1, %xmm1 285; X64AVX-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 286; X64AVX-NEXT: retq 287 %ins = insertelement <8 x i32> <i32 42, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, i32 %x, i32 7 288 ret <8 x i32> %ins 289} 290 291define <8 x float> @elt6_v8f32(float %x) { 292; X32SSE2-LABEL: elt6_v8f32: 293; X32SSE2: # BB#0: 294; X32SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 295; X32SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,u,7> 296; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] 297; X32SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] 298; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = [4.200000e+01,1.000000e+00,2.000000e+00,3.000000e+00] 299; X32SSE2-NEXT: retl 300; 301; X64SSE2-LABEL: elt6_v8f32: 302; X64SSE2: # BB#0: 303; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,u,7> 304; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] 305; X64SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] 306; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = [4.200000e+01,1.000000e+00,2.000000e+00,3.000000e+00] 307; X64SSE2-NEXT: retq 308; 309; X32SSE4-LABEL: elt6_v8f32: 310; X32SSE4: # BB#0: 311; X32SSE4-NEXT: movaps {{.*#+}} xmm1 = <4,5,u,7> 312; X32SSE4-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] 313; X32SSE4-NEXT: movaps {{.*#+}} xmm0 = [4.200000e+01,1.000000e+00,2.000000e+00,3.000000e+00] 314; X32SSE4-NEXT: retl 315; 316; X64SSE4-LABEL: elt6_v8f32: 317; X64SSE4: # BB#0: 318; X64SSE4-NEXT: movaps {{.*#+}} xmm1 = <4,5,u,7> 319; X64SSE4-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0],xmm1[3] 320; X64SSE4-NEXT: movaps {{.*#+}} xmm0 = [4.200000e+01,1.000000e+00,2.000000e+00,3.000000e+00] 321; X64SSE4-NEXT: retq 322; 323; X32AVX-LABEL: elt6_v8f32: 324; X32AVX: # BB#0: 325; X32AVX-NEXT: vmovaps {{.*#+}} ymm0 = <42,1,2,3,4,5,u,7> 326; X32AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 327; X32AVX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] 328; X32AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 329; X32AVX-NEXT: retl 330; 331; X64AVX-LABEL: elt6_v8f32: 332; X64AVX: # BB#0: 333; X64AVX-NEXT: vmovaps {{.*#+}} ymm1 = <42,1,2,3,4,5,u,7> 334; X64AVX-NEXT: vextractf128 $1, %ymm1, %xmm2 335; X64AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3] 336; X64AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 337; X64AVX-NEXT: retq 338 %ins = insertelement <8 x float> <float 42.0, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0>, float %x, i32 6 339 ret <8 x float> %ins 340} 341 342define <8 x i64> @elt5_v8i64(i64 %x) { 343; X32SSE-LABEL: elt5_v8i64: 344; X32SSE: # BB#0: 345; X32SSE-NEXT: movl $4, %eax 346; X32SSE-NEXT: movd %eax, %xmm2 347; X32SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 348; X32SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] 349; X32SSE-NEXT: movaps {{.*#+}} xmm0 = [42,0,1,0] 350; X32SSE-NEXT: movaps {{.*#+}} xmm1 = [2,0,3,0] 351; X32SSE-NEXT: movaps {{.*#+}} xmm3 = [6,0,7,0] 352; X32SSE-NEXT: retl 353; 354; X64SSE2-LABEL: elt5_v8i64: 355; X64SSE2: # BB#0: 356; X64SSE2-NEXT: movq %rdi, %xmm0 357; X64SSE2-NEXT: movdqa {{.*#+}} xmm2 = <4,u> 358; X64SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] 359; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,1] 360; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = [2,3] 361; X64SSE2-NEXT: movaps {{.*#+}} xmm3 = [6,7] 362; X64SSE2-NEXT: retq 363; 364; X64SSE4-LABEL: elt5_v8i64: 365; X64SSE4: # BB#0: 366; X64SSE4-NEXT: movdqa {{.*#+}} xmm2 = <4,u> 367; X64SSE4-NEXT: pinsrq $1, %rdi, %xmm2 368; X64SSE4-NEXT: movaps {{.*#+}} xmm0 = [42,1] 369; X64SSE4-NEXT: movaps {{.*#+}} xmm1 = [2,3] 370; X64SSE4-NEXT: movaps {{.*#+}} xmm3 = [6,7] 371; X64SSE4-NEXT: retq 372; 373; X32AVX2-LABEL: elt5_v8i64: 374; X32AVX2: # BB#0: 375; X32AVX2-NEXT: movl $4, %eax 376; X32AVX2-NEXT: vmovd %eax, %xmm0 377; X32AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero 378; X32AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 379; X32AVX2-NEXT: vinserti128 $1, {{\.LCPI.*}}, %ymm0, %ymm1 380; X32AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] 381; X32AVX2-NEXT: retl 382; 383; X64AVX2-LABEL: elt5_v8i64: 384; X64AVX2: # BB#0: 385; X64AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = <4,u,6,7> 386; X64AVX2-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm1 387; X64AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] 388; X64AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,1,2,3] 389; X64AVX2-NEXT: retq 390; 391; X32AVX512F-LABEL: elt5_v8i64: 392; X32AVX512F: # BB#0: 393; X32AVX512F-NEXT: vmovdqa {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] 394; X32AVX512F-NEXT: movl $4, %eax 395; X32AVX512F-NEXT: vmovd %eax, %xmm1 396; X32AVX512F-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero 397; X32AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] 398; X32AVX512F-NEXT: vinserti128 $1, {{\.LCPI.*}}, %ymm1, %ymm1 399; X32AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 400; X32AVX512F-NEXT: retl 401; 402; X64AVX512F-LABEL: elt5_v8i64: 403; X64AVX512F: # BB#0: 404; X64AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = <42,1,2,3,4,u,6,7> 405; X64AVX512F-NEXT: vextracti32x4 $2, %zmm0, %xmm1 406; X64AVX512F-NEXT: vpinsrq $1, %rdi, %xmm1, %xmm1 407; X64AVX512F-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm0 408; X64AVX512F-NEXT: retq 409 %ins = insertelement <8 x i64> <i64 42, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, i64 %x, i32 5 410 ret <8 x i64> %ins 411} 412 413define <8 x double> @elt1_v8f64(double %x) { 414; X32SSE-LABEL: elt1_v8f64: 415; X32SSE: # BB#0: 416; X32SSE-NEXT: movapd {{.*#+}} xmm0 = <42,u> 417; X32SSE-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0] 418; X32SSE-NEXT: movaps {{.*#+}} xmm1 = [2.000000e+00,3.000000e+00] 419; X32SSE-NEXT: movaps {{.*#+}} xmm2 = [4.000000e+00,5.000000e+00] 420; X32SSE-NEXT: movaps {{.*#+}} xmm3 = [6.000000e+00,7.000000e+00] 421; X32SSE-NEXT: retl 422; 423; X64SSE-LABEL: elt1_v8f64: 424; X64SSE: # BB#0: 425; X64SSE-NEXT: movaps {{.*#+}} xmm4 = <42,u> 426; X64SSE-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm0[0] 427; X64SSE-NEXT: movaps {{.*#+}} xmm1 = [2.000000e+00,3.000000e+00] 428; X64SSE-NEXT: movaps {{.*#+}} xmm2 = [4.000000e+00,5.000000e+00] 429; X64SSE-NEXT: movaps {{.*#+}} xmm3 = [6.000000e+00,7.000000e+00] 430; X64SSE-NEXT: movaps %xmm4, %xmm0 431; X64SSE-NEXT: retq 432; 433; X32AVX2-LABEL: elt1_v8f64: 434; X32AVX2: # BB#0: 435; X32AVX2-NEXT: vmovapd {{.*#+}} ymm0 = <42,u,2,3> 436; X32AVX2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm0[0],mem[0] 437; X32AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] 438; X32AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [4.000000e+00,5.000000e+00,6.000000e+00,7.000000e+00] 439; X32AVX2-NEXT: retl 440; 441; X64AVX2-LABEL: elt1_v8f64: 442; X64AVX2: # BB#0: 443; X64AVX2-NEXT: vmovapd {{.*#+}} ymm1 = <42,u,2,3> 444; X64AVX2-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0] 445; X64AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] 446; X64AVX2-NEXT: vmovaps {{.*#+}} ymm1 = [4.000000e+00,5.000000e+00,6.000000e+00,7.000000e+00] 447; X64AVX2-NEXT: retq 448; 449; X32AVX512F-LABEL: elt1_v8f64: 450; X32AVX512F: # BB#0: 451; X32AVX512F-NEXT: vmovapd {{.*#+}} zmm0 = <42,u,2,3,4,5,6,7> 452; X32AVX512F-NEXT: vmovhpd {{.*#+}} xmm1 = xmm0[0],mem[0] 453; X32AVX512F-NEXT: vinsertf32x4 $0, %xmm1, %zmm0, %zmm0 454; X32AVX512F-NEXT: retl 455; 456; X64AVX512F-LABEL: elt1_v8f64: 457; X64AVX512F: # BB#0: 458; X64AVX512F-NEXT: vmovaps {{.*#+}} zmm1 = <42,u,2,3,4,5,6,7> 459; X64AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] 460; X64AVX512F-NEXT: vinsertf32x4 $0, %xmm0, %zmm1, %zmm0 461; X64AVX512F-NEXT: retq 462 %ins = insertelement <8 x double> <double 42.0, double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0>, double %x, i32 1 463 ret <8 x double> %ins 464} 465 466