1; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false -fixup-byte-word-insts=1 \
2; RUN:   | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL -check-prefix=BWON
3; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false -fixup-byte-word-insts=0 \
4; RUN:   | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL -check-prefix=BWOFF
5; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false -fixup-byte-word-insts=1 \
6; RUN:    | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C -check-prefix=BWON
7; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr +sse2 -asm-verbose=false -fixup-byte-word-insts=0  \
8; RUN:    | FileCheck %s -check-prefix=CHECK-I686
9
10define void @test_load_store(half* %in, half* %out) {
11; CHECK-LABEL: test_load_store:
12; BWON:  movzwl (%rdi), %eax
13; BWOFF: movw (%rdi), %ax
14; CHECK: movw %ax, (%rsi)
15  %val = load half, half* %in
16  store half %val, half* %out
17  ret void
18}
19
20define i16 @test_bitcast_from_half(half* %addr) {
21; CHECK-LABEL: test_bitcast_from_half:
22; CHECK: movzwl (%rdi), %eax
23  %val = load half, half* %addr
24  %val_int = bitcast half %val to i16
25  ret i16 %val_int
26}
27
28define void @test_bitcast_to_half(half* %addr, i16 %in) {
29; CHECK-LABEL: test_bitcast_to_half:
30; CHECK: movw %si, (%rdi)
31  %val_fp = bitcast i16 %in to half
32  store half %val_fp, half* %addr
33  ret void
34}
35
36define float @test_extend32(half* %addr) {
37; CHECK-LABEL: test_extend32:
38
39; CHECK-LIBCALL: jmp __gnu_h2f_ieee
40; CHECK-F16C: vcvtph2ps
41  %val16 = load half, half* %addr
42  %val32 = fpext half %val16 to float
43  ret float %val32
44}
45
46define double @test_extend64(half* %addr) {
47; CHECK-LABEL: test_extend64:
48
49; CHECK-LIBCALL: callq __gnu_h2f_ieee
50; CHECK-LIBCALL: cvtss2sd
51; CHECK-F16C: vcvtph2ps
52; CHECK-F16C: vcvtss2sd
53  %val16 = load half, half* %addr
54  %val32 = fpext half %val16 to double
55  ret double %val32
56}
57
58define void @test_trunc32(float %in, half* %addr) {
59; CHECK-LABEL: test_trunc32:
60
61; CHECK-LIBCALL: callq __gnu_f2h_ieee
62; CHECK-F16C: vcvtps2ph
63  %val16 = fptrunc float %in to half
64  store half %val16, half* %addr
65  ret void
66}
67
68define void @test_trunc64(double %in, half* %addr) {
69; CHECK-LABEL: test_trunc64:
70
71; CHECK-LIBCALL: callq __truncdfhf2
72; CHECK-F16C: callq __truncdfhf2
73  %val16 = fptrunc double %in to half
74  store half %val16, half* %addr
75  ret void
76}
77
78define i64 @test_fptosi_i64(half* %p) #0 {
79; CHECK-LABEL: test_fptosi_i64:
80
81; CHECK-LIBCALL-NEXT: pushq %rax
82; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
83; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
84; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, %rax
85; CHECK-LIBCALL-NEXT: popq %rcx
86; CHECK-LIBCALL-NEXT: retq
87
88; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
89; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
90; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
91; CHECK-F16C-NEXT: vcvttss2si [[REG2]], %rax
92; CHECK-F16C-NEXT: retq
93  %a = load half, half* %p, align 2
94  %r = fptosi half %a to i64
95  ret i64 %r
96}
97
98define void @test_sitofp_i64(i64 %a, half* %p) #0 {
99; CHECK-LABEL: test_sitofp_i64:
100
101; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z]+]]
102; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
103; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, %xmm0
104; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
105; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
106; CHECK_LIBCALL-NEXT: popq [[ADDR]]
107; CHECK_LIBCALL-NEXT: retq
108
109; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG0:%[a-z0-9]+]], [[REG0]]
110; CHECK-F16C-NEXT: vcvtps2ph $4, [[REG0]], [[REG0]]
111; CHECK-F16C-NEXT: vmovd [[REG0]], %eax
112; CHECK-F16C-NEXT: movw %ax, (%rsi)
113; CHECK-F16C-NEXT: retq
114  %r = sitofp i64 %a to half
115  store half %r, half* %p
116  ret void
117}
118
119define i64 @test_fptoui_i64(half* %p) #0 {
120; CHECK-LABEL: test_fptoui_i64:
121
122; FP_TO_UINT is expanded using FP_TO_SINT
123; CHECK-LIBCALL-NEXT: pushq %rax
124; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
125; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
126; CHECK-LIBCALL-NEXT: movss {{.[A-Z_0-9]+}}(%rip), [[REG1:%[a-z0-9]+]]
127; CHECK-LIBCALL-NEXT: movaps %xmm0, [[REG2:%[a-z0-9]+]]
128; CHECK-LIBCALL-NEXT: subss [[REG1]], [[REG2]]
129; CHECK-LIBCALL-NEXT: cvttss2si [[REG2]], [[REG3:%[a-z0-9]+]]
130; CHECK-LIBCALL-NEXT: movabsq  $-9223372036854775808, [[REG4:%[a-z0-9]+]]
131; CHECK-LIBCALL-NEXT: xorq [[REG3]], [[REG4]]
132; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, [[REG5:%[a-z0-9]+]]
133; CHECK-LIBCALL-NEXT: ucomiss [[REG1]], %xmm0
134; CHECK-LIBCALL-NEXT: cmovaeq [[REG4]], [[REG5]]
135; CHECK-LIBCALL-NEXT: popq %rcx
136; CHECK-LIBCALL-NEXT: retq
137
138; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
139; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
140; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
141; CHECK-F16C-NEXT: vmovss {{.[A-Z_0-9]+}}(%rip), [[REG3:%[a-z0-9]+]]
142; CHECK-F16C-NEXT: vsubss [[REG3]], [[REG2]], [[REG4:%[a-z0-9]+]]
143; CHECK-F16C-NEXT: vcvttss2si [[REG4]], [[REG5:%[a-z0-9]+]]
144; CHECK-F16C-NEXT: movabsq $-9223372036854775808, [[REG6:%[a-z0-9]+]]
145; CHECK-F16C-NEXT: xorq [[REG5]], [[REG6:%[a-z0-9]+]]
146; CHECK-F16C-NEXT: vcvttss2si [[REG2]], [[REG7:%[a-z0-9]+]]
147; CHECK-F16C-NEXT: vucomiss [[REG3]], [[REG2]]
148; CHECK-F16C-NEXT: cmovaeq [[REG6]], %rax
149; CHECK-F16C-NEXT: retq
150  %a = load half, half* %p, align 2
151  %r = fptoui half %a to i64
152  ret i64 %r
153}
154
155define void @test_uitofp_i64(i64 %a, half* %p) #0 {
156; CHECK-LABEL: test_uitofp_i64:
157; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z0-9]+]]
158; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
159; CHECK-NEXT: movl %edi, [[REG0:%[a-z0-9]+]]
160; CHECK-NEXT: andl $1, [[REG0]]
161; CHECK-NEXT: testq %rdi, %rdi
162; CHECK-NEXT: js [[LABEL1:.LBB[0-9_]+]]
163
164; simple conversion to float if non-negative
165; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]]
166; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]], [[REG1]]
167; CHECK-NEXT: jmp [[LABEL2:.LBB[0-9_]+]]
168
169; convert using shift+or if negative
170; CHECK-NEXT: [[LABEL1]]:
171; CHECK-NEXT: shrq %rdi
172; CHECK-NEXT: orq %rdi, [[REG2:%[a-z0-9]+]]
173; CHECK-LIBCALL-NEXT: cvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]]
174; CHECK-LIBCALL-NEXT: addss [[REG3]], [[REG1]]
175; CHECK-F16C-NEXT: vcvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]], [[REG3]]
176; CHECK-F16C-NEXT: vaddss [[REG3]], [[REG3]], [[REG1:[%a-z0-9]+]]
177
178; convert float to half
179; CHECK-NEXT: [[LABEL2]]:
180; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
181; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
182; CHECK-LIBCALL-NEXT: popq [[ADDR]]
183; CHECK-F16C-NEXT: vcvtps2ph $4, [[REG1]], [[REG4:%[a-z0-9]+]]
184; CHECK-F16C-NEXT: vmovd [[REG4]], %eax
185; CHECK-F16C-NEXT: movw %ax, (%rsi)
186; CHECK-NEXT: retq
187
188  %r = uitofp i64 %a to half
189  store half %r, half* %p
190  ret void
191}
192
193define <4 x float> @test_extend32_vec4(<4 x half>* %p) #0 {
194; CHECK-LABEL: test_extend32_vec4:
195
196; CHECK-LIBCALL: callq __gnu_h2f_ieee
197; CHECK-LIBCALL: callq __gnu_h2f_ieee
198; CHECK-LIBCALL: callq __gnu_h2f_ieee
199; CHECK-LIBCALL: callq __gnu_h2f_ieee
200; CHECK-F16C: vcvtph2ps
201; CHECK-F16C: vcvtph2ps
202; CHECK-F16C: vcvtph2ps
203; CHECK-F16C: vcvtph2ps
204  %a = load <4 x half>, <4 x half>* %p, align 8
205  %b = fpext <4 x half> %a to <4 x float>
206  ret <4 x float> %b
207}
208
209define <4 x double> @test_extend64_vec4(<4 x half>* %p) #0 {
210; CHECK-LABEL: test_extend64_vec4
211
212; CHECK-LIBCALL: callq __gnu_h2f_ieee
213; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
214; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
215; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
216; CHECK-LIBCALL-DAG: cvtss2sd
217; CHECK-LIBCALL-DAG: cvtss2sd
218; CHECK-LIBCALL-DAG: cvtss2sd
219; CHECK-LIBCALL: cvtss2sd
220; CHECK-F16C: vcvtph2ps
221; CHECK-F16C-DAG: vcvtph2ps
222; CHECK-F16C-DAG: vcvtph2ps
223; CHECK-F16C-DAG: vcvtph2ps
224; CHECK-F16C-DAG: vcvtss2sd
225; CHECK-F16C-DAG: vcvtss2sd
226; CHECK-F16C-DAG: vcvtss2sd
227; CHECK-F16C: vcvtss2sd
228  %a = load <4 x half>, <4 x half>* %p, align 8
229  %b = fpext <4 x half> %a to <4 x double>
230  ret <4 x double> %b
231}
232
233define void @test_trunc32_vec4(<4 x float> %a, <4 x half>* %p) {
234; CHECK-LABEL: test_trunc32_vec4:
235
236; CHECK-LIBCALL: callq __gnu_f2h_ieee
237; CHECK-LIBCALL: callq __gnu_f2h_ieee
238; CHECK-LIBCALL: callq __gnu_f2h_ieee
239; CHECK-LIBCALL: callq __gnu_f2h_ieee
240; CHECK-F16C: vcvtps2ph
241; CHECK-F16C: vcvtps2ph
242; CHECK-F16C: vcvtps2ph
243; CHECK-F16C: vcvtps2ph
244; CHECK: movw
245; CHECK: movw
246; CHECK: movw
247; CHECK: movw
248  %v = fptrunc <4 x float> %a to <4 x half>
249  store <4 x half> %v, <4 x half>* %p
250  ret void
251}
252
253define void @test_trunc64_vec4(<4 x double> %a, <4 x half>* %p) {
254; CHECK-LABEL: test_trunc64_vec4:
255; CHECK: callq  __truncdfhf2
256; CHECK: callq  __truncdfhf2
257; CHECK: callq  __truncdfhf2
258; CHECK: callq  __truncdfhf2
259; CHECK: movw
260; CHECK: movw
261; CHECK: movw
262; CHECK: movw
263  %v = fptrunc <4 x double> %a to <4 x half>
264  store <4 x half> %v, <4 x half>* %p
265  ret void
266}
267
268declare float @test_floatret();
269
270; On i686, if SSE2 is available, the return value from test_floatret is loaded
271; to f80 and then rounded to f32.  The DAG combiner should not combine this
272; fp_round and the subsequent fptrunc from float to half.
273define half @test_f80trunc_nodagcombine() #0 {
274; CHECK-LABEL: test_f80trunc_nodagcombine:
275; CHECK-I686-NOT: calll __truncxfhf2
276  %1 = call float @test_floatret()
277  %2 = fptrunc float %1 to half
278  ret half %2
279}
280
281attributes #0 = { nounwind }
282