1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686--   -mattr=sse2 | FileCheck %s --check-prefixes=ANY,X32-SSE2
3; RUN: llc < %s -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=ANY,X64-AVX2
4
5declare i8 @llvm.fshl.i8(i8, i8, i8)
6declare i16 @llvm.fshl.i16(i16, i16, i16)
7declare i32 @llvm.fshl.i32(i32, i32, i32)
8declare i64 @llvm.fshl.i64(i64, i64, i64)
9declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
10
11declare i8 @llvm.fshr.i8(i8, i8, i8)
12declare i16 @llvm.fshr.i16(i16, i16, i16)
13declare i32 @llvm.fshr.i32(i32, i32, i32)
14declare i64 @llvm.fshr.i64(i64, i64, i64)
15declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
16
17; General case - all operands can be variables
18
19define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) nounwind {
20; X32-SSE2-LABEL: fshl_i32:
21; X32-SSE2:       # %bb.0:
22; X32-SSE2-NEXT:    movb {{[0-9]+}}(%esp), %cl
23; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edx
24; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
25; X32-SSE2-NEXT:    shldl %cl, %edx, %eax
26; X32-SSE2-NEXT:    retl
27;
28; X64-AVX2-LABEL: fshl_i32:
29; X64-AVX2:       # %bb.0:
30; X64-AVX2-NEXT:    movl %edx, %ecx
31; X64-AVX2-NEXT:    movl %edi, %eax
32; X64-AVX2-NEXT:    # kill: def $cl killed $cl killed $ecx
33; X64-AVX2-NEXT:    shldl %cl, %esi, %eax
34; X64-AVX2-NEXT:    retq
35  %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
36  ret i32 %f
37}
38
39; Verify that weird types are minimally supported.
40declare i37 @llvm.fshl.i37(i37, i37, i37)
41define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) nounwind {
42; X32-SSE2-LABEL: fshl_i37:
43; X32-SSE2:       # %bb.0:
44; X32-SSE2-NEXT:    pushl %ebp
45; X32-SSE2-NEXT:    pushl %ebx
46; X32-SSE2-NEXT:    pushl %edi
47; X32-SSE2-NEXT:    pushl %esi
48; X32-SSE2-NEXT:    pushl %eax
49; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edi
50; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %esi
51; X32-SSE2-NEXT:    andl $31, %esi
52; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
53; X32-SSE2-NEXT:    andl $31, %eax
54; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ebp
55; X32-SSE2-NEXT:    pushl $0
56; X32-SSE2-NEXT:    pushl $37
57; X32-SSE2-NEXT:    pushl %eax
58; X32-SSE2-NEXT:    pushl {{[0-9]+}}(%esp)
59; X32-SSE2-NEXT:    calll __umoddi3
60; X32-SSE2-NEXT:    addl $16, %esp
61; X32-SSE2-NEXT:    movl %eax, %ebx
62; X32-SSE2-NEXT:    movl %edx, (%esp) # 4-byte Spill
63; X32-SSE2-NEXT:    movl %ebp, %edx
64; X32-SSE2-NEXT:    movl %ebx, %ecx
65; X32-SSE2-NEXT:    shll %cl, %ebp
66; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
67; X32-SSE2-NEXT:    shldl %cl, %edx, %eax
68; X32-SSE2-NEXT:    xorl %ecx, %ecx
69; X32-SSE2-NEXT:    testb $32, %bl
70; X32-SSE2-NEXT:    cmovnel %ebp, %eax
71; X32-SSE2-NEXT:    cmovnel %ecx, %ebp
72; X32-SSE2-NEXT:    xorl %edx, %edx
73; X32-SSE2-NEXT:    movb $37, %cl
74; X32-SSE2-NEXT:    subb %bl, %cl
75; X32-SSE2-NEXT:    shrdl %cl, %esi, %edi
76; X32-SSE2-NEXT:    shrl %cl, %esi
77; X32-SSE2-NEXT:    testb $32, %cl
78; X32-SSE2-NEXT:    cmovnel %esi, %edi
79; X32-SSE2-NEXT:    cmovnel %edx, %esi
80; X32-SSE2-NEXT:    orl %eax, %esi
81; X32-SSE2-NEXT:    orl %ebp, %edi
82; X32-SSE2-NEXT:    orl %ebx, (%esp) # 4-byte Folded Spill
83; X32-SSE2-NEXT:    cmovel {{[0-9]+}}(%esp), %edi
84; X32-SSE2-NEXT:    cmovel {{[0-9]+}}(%esp), %esi
85; X32-SSE2-NEXT:    movl %edi, %eax
86; X32-SSE2-NEXT:    movl %esi, %edx
87; X32-SSE2-NEXT:    addl $4, %esp
88; X32-SSE2-NEXT:    popl %esi
89; X32-SSE2-NEXT:    popl %edi
90; X32-SSE2-NEXT:    popl %ebx
91; X32-SSE2-NEXT:    popl %ebp
92; X32-SSE2-NEXT:    retl
93;
94; X64-AVX2-LABEL: fshl_i37:
95; X64-AVX2:       # %bb.0:
96; X64-AVX2-NEXT:    movq %rdx, %r8
97; X64-AVX2-NEXT:    movabsq $137438953471, %rax # imm = 0x1FFFFFFFFF
98; X64-AVX2-NEXT:    andq %rax, %rsi
99; X64-AVX2-NEXT:    andq %rax, %r8
100; X64-AVX2-NEXT:    movabsq $-2492803253203993461, %rcx # imm = 0xDD67C8A60DD67C8B
101; X64-AVX2-NEXT:    movq %r8, %rax
102; X64-AVX2-NEXT:    mulq %rcx
103; X64-AVX2-NEXT:    shrq $5, %rdx
104; X64-AVX2-NEXT:    leaq (%rdx,%rdx,8), %rax
105; X64-AVX2-NEXT:    leaq (%rdx,%rax,4), %rax
106; X64-AVX2-NEXT:    subq %rax, %r8
107; X64-AVX2-NEXT:    movq %rdi, %rax
108; X64-AVX2-NEXT:    movl %r8d, %ecx
109; X64-AVX2-NEXT:    shlq %cl, %rax
110; X64-AVX2-NEXT:    movl $37, %ecx
111; X64-AVX2-NEXT:    subl %r8d, %ecx
112; X64-AVX2-NEXT:    # kill: def $cl killed $cl killed $ecx
113; X64-AVX2-NEXT:    shrq %cl, %rsi
114; X64-AVX2-NEXT:    orq %rax, %rsi
115; X64-AVX2-NEXT:    testq %r8, %r8
116; X64-AVX2-NEXT:    cmoveq %rdi, %rsi
117; X64-AVX2-NEXT:    movq %rsi, %rax
118; X64-AVX2-NEXT:    retq
119  %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
120  ret i37 %f
121}
122
123; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
124
125declare i7 @llvm.fshl.i7(i7, i7, i7)
126define i7 @fshl_i7_const_fold() {
127; ANY-LABEL: fshl_i7_const_fold:
128; ANY:       # %bb.0:
129; ANY-NEXT:    movb $67, %al
130; ANY-NEXT:    ret{{[l|q]}}
131  %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
132  ret i7 %f
133}
134
135; With constant shift amount, this is 'shld' with constant operand.
136
137define i32 @fshl_i32_const_shift(i32 %x, i32 %y) nounwind {
138; X32-SSE2-LABEL: fshl_i32_const_shift:
139; X32-SSE2:       # %bb.0:
140; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
141; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
142; X32-SSE2-NEXT:    shldl $9, %ecx, %eax
143; X32-SSE2-NEXT:    retl
144;
145; X64-AVX2-LABEL: fshl_i32_const_shift:
146; X64-AVX2:       # %bb.0:
147; X64-AVX2-NEXT:    movl %edi, %eax
148; X64-AVX2-NEXT:    shldl $9, %esi, %eax
149; X64-AVX2-NEXT:    retq
150  %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
151  ret i32 %f
152}
153
154; Check modulo math on shift amount.
155
156define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) nounwind {
157; X32-SSE2-LABEL: fshl_i32_const_overshift:
158; X32-SSE2:       # %bb.0:
159; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
160; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
161; X32-SSE2-NEXT:    shldl $9, %ecx, %eax
162; X32-SSE2-NEXT:    retl
163;
164; X64-AVX2-LABEL: fshl_i32_const_overshift:
165; X64-AVX2:       # %bb.0:
166; X64-AVX2-NEXT:    movl %edi, %eax
167; X64-AVX2-NEXT:    shldl $9, %esi, %eax
168; X64-AVX2-NEXT:    retq
169  %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
170  ret i32 %f
171}
172
173; 64-bit should also work.
174
175define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) nounwind {
176; X32-SSE2-LABEL: fshl_i64_const_overshift:
177; X32-SSE2:       # %bb.0:
178; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
179; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
180; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edx
181; X32-SSE2-NEXT:    shldl $9, %ecx, %edx
182; X32-SSE2-NEXT:    shrdl $23, %ecx, %eax
183; X32-SSE2-NEXT:    retl
184;
185; X64-AVX2-LABEL: fshl_i64_const_overshift:
186; X64-AVX2:       # %bb.0:
187; X64-AVX2-NEXT:    movq %rdi, %rax
188; X64-AVX2-NEXT:    shldq $41, %rsi, %rax
189; X64-AVX2-NEXT:    retq
190  %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
191  ret i64 %f
192}
193
194; This should work without any node-specific logic.
195
196define i8 @fshl_i8_const_fold() nounwind {
197; ANY-LABEL: fshl_i8_const_fold:
198; ANY:       # %bb.0:
199; ANY-NEXT:    movb $-128, %al
200; ANY-NEXT:    ret{{[l|q]}}
201  %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
202  ret i8 %f
203}
204
205; Repeat everything for funnel shift right.
206
207; General case - all operands can be variables
208
209define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) nounwind {
210; X32-SSE2-LABEL: fshr_i32:
211; X32-SSE2:       # %bb.0:
212; X32-SSE2-NEXT:    movb {{[0-9]+}}(%esp), %cl
213; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edx
214; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
215; X32-SSE2-NEXT:    shrdl %cl, %edx, %eax
216; X32-SSE2-NEXT:    retl
217;
218; X64-AVX2-LABEL: fshr_i32:
219; X64-AVX2:       # %bb.0:
220; X64-AVX2-NEXT:    movl %edx, %ecx
221; X64-AVX2-NEXT:    movl %esi, %eax
222; X64-AVX2-NEXT:    # kill: def $cl killed $cl killed $ecx
223; X64-AVX2-NEXT:    shrdl %cl, %edi, %eax
224; X64-AVX2-NEXT:    retq
225  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
226  ret i32 %f
227}
228
229; Verify that weird types are minimally supported.
230declare i37 @llvm.fshr.i37(i37, i37, i37)
231define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) nounwind {
232; X32-SSE2-LABEL: fshr_i37:
233; X32-SSE2:       # %bb.0:
234; X32-SSE2-NEXT:    pushl %ebp
235; X32-SSE2-NEXT:    pushl %ebx
236; X32-SSE2-NEXT:    pushl %edi
237; X32-SSE2-NEXT:    pushl %esi
238; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %esi
239; X32-SSE2-NEXT:    andl $31, %esi
240; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
241; X32-SSE2-NEXT:    andl $31, %eax
242; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ebp
243; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edi
244; X32-SSE2-NEXT:    pushl $0
245; X32-SSE2-NEXT:    pushl $37
246; X32-SSE2-NEXT:    pushl %eax
247; X32-SSE2-NEXT:    pushl {{[0-9]+}}(%esp)
248; X32-SSE2-NEXT:    calll __umoddi3
249; X32-SSE2-NEXT:    addl $16, %esp
250; X32-SSE2-NEXT:    movl %eax, %ebx
251; X32-SSE2-NEXT:    movb $37, %cl
252; X32-SSE2-NEXT:    subb %bl, %cl
253; X32-SSE2-NEXT:    movl %ebp, %eax
254; X32-SSE2-NEXT:    shll %cl, %ebp
255; X32-SSE2-NEXT:    shldl %cl, %eax, %edi
256; X32-SSE2-NEXT:    xorl %eax, %eax
257; X32-SSE2-NEXT:    testb $32, %cl
258; X32-SSE2-NEXT:    cmovnel %ebp, %edi
259; X32-SSE2-NEXT:    cmovnel %eax, %ebp
260; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
261; X32-SSE2-NEXT:    movl %ebx, %ecx
262; X32-SSE2-NEXT:    shrdl %cl, %esi, %eax
263; X32-SSE2-NEXT:    shrl %cl, %esi
264; X32-SSE2-NEXT:    testb $32, %bl
265; X32-SSE2-NEXT:    cmovnel %esi, %eax
266; X32-SSE2-NEXT:    movl $0, %ecx
267; X32-SSE2-NEXT:    cmovnel %ecx, %esi
268; X32-SSE2-NEXT:    orl %edi, %esi
269; X32-SSE2-NEXT:    orl %ebp, %eax
270; X32-SSE2-NEXT:    orl %ebx, %edx
271; X32-SSE2-NEXT:    cmovel {{[0-9]+}}(%esp), %eax
272; X32-SSE2-NEXT:    cmovel {{[0-9]+}}(%esp), %esi
273; X32-SSE2-NEXT:    movl %esi, %edx
274; X32-SSE2-NEXT:    popl %esi
275; X32-SSE2-NEXT:    popl %edi
276; X32-SSE2-NEXT:    popl %ebx
277; X32-SSE2-NEXT:    popl %ebp
278; X32-SSE2-NEXT:    retl
279;
280; X64-AVX2-LABEL: fshr_i37:
281; X64-AVX2:       # %bb.0:
282; X64-AVX2-NEXT:    movq %rdx, %r8
283; X64-AVX2-NEXT:    movabsq $137438953471, %rax # imm = 0x1FFFFFFFFF
284; X64-AVX2-NEXT:    movq %rsi, %r9
285; X64-AVX2-NEXT:    andq %rax, %r9
286; X64-AVX2-NEXT:    andq %rax, %r8
287; X64-AVX2-NEXT:    movabsq $-2492803253203993461, %rcx # imm = 0xDD67C8A60DD67C8B
288; X64-AVX2-NEXT:    movq %r8, %rax
289; X64-AVX2-NEXT:    mulq %rcx
290; X64-AVX2-NEXT:    shrq $5, %rdx
291; X64-AVX2-NEXT:    leaq (%rdx,%rdx,8), %rax
292; X64-AVX2-NEXT:    leaq (%rdx,%rax,4), %rax
293; X64-AVX2-NEXT:    subq %rax, %r8
294; X64-AVX2-NEXT:    movl %r8d, %ecx
295; X64-AVX2-NEXT:    shrq %cl, %r9
296; X64-AVX2-NEXT:    movl $37, %ecx
297; X64-AVX2-NEXT:    subl %r8d, %ecx
298; X64-AVX2-NEXT:    # kill: def $cl killed $cl killed $ecx
299; X64-AVX2-NEXT:    shlq %cl, %rdi
300; X64-AVX2-NEXT:    orq %r9, %rdi
301; X64-AVX2-NEXT:    testq %r8, %r8
302; X64-AVX2-NEXT:    cmoveq %rsi, %rdi
303; X64-AVX2-NEXT:    movq %rdi, %rax
304; X64-AVX2-NEXT:    retq
305  %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
306  ret i37 %f
307}
308
309; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
310
311declare i7 @llvm.fshr.i7(i7, i7, i7)
312define i7 @fshr_i7_const_fold() nounwind {
313; ANY-LABEL: fshr_i7_const_fold:
314; ANY:       # %bb.0:
315; ANY-NEXT:    movb $31, %al
316; ANY-NEXT:    ret{{[l|q]}}
317  %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
318  ret i7 %f
319}
320
321; With constant shift amount, this is 'shrd' or 'shld'.
322
323define i32 @fshr_i32_const_shift(i32 %x, i32 %y) nounwind {
324; X32-SSE2-LABEL: fshr_i32_const_shift:
325; X32-SSE2:       # %bb.0:
326; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
327; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
328; X32-SSE2-NEXT:    shrdl $9, %ecx, %eax
329; X32-SSE2-NEXT:    retl
330;
331; X64-AVX2-LABEL: fshr_i32_const_shift:
332; X64-AVX2:       # %bb.0:
333; X64-AVX2-NEXT:    movl %edi, %eax
334; X64-AVX2-NEXT:    shldl $23, %esi, %eax
335; X64-AVX2-NEXT:    retq
336  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
337  ret i32 %f
338}
339
340; Check modulo math on shift amount. 41-32=9, but right-shift may became left, so 32-9=23.
341
342define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) nounwind {
343; X32-SSE2-LABEL: fshr_i32_const_overshift:
344; X32-SSE2:       # %bb.0:
345; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
346; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
347; X32-SSE2-NEXT:    shrdl $9, %ecx, %eax
348; X32-SSE2-NEXT:    retl
349;
350; X64-AVX2-LABEL: fshr_i32_const_overshift:
351; X64-AVX2:       # %bb.0:
352; X64-AVX2-NEXT:    movl %edi, %eax
353; X64-AVX2-NEXT:    shldl $23, %esi, %eax
354; X64-AVX2-NEXT:    retq
355  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
356  ret i32 %f
357}
358
359; 64-bit should also work. 105-64 = 41, but right-shift became left, so 64-41=23.
360
361define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) nounwind {
362; X32-SSE2-LABEL: fshr_i64_const_overshift:
363; X32-SSE2:       # %bb.0:
364; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
365; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
366; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edx
367; X32-SSE2-NEXT:    shrdl $9, %ecx, %eax
368; X32-SSE2-NEXT:    shldl $23, %ecx, %edx
369; X32-SSE2-NEXT:    retl
370;
371; X64-AVX2-LABEL: fshr_i64_const_overshift:
372; X64-AVX2:       # %bb.0:
373; X64-AVX2-NEXT:    movq %rdi, %rax
374; X64-AVX2-NEXT:    shldq $23, %rsi, %rax
375; X64-AVX2-NEXT:    retq
376  %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
377  ret i64 %f
378}
379
380; This should work without any node-specific logic.
381
382define i8 @fshr_i8_const_fold() nounwind {
383; ANY-LABEL: fshr_i8_const_fold:
384; ANY:       # %bb.0:
385; ANY-NEXT:    movb $-2, %al
386; ANY-NEXT:    ret{{[l|q]}}
387  %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
388  ret i8 %f
389}
390
391define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) nounwind {
392; X32-SSE2-LABEL: fshl_i32_shift_by_bitwidth:
393; X32-SSE2:       # %bb.0:
394; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
395; X32-SSE2-NEXT:    retl
396;
397; X64-AVX2-LABEL: fshl_i32_shift_by_bitwidth:
398; X64-AVX2:       # %bb.0:
399; X64-AVX2-NEXT:    movl %edi, %eax
400; X64-AVX2-NEXT:    retq
401  %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 32)
402  ret i32 %f
403}
404
405define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) nounwind {
406; X32-SSE2-LABEL: fshr_i32_shift_by_bitwidth:
407; X32-SSE2:       # %bb.0:
408; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
409; X32-SSE2-NEXT:    retl
410;
411; X64-AVX2-LABEL: fshr_i32_shift_by_bitwidth:
412; X64-AVX2:       # %bb.0:
413; X64-AVX2-NEXT:    movl %esi, %eax
414; X64-AVX2-NEXT:    retq
415  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 32)
416  ret i32 %f
417}
418
419define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) nounwind {
420; ANY-LABEL: fshl_v4i32_shift_by_bitwidth:
421; ANY:       # %bb.0:
422; ANY-NEXT:    ret{{[l|q]}}
423  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
424  ret <4 x i32> %f
425}
426
427define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) nounwind {
428; X32-SSE2-LABEL: fshr_v4i32_shift_by_bitwidth:
429; X32-SSE2:       # %bb.0:
430; X32-SSE2-NEXT:    movaps %xmm1, %xmm0
431; X32-SSE2-NEXT:    retl
432;
433; X64-AVX2-LABEL: fshr_v4i32_shift_by_bitwidth:
434; X64-AVX2:       # %bb.0:
435; X64-AVX2-NEXT:    vmovaps %xmm1, %xmm0
436; X64-AVX2-NEXT:    retq
437  %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
438  ret <4 x i32> %f
439}
440
441