1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2    | FileCheck %s --check-prefixes=SSE,SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1  | FileCheck %s --check-prefixes=SSE,SSE41
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx     | FileCheck %s --check-prefixes=AVX1
5
6define float @trunc_unsigned_f32(float %x) #0 {
7; SSE2-LABEL: trunc_unsigned_f32:
8; SSE2:       # %bb.0:
9; SSE2-NEXT:    cvttss2si %xmm0, %rax
10; SSE2-NEXT:    movl %eax, %eax
11; SSE2-NEXT:    xorps %xmm0, %xmm0
12; SSE2-NEXT:    cvtsi2ss %rax, %xmm0
13; SSE2-NEXT:    retq
14;
15; SSE41-LABEL: trunc_unsigned_f32:
16; SSE41:       # %bb.0:
17; SSE41-NEXT:    roundss $11, %xmm0, %xmm0
18; SSE41-NEXT:    retq
19;
20; AVX1-LABEL: trunc_unsigned_f32:
21; AVX1:       # %bb.0:
22; AVX1-NEXT:    vroundss $11, %xmm0, %xmm0, %xmm0
23; AVX1-NEXT:    retq
24  %i = fptoui float %x to i32
25  %r = uitofp i32 %i to float
26  ret float %r
27}
28
29define double @trunc_unsigned_f64(double %x) #0 {
30; SSE2-LABEL: trunc_unsigned_f64:
31; SSE2:       # %bb.0:
32; SSE2-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
33; SSE2-NEXT:    movapd %xmm0, %xmm2
34; SSE2-NEXT:    subsd %xmm1, %xmm2
35; SSE2-NEXT:    cvttsd2si %xmm2, %rax
36; SSE2-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
37; SSE2-NEXT:    xorq %rax, %rcx
38; SSE2-NEXT:    cvttsd2si %xmm0, %rax
39; SSE2-NEXT:    ucomisd %xmm1, %xmm0
40; SSE2-NEXT:    cmovaeq %rcx, %rax
41; SSE2-NEXT:    movq %rax, %xmm1
42; SSE2-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
43; SSE2-NEXT:    subpd {{.*}}(%rip), %xmm1
44; SSE2-NEXT:    movapd %xmm1, %xmm0
45; SSE2-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
46; SSE2-NEXT:    addsd %xmm1, %xmm0
47; SSE2-NEXT:    retq
48;
49; SSE41-LABEL: trunc_unsigned_f64:
50; SSE41:       # %bb.0:
51; SSE41-NEXT:    roundsd $11, %xmm0, %xmm0
52; SSE41-NEXT:    retq
53;
54; AVX1-LABEL: trunc_unsigned_f64:
55; AVX1:       # %bb.0:
56; AVX1-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
57; AVX1-NEXT:    retq
58  %i = fptoui double %x to i64
59  %r = uitofp i64 %i to double
60  ret double %r
61}
62
63define <4 x float> @trunc_unsigned_v4f32(<4 x float> %x) #0 {
64; SSE2-LABEL: trunc_unsigned_v4f32:
65; SSE2:       # %bb.0:
66; SSE2-NEXT:    movaps {{.*#+}} xmm2 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
67; SSE2-NEXT:    movaps %xmm0, %xmm1
68; SSE2-NEXT:    cmpltps %xmm2, %xmm1
69; SSE2-NEXT:    cvttps2dq %xmm0, %xmm3
70; SSE2-NEXT:    subps %xmm2, %xmm0
71; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
72; SSE2-NEXT:    xorps {{.*}}(%rip), %xmm0
73; SSE2-NEXT:    andps %xmm1, %xmm3
74; SSE2-NEXT:    andnps %xmm0, %xmm1
75; SSE2-NEXT:    orps %xmm3, %xmm1
76; SSE2-NEXT:    movaps {{.*#+}} xmm0 = [65535,65535,65535,65535]
77; SSE2-NEXT:    andps %xmm1, %xmm0
78; SSE2-NEXT:    orps {{.*}}(%rip), %xmm0
79; SSE2-NEXT:    psrld $16, %xmm1
80; SSE2-NEXT:    por {{.*}}(%rip), %xmm1
81; SSE2-NEXT:    subps {{.*}}(%rip), %xmm1
82; SSE2-NEXT:    addps %xmm0, %xmm1
83; SSE2-NEXT:    movaps %xmm1, %xmm0
84; SSE2-NEXT:    retq
85;
86; SSE41-LABEL: trunc_unsigned_v4f32:
87; SSE41:       # %bb.0:
88; SSE41-NEXT:    roundps $11, %xmm0, %xmm0
89; SSE41-NEXT:    retq
90;
91; AVX1-LABEL: trunc_unsigned_v4f32:
92; AVX1:       # %bb.0:
93; AVX1-NEXT:    vroundps $11, %xmm0, %xmm0
94; AVX1-NEXT:    retq
95  %i = fptoui <4 x float> %x to <4 x i32>
96  %r = uitofp <4 x i32> %i to <4 x float>
97  ret <4 x float> %r
98}
99
100define <2 x double> @trunc_unsigned_v2f64(<2 x double> %x) #0 {
101; SSE2-LABEL: trunc_unsigned_v2f64:
102; SSE2:       # %bb.0:
103; SSE2-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
104; SSE2-NEXT:    movapd %xmm0, %xmm1
105; SSE2-NEXT:    subsd %xmm2, %xmm1
106; SSE2-NEXT:    cvttsd2si %xmm1, %rax
107; SSE2-NEXT:    movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
108; SSE2-NEXT:    xorq %rcx, %rax
109; SSE2-NEXT:    cvttsd2si %xmm0, %rdx
110; SSE2-NEXT:    ucomisd %xmm2, %xmm0
111; SSE2-NEXT:    cmovaeq %rax, %rdx
112; SSE2-NEXT:    movq %rdx, %xmm1
113; SSE2-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
114; SSE2-NEXT:    movapd %xmm0, %xmm3
115; SSE2-NEXT:    subsd %xmm2, %xmm3
116; SSE2-NEXT:    cvttsd2si %xmm3, %rax
117; SSE2-NEXT:    xorq %rcx, %rax
118; SSE2-NEXT:    cvttsd2si %xmm0, %rcx
119; SSE2-NEXT:    ucomisd %xmm2, %xmm0
120; SSE2-NEXT:    cmovaeq %rax, %rcx
121; SSE2-NEXT:    movq %rcx, %xmm0
122; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
123; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [4294967295,4294967295]
124; SSE2-NEXT:    pand %xmm1, %xmm0
125; SSE2-NEXT:    por {{.*}}(%rip), %xmm0
126; SSE2-NEXT:    psrlq $32, %xmm1
127; SSE2-NEXT:    por {{.*}}(%rip), %xmm1
128; SSE2-NEXT:    subpd {{.*}}(%rip), %xmm1
129; SSE2-NEXT:    addpd %xmm0, %xmm1
130; SSE2-NEXT:    movapd %xmm1, %xmm0
131; SSE2-NEXT:    retq
132;
133; SSE41-LABEL: trunc_unsigned_v2f64:
134; SSE41:       # %bb.0:
135; SSE41-NEXT:    roundpd $11, %xmm0, %xmm0
136; SSE41-NEXT:    retq
137;
138; AVX1-LABEL: trunc_unsigned_v2f64:
139; AVX1:       # %bb.0:
140; AVX1-NEXT:    vroundpd $11, %xmm0, %xmm0
141; AVX1-NEXT:    retq
142  %i = fptoui <2 x double> %x to <2 x i64>
143  %r = uitofp <2 x i64> %i to <2 x double>
144  ret <2 x double> %r
145}
146
147define <4 x double> @trunc_unsigned_v4f64(<4 x double> %x) #0 {
148; SSE2-LABEL: trunc_unsigned_v4f64:
149; SSE2:       # %bb.0:
150; SSE2-NEXT:    movapd %xmm1, %xmm2
151; SSE2-NEXT:    movsd {{.*#+}} xmm3 = mem[0],zero
152; SSE2-NEXT:    subsd %xmm3, %xmm1
153; SSE2-NEXT:    cvttsd2si %xmm1, %rcx
154; SSE2-NEXT:    movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
155; SSE2-NEXT:    xorq %rax, %rcx
156; SSE2-NEXT:    cvttsd2si %xmm2, %rdx
157; SSE2-NEXT:    ucomisd %xmm3, %xmm2
158; SSE2-NEXT:    cmovaeq %rcx, %rdx
159; SSE2-NEXT:    movq %rdx, %xmm1
160; SSE2-NEXT:    unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
161; SSE2-NEXT:    movapd %xmm2, %xmm4
162; SSE2-NEXT:    subsd %xmm3, %xmm4
163; SSE2-NEXT:    cvttsd2si %xmm4, %rcx
164; SSE2-NEXT:    xorq %rax, %rcx
165; SSE2-NEXT:    cvttsd2si %xmm2, %rdx
166; SSE2-NEXT:    ucomisd %xmm3, %xmm2
167; SSE2-NEXT:    cmovaeq %rcx, %rdx
168; SSE2-NEXT:    movq %rdx, %xmm2
169; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
170; SSE2-NEXT:    movapd %xmm0, %xmm2
171; SSE2-NEXT:    subsd %xmm3, %xmm2
172; SSE2-NEXT:    cvttsd2si %xmm2, %rcx
173; SSE2-NEXT:    xorq %rax, %rcx
174; SSE2-NEXT:    cvttsd2si %xmm0, %rdx
175; SSE2-NEXT:    ucomisd %xmm3, %xmm0
176; SSE2-NEXT:    cmovaeq %rcx, %rdx
177; SSE2-NEXT:    movq %rdx, %xmm2
178; SSE2-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
179; SSE2-NEXT:    movapd %xmm0, %xmm4
180; SSE2-NEXT:    subsd %xmm3, %xmm4
181; SSE2-NEXT:    cvttsd2si %xmm4, %rcx
182; SSE2-NEXT:    xorq %rax, %rcx
183; SSE2-NEXT:    cvttsd2si %xmm0, %rax
184; SSE2-NEXT:    ucomisd %xmm3, %xmm0
185; SSE2-NEXT:    cmovaeq %rcx, %rax
186; SSE2-NEXT:    movq %rax, %xmm0
187; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
188; SSE2-NEXT:    movdqa {{.*#+}} xmm0 = [4294967295,4294967295]
189; SSE2-NEXT:    movdqa %xmm2, %xmm3
190; SSE2-NEXT:    pand %xmm0, %xmm3
191; SSE2-NEXT:    movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
192; SSE2-NEXT:    por %xmm4, %xmm3
193; SSE2-NEXT:    psrlq $32, %xmm2
194; SSE2-NEXT:    movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
195; SSE2-NEXT:    por %xmm5, %xmm2
196; SSE2-NEXT:    movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
197; SSE2-NEXT:    subpd %xmm6, %xmm2
198; SSE2-NEXT:    addpd %xmm3, %xmm2
199; SSE2-NEXT:    pand %xmm1, %xmm0
200; SSE2-NEXT:    por %xmm4, %xmm0
201; SSE2-NEXT:    psrlq $32, %xmm1
202; SSE2-NEXT:    por %xmm5, %xmm1
203; SSE2-NEXT:    subpd %xmm6, %xmm1
204; SSE2-NEXT:    addpd %xmm0, %xmm1
205; SSE2-NEXT:    movapd %xmm2, %xmm0
206; SSE2-NEXT:    retq
207;
208; SSE41-LABEL: trunc_unsigned_v4f64:
209; SSE41:       # %bb.0:
210; SSE41-NEXT:    roundpd $11, %xmm0, %xmm0
211; SSE41-NEXT:    roundpd $11, %xmm1, %xmm1
212; SSE41-NEXT:    retq
213;
214; AVX1-LABEL: trunc_unsigned_v4f64:
215; AVX1:       # %bb.0:
216; AVX1-NEXT:    vroundpd $11, %ymm0, %ymm0
217; AVX1-NEXT:    retq
218  %i = fptoui <4 x double> %x to <4 x i64>
219  %r = uitofp <4 x i64> %i to <4 x double>
220  ret <4 x double> %r
221}
222
223define float @trunc_signed_f32_no_fast_math(float %x) {
224; SSE-LABEL: trunc_signed_f32_no_fast_math:
225; SSE:       # %bb.0:
226; SSE-NEXT:    cvttps2dq %xmm0, %xmm0
227; SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
228; SSE-NEXT:    retq
229;
230; AVX1-LABEL: trunc_signed_f32_no_fast_math:
231; AVX1:       # %bb.0:
232; AVX1-NEXT:    vcvttps2dq %xmm0, %xmm0
233; AVX1-NEXT:    vcvtdq2ps %xmm0, %xmm0
234; AVX1-NEXT:    retq
235  %i = fptosi float %x to i32
236  %r = sitofp i32 %i to float
237  ret float %r
238}
239
240; Without -0.0, it is ok to use roundss if it is available.
241
242define float @trunc_signed_f32_nsz(float %x) #0 {
243; SSE2-LABEL: trunc_signed_f32_nsz:
244; SSE2:       # %bb.0:
245; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
246; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
247; SSE2-NEXT:    retq
248;
249; SSE41-LABEL: trunc_signed_f32_nsz:
250; SSE41:       # %bb.0:
251; SSE41-NEXT:    roundss $11, %xmm0, %xmm0
252; SSE41-NEXT:    retq
253;
254; AVX1-LABEL: trunc_signed_f32_nsz:
255; AVX1:       # %bb.0:
256; AVX1-NEXT:    vroundss $11, %xmm0, %xmm0, %xmm0
257; AVX1-NEXT:    retq
258  %i = fptosi float %x to i32
259  %r = sitofp i32 %i to float
260  ret float %r
261}
262
263define double @trunc_signed32_f64_no_fast_math(double %x) {
264; SSE-LABEL: trunc_signed32_f64_no_fast_math:
265; SSE:       # %bb.0:
266; SSE-NEXT:    cvttsd2si %xmm0, %eax
267; SSE-NEXT:    xorps %xmm0, %xmm0
268; SSE-NEXT:    cvtsi2sd %eax, %xmm0
269; SSE-NEXT:    retq
270;
271; AVX1-LABEL: trunc_signed32_f64_no_fast_math:
272; AVX1:       # %bb.0:
273; AVX1-NEXT:    vcvttsd2si %xmm0, %eax
274; AVX1-NEXT:    vcvtsi2sd %eax, %xmm1, %xmm0
275; AVX1-NEXT:    retq
276  %i = fptosi double %x to i32
277  %r = sitofp i32 %i to double
278  ret double %r
279}
280
281define double @trunc_signed32_f64_nsz(double %x) #0 {
282; SSE2-LABEL: trunc_signed32_f64_nsz:
283; SSE2:       # %bb.0:
284; SSE2-NEXT:    cvttsd2si %xmm0, %eax
285; SSE2-NEXT:    xorps %xmm0, %xmm0
286; SSE2-NEXT:    cvtsi2sd %eax, %xmm0
287; SSE2-NEXT:    retq
288;
289; SSE41-LABEL: trunc_signed32_f64_nsz:
290; SSE41:       # %bb.0:
291; SSE41-NEXT:    roundsd $11, %xmm0, %xmm0
292; SSE41-NEXT:    retq
293;
294; AVX1-LABEL: trunc_signed32_f64_nsz:
295; AVX1:       # %bb.0:
296; AVX1-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
297; AVX1-NEXT:    retq
298  %i = fptosi double %x to i32
299  %r = sitofp i32 %i to double
300  ret double %r
301}
302
303define double @trunc_signed_f64_no_fast_math(double %x) {
304; SSE-LABEL: trunc_signed_f64_no_fast_math:
305; SSE:       # %bb.0:
306; SSE-NEXT:    cvttsd2si %xmm0, %rax
307; SSE-NEXT:    xorps %xmm0, %xmm0
308; SSE-NEXT:    cvtsi2sd %rax, %xmm0
309; SSE-NEXT:    retq
310;
311; AVX1-LABEL: trunc_signed_f64_no_fast_math:
312; AVX1:       # %bb.0:
313; AVX1-NEXT:    vcvttsd2si %xmm0, %rax
314; AVX1-NEXT:    vcvtsi2sd %rax, %xmm1, %xmm0
315; AVX1-NEXT:    retq
316  %i = fptosi double %x to i64
317  %r = sitofp i64 %i to double
318  ret double %r
319}
320
321define double @trunc_signed_f64_nsz(double %x) #0 {
322; SSE2-LABEL: trunc_signed_f64_nsz:
323; SSE2:       # %bb.0:
324; SSE2-NEXT:    cvttsd2si %xmm0, %rax
325; SSE2-NEXT:    xorps %xmm0, %xmm0
326; SSE2-NEXT:    cvtsi2sd %rax, %xmm0
327; SSE2-NEXT:    retq
328;
329; SSE41-LABEL: trunc_signed_f64_nsz:
330; SSE41:       # %bb.0:
331; SSE41-NEXT:    roundsd $11, %xmm0, %xmm0
332; SSE41-NEXT:    retq
333;
334; AVX1-LABEL: trunc_signed_f64_nsz:
335; AVX1:       # %bb.0:
336; AVX1-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
337; AVX1-NEXT:    retq
338  %i = fptosi double %x to i64
339  %r = sitofp i64 %i to double
340  ret double %r
341}
342
343define <4 x float> @trunc_signed_v4f32_nsz(<4 x float> %x) #0 {
344; SSE2-LABEL: trunc_signed_v4f32_nsz:
345; SSE2:       # %bb.0:
346; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
347; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
348; SSE2-NEXT:    retq
349;
350; SSE41-LABEL: trunc_signed_v4f32_nsz:
351; SSE41:       # %bb.0:
352; SSE41-NEXT:    roundps $11, %xmm0, %xmm0
353; SSE41-NEXT:    retq
354;
355; AVX1-LABEL: trunc_signed_v4f32_nsz:
356; AVX1:       # %bb.0:
357; AVX1-NEXT:    vroundps $11, %xmm0, %xmm0
358; AVX1-NEXT:    retq
359  %i = fptosi <4 x float> %x to <4 x i32>
360  %r = sitofp <4 x i32> %i to <4 x float>
361  ret <4 x float> %r
362}
363
364define <2 x double> @trunc_signed_v2f64_nsz(<2 x double> %x) #0 {
365; SSE2-LABEL: trunc_signed_v2f64_nsz:
366; SSE2:       # %bb.0:
367; SSE2-NEXT:    cvttsd2si %xmm0, %rax
368; SSE2-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
369; SSE2-NEXT:    cvttsd2si %xmm0, %rcx
370; SSE2-NEXT:    xorps %xmm0, %xmm0
371; SSE2-NEXT:    cvtsi2sd %rax, %xmm0
372; SSE2-NEXT:    cvtsi2sd %rcx, %xmm1
373; SSE2-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
374; SSE2-NEXT:    retq
375;
376; SSE41-LABEL: trunc_signed_v2f64_nsz:
377; SSE41:       # %bb.0:
378; SSE41-NEXT:    roundpd $11, %xmm0, %xmm0
379; SSE41-NEXT:    retq
380;
381; AVX1-LABEL: trunc_signed_v2f64_nsz:
382; AVX1:       # %bb.0:
383; AVX1-NEXT:    vroundpd $11, %xmm0, %xmm0
384; AVX1-NEXT:    retq
385  %i = fptosi <2 x double> %x to <2 x i64>
386  %r = sitofp <2 x i64> %i to <2 x double>
387  ret <2 x double> %r
388}
389
390define <4 x double> @trunc_signed_v4f64_nsz(<4 x double> %x) #0 {
391; SSE2-LABEL: trunc_signed_v4f64_nsz:
392; SSE2:       # %bb.0:
393; SSE2-NEXT:    cvttsd2si %xmm1, %rax
394; SSE2-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
395; SSE2-NEXT:    cvttsd2si %xmm1, %rcx
396; SSE2-NEXT:    cvttsd2si %xmm0, %rdx
397; SSE2-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
398; SSE2-NEXT:    cvttsd2si %xmm0, %rsi
399; SSE2-NEXT:    xorps %xmm0, %xmm0
400; SSE2-NEXT:    cvtsi2sd %rdx, %xmm0
401; SSE2-NEXT:    xorps %xmm1, %xmm1
402; SSE2-NEXT:    cvtsi2sd %rsi, %xmm1
403; SSE2-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
404; SSE2-NEXT:    xorps %xmm1, %xmm1
405; SSE2-NEXT:    cvtsi2sd %rax, %xmm1
406; SSE2-NEXT:    cvtsi2sd %rcx, %xmm2
407; SSE2-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
408; SSE2-NEXT:    retq
409;
410; SSE41-LABEL: trunc_signed_v4f64_nsz:
411; SSE41:       # %bb.0:
412; SSE41-NEXT:    roundpd $11, %xmm0, %xmm0
413; SSE41-NEXT:    roundpd $11, %xmm1, %xmm1
414; SSE41-NEXT:    retq
415;
416; AVX1-LABEL: trunc_signed_v4f64_nsz:
417; AVX1:       # %bb.0:
418; AVX1-NEXT:    vroundpd $11, %ymm0, %ymm0
419; AVX1-NEXT:    retq
420  %i = fptosi <4 x double> %x to <4 x i64>
421  %r = sitofp <4 x i64> %i to <4 x double>
422  ret <4 x double> %r
423}
424
425; The fold may be guarded to allow existing code to continue
426; working based on its assumptions of float->int overflow.
427
428define float @trunc_unsigned_f32_disable_via_attr(float %x) #1 {
429; SSE-LABEL: trunc_unsigned_f32_disable_via_attr:
430; SSE:       # %bb.0:
431; SSE-NEXT:    cvttss2si %xmm0, %rax
432; SSE-NEXT:    movl %eax, %eax
433; SSE-NEXT:    xorps %xmm0, %xmm0
434; SSE-NEXT:    cvtsi2ss %rax, %xmm0
435; SSE-NEXT:    retq
436;
437; AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
438; AVX1:       # %bb.0:
439; AVX1-NEXT:    vcvttss2si %xmm0, %rax
440; AVX1-NEXT:    movl %eax, %eax
441; AVX1-NEXT:    vcvtsi2ss %rax, %xmm1, %xmm0
442; AVX1-NEXT:    retq
443  %i = fptoui float %x to i32
444  %r = uitofp i32 %i to float
445  ret float %r
446}
447
448define double @trunc_signed_f64_disable_via_attr(double %x) #1 {
449; SSE-LABEL: trunc_signed_f64_disable_via_attr:
450; SSE:       # %bb.0:
451; SSE-NEXT:    cvttsd2si %xmm0, %rax
452; SSE-NEXT:    xorps %xmm0, %xmm0
453; SSE-NEXT:    cvtsi2sd %rax, %xmm0
454; SSE-NEXT:    retq
455;
456; AVX1-LABEL: trunc_signed_f64_disable_via_attr:
457; AVX1:       # %bb.0:
458; AVX1-NEXT:    vcvttsd2si %xmm0, %rax
459; AVX1-NEXT:    vcvtsi2sd %rax, %xmm1, %xmm0
460; AVX1-NEXT:    retq
461  %i = fptosi double %x to i64
462  %r = sitofp i64 %i to double
463  ret double %r
464}
465
466attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" }
467attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" "strict-float-cast-overflow"="false" }
468