1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+sse2 | FileCheck %s --check-prefix=SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx  | FileCheck %s --check-prefix=AVX
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq,+avx512vl  | FileCheck %s --check-prefix=AVX512DQ
5
6; Test that we can replace "scalar" FP-bitwise-logic with the optimal instruction.
7; Scalar x86 FP-logic instructions only exist in your imagination and/or the bowels
8; of compilers, but float and double variants of FP-logic instructions are reality
9; and float may be a shorter instruction depending on which flavor of vector ISA
10; you have...so just prefer float all the time, ok? Yay, x86!
11
12define double @FsANDPSrr(double %x, double %y) {
13; SSE-LABEL: FsANDPSrr:
14; SSE:       # BB#0:
15; SSE-NEXT:    andps %xmm1, %xmm0 # encoding: [0x0f,0x54,0xc1]
16; SSE-NEXT:    retq # encoding: [0xc3]
17;
18; AVX-LABEL: FsANDPSrr:
19; AVX:       # BB#0:
20; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x54,0xc1]
21; AVX-NEXT:    retq # encoding: [0xc3]
22;
23; AVX512DQ-LABEL: FsANDPSrr:
24; AVX512DQ:       # BB#0:
25; AVX512DQ-NEXT:    vandps %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf1,0x7c,0x08,0x54,0xc1]
26; AVX512DQ-NEXT:    retq # encoding: [0xc3]
27;
28  %bc1 = bitcast double %x to i64
29  %bc2 = bitcast double %y to i64
30  %and = and i64 %bc1, %bc2
31  %bc3 = bitcast i64 %and to double
32  ret double %bc3
33}
34
35define double @FsANDNPSrr(double %x, double %y) {
36; SSE-LABEL: FsANDNPSrr:
37; SSE:       # BB#0:
38; SSE-NEXT:    andnps %xmm0, %xmm1 # encoding: [0x0f,0x55,0xc8]
39; SSE-NEXT:    movaps %xmm1, %xmm0 # encoding: [0x0f,0x28,0xc1]
40; SSE-NEXT:    retq # encoding: [0xc3]
41;
42; AVX-LABEL: FsANDNPSrr:
43; AVX:       # BB#0:
44; AVX-NEXT:    vandnps %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf0,0x55,0xc0]
45; AVX-NEXT:    retq # encoding: [0xc3]
46;
47; AVX512DQ-LABEL: FsANDNPSrr:
48; AVX512DQ:       # BB#0:
49; AVX512DQ-NEXT:    vandnps %xmm0, %xmm1, %xmm0 # encoding: [0x62,0xf1,0x74,0x08,0x55,0xc0]
50; AVX512DQ-NEXT:    retq # encoding: [0xc3]
51;
52  %bc1 = bitcast double %x to i64
53  %bc2 = bitcast double %y to i64
54  %not = xor i64 %bc2, -1
55  %and = and i64 %bc1, %not
56  %bc3 = bitcast i64 %and to double
57  ret double %bc3
58}
59
60define double @FsORPSrr(double %x, double %y) {
61; SSE-LABEL: FsORPSrr:
62; SSE:       # BB#0:
63; SSE-NEXT:    orps %xmm1, %xmm0 # encoding: [0x0f,0x56,0xc1]
64; SSE-NEXT:    retq # encoding: [0xc3]
65;
66; AVX-LABEL: FsORPSrr:
67; AVX:       # BB#0:
68; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x56,0xc1]
69; AVX-NEXT:    retq # encoding: [0xc3]
70;
71; AVX512DQ-LABEL: FsORPSrr:
72; AVX512DQ:       # BB#0:
73; AVX512DQ-NEXT:    vorps %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf1,0x7c,0x08,0x56,0xc1]
74; AVX512DQ-NEXT:    retq # encoding: [0xc3]
75;
76  %bc1 = bitcast double %x to i64
77  %bc2 = bitcast double %y to i64
78  %or = or i64 %bc1, %bc2
79  %bc3 = bitcast i64 %or to double
80  ret double %bc3
81}
82
83define double @FsXORPSrr(double %x, double %y) {
84; SSE-LABEL: FsXORPSrr:
85; SSE:       # BB#0:
86; SSE-NEXT:    xorps %xmm1, %xmm0 # encoding: [0x0f,0x57,0xc1]
87; SSE-NEXT:    retq # encoding: [0xc3]
88;
89; AVX-LABEL: FsXORPSrr:
90; AVX:       # BB#0:
91; AVX-NEXT:    vxorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc1]
92; AVX-NEXT:    retq # encoding: [0xc3]
93;
94; AVX512DQ-LABEL: FsXORPSrr:
95; AVX512DQ:       # BB#0:
96; AVX512DQ-NEXT:    vxorps %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf1,0x7c,0x08,0x57,0xc1]
97; AVX512DQ-NEXT:    retq # encoding: [0xc3]
98;
99  %bc1 = bitcast double %x to i64
100  %bc2 = bitcast double %y to i64
101  %xor = xor i64 %bc1, %bc2
102  %bc3 = bitcast i64 %xor to double
103  ret double %bc3
104}
105
106