1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s --check-prefix=AVX
4
5; Test that we can replace "scalar" FP-bitwise-logic with the optimal instruction.
6; Scalar x86 FP-logic instructions only exist in your imagination and/or the bowels
7; of compilers, but float and double variants of FP-logic instructions are reality
8; and float may be a shorter instruction depending on which flavor of vector ISA
9; you have...so just prefer float all the time, ok? Yay, x86!
10
11define double @FsANDPSrr(double %x, double %y) {
12; SSE-LABEL: FsANDPSrr:
13; SSE:       # BB#0:
14; SSE-NEXT:    andps %xmm1, %xmm0
15; SSE-NEXT:    retq
16;
17; AVX-LABEL: FsANDPSrr:
18; AVX:       # BB#0:
19; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0
20; AVX-NEXT:    retq
21;
22  %bc1 = bitcast double %x to i64
23  %bc2 = bitcast double %y to i64
24  %and = and i64 %bc1, %bc2
25  %bc3 = bitcast i64 %and to double
26  ret double %bc3
27}
28
29define double @FsANDNPSrr(double %x, double %y) {
30; SSE-LABEL: FsANDNPSrr:
31; SSE:       # BB#0:
32; SSE-NEXT:    andnps %xmm0, %xmm1
33; SSE-NEXT:    movaps %xmm1, %xmm0
34; SSE-NEXT:    retq
35;
36; AVX-LABEL: FsANDNPSrr:
37; AVX:       # BB#0:
38; AVX-NEXT:    vandnps %xmm0, %xmm1, %xmm0
39; AVX-NEXT:    retq
40;
41  %bc1 = bitcast double %x to i64
42  %bc2 = bitcast double %y to i64
43  %not = xor i64 %bc2, -1
44  %and = and i64 %bc1, %not
45  %bc3 = bitcast i64 %and to double
46  ret double %bc3
47}
48
49define double @FsORPSrr(double %x, double %y) {
50; SSE-LABEL: FsORPSrr:
51; SSE:       # BB#0:
52; SSE-NEXT:    orps %xmm1, %xmm0
53; SSE-NEXT:    retq
54;
55; AVX-LABEL: FsORPSrr:
56; AVX:       # BB#0:
57; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
58; AVX-NEXT:    retq
59;
60  %bc1 = bitcast double %x to i64
61  %bc2 = bitcast double %y to i64
62  %or = or i64 %bc1, %bc2
63  %bc3 = bitcast i64 %or to double
64  ret double %bc3
65}
66
67define double @FsXORPSrr(double %x, double %y) {
68; SSE-LABEL: FsXORPSrr:
69; SSE:       # BB#0:
70; SSE-NEXT:    xorps %xmm1, %xmm0
71; SSE-NEXT:    retq
72;
73; AVX-LABEL: FsXORPSrr:
74; AVX:       # BB#0:
75; AVX-NEXT:    vxorps %xmm1, %xmm0, %xmm0
76; AVX-NEXT:    retq
77;
78  %bc1 = bitcast double %x to i64
79  %bc2 = bitcast double %y to i64
80  %xor = xor i64 %bc1, %bc2
81  %bc3 = bitcast i64 %xor to double
82  ret double %bc3
83}
84
85