1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s --check-prefix=AVX
4
5; Test that we can replace "scalar" FP-bitwise-logic with the optimal instruction.
6; Scalar x86 FP-logic instructions only exist in your imagination and/or the bowels
7; of compilers, but float and double variants of FP-logic instructions are reality
8; and float may be a shorter instruction depending on which flavor of vector ISA
9; you have...so just prefer float all the time, ok? Yay, x86!
10
11define double @FsANDPSrr(double %x, double %y) {
12; SSE-LABEL: FsANDPSrr:
13; SSE:       # BB#0:
14; SSE-NEXT:    andps %xmm1, %xmm0
15; SSE-NEXT:    retq
16;
17; AVX-LABEL: FsANDPSrr:
18; AVX:       # BB#0:
19; AVX-NEXT:    vandps %xmm1, %xmm0, %xmm0
20; AVX-NEXT:    retq
21;
22  %bc1 = bitcast double %x to i64
23  %bc2 = bitcast double %y to i64
24  %and = and i64 %bc1, %bc2
25  %bc3 = bitcast i64 %and to double
26  ret double %bc3
27}
28
29define double @FsANDNPSrr(double %x, double %y) {
30; SSE-LABEL: FsANDNPSrr:
31; SSE:       # BB#0:
32; SSE-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
33; SSE-NEXT:    xorpd %xmm1, %xmm2
34; SSE-NEXT:    andpd %xmm2, %xmm0
35; SSE-NEXT:    retq
36;
37; AVX-LABEL: FsANDNPSrr:
38; AVX:       # BB#0:
39; AVX-NEXT:    vmovsd {{.*#+}} xmm2 = mem[0],zero
40; AVX-NEXT:    vxorpd %xmm2, %xmm1, %xmm1
41; AVX-NEXT:    vandpd %xmm1, %xmm0, %xmm0
42; AVX-NEXT:    retq
43;
44  %bc1 = bitcast double %x to i64
45  %bc2 = bitcast double %y to i64
46  %not = xor i64 %bc2, -1
47  %and = and i64 %bc1, %not
48  %bc3 = bitcast i64 %and to double
49  ret double %bc3
50}
51
52define double @FsORPSrr(double %x, double %y) {
53; SSE-LABEL: FsORPSrr:
54; SSE:       # BB#0:
55; SSE-NEXT:    orps %xmm1, %xmm0
56; SSE-NEXT:    retq
57;
58; AVX-LABEL: FsORPSrr:
59; AVX:       # BB#0:
60; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
61; AVX-NEXT:    retq
62;
63  %bc1 = bitcast double %x to i64
64  %bc2 = bitcast double %y to i64
65  %or = or i64 %bc1, %bc2
66  %bc3 = bitcast i64 %or to double
67  ret double %bc3
68}
69
70define double @FsXORPSrr(double %x, double %y) {
71; SSE-LABEL: FsXORPSrr:
72; SSE:       # BB#0:
73; SSE-NEXT:    xorps %xmm1, %xmm0
74; SSE-NEXT:    retq
75;
76; AVX-LABEL: FsXORPSrr:
77; AVX:       # BB#0:
78; AVX-NEXT:    vxorps %xmm1, %xmm0, %xmm0
79; AVX-NEXT:    retq
80;
81  %bc1 = bitcast double %x to i64
82  %bc2 = bitcast double %y to i64
83  %xor = xor i64 %bc1, %bc2
84  %bc3 = bitcast i64 %xor to double
85  ret double %bc3
86}
87
88