1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10                  | FileCheck %s --check-prefix=CHECK --check-prefix=NOAVX512
3; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -mattr=+avx512f  | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
4
5; Test conditional move for the supported types (i16, i32, and i32) and
6; conditon input (argument or cmp). Currently i8 is not supported.
7
8define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroext %b) {
9; NOAVX512-LABEL: select_cmov_i16:
10; NOAVX512:       ## BB#0:
11; NOAVX512-NEXT:    testb $1, %dil
12; NOAVX512-NEXT:    cmovew %dx, %si
13; NOAVX512-NEXT:    movzwl %si, %eax
14; NOAVX512-NEXT:    retq
15;
16; AVX512-LABEL: select_cmov_i16:
17; AVX512:       ## BB#0:
18; AVX512-NEXT:    kmovw %edi, %k0
19; AVX512-NEXT:    kmovw %k0, %eax
20; AVX512-NEXT:    testb $1, %al
21; AVX512-NEXT:    cmovew %dx, %si
22; AVX512-NEXT:    movzwl %si, %eax
23; AVX512-NEXT:    retq
24  %1 = select i1 %cond, i16 %a, i16 %b
25  ret i16 %1
26}
27
28define zeroext i16 @select_cmp_cmov_i16(i16 zeroext %a, i16 zeroext %b) {
29; CHECK-LABEL: select_cmp_cmov_i16:
30; CHECK:       ## BB#0:
31; CHECK-NEXT:    cmpw %si, %di
32; CHECK-NEXT:    cmovbw %di, %si
33; CHECK-NEXT:    movzwl %si, %eax
34; CHECK-NEXT:    retq
35  %1 = icmp ult i16 %a, %b
36  %2 = select i1 %1, i16 %a, i16 %b
37  ret i16 %2
38}
39
40define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
41; NOAVX512-LABEL: select_cmov_i32:
42; NOAVX512:       ## BB#0:
43; NOAVX512-NEXT:    testb $1, %dil
44; NOAVX512-NEXT:    cmovel %edx, %esi
45; NOAVX512-NEXT:    movl %esi, %eax
46; NOAVX512-NEXT:    retq
47;
48; AVX512-LABEL: select_cmov_i32:
49; AVX512:       ## BB#0:
50; AVX512-NEXT:    kmovw %edi, %k0
51; AVX512-NEXT:    kmovw %k0, %eax
52; AVX512-NEXT:    testb $1, %al
53; AVX512-NEXT:    cmovel %edx, %esi
54; AVX512-NEXT:    movl %esi, %eax
55; AVX512-NEXT:    retq
56  %1 = select i1 %cond, i32 %a, i32 %b
57  ret i32 %1
58}
59
60define i32 @select_cmp_cmov_i32(i32 %a, i32 %b) {
61; CHECK-LABEL: select_cmp_cmov_i32:
62; CHECK:       ## BB#0:
63; CHECK-NEXT:    cmpl %esi, %edi
64; CHECK-NEXT:    cmovbl %edi, %esi
65; CHECK-NEXT:    movl %esi, %eax
66; CHECK-NEXT:    retq
67  %1 = icmp ult i32 %a, %b
68  %2 = select i1 %1, i32 %a, i32 %b
69  ret i32 %2
70}
71
72define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
73; NOAVX512-LABEL: select_cmov_i64:
74; NOAVX512:       ## BB#0:
75; NOAVX512-NEXT:    testb $1, %dil
76; NOAVX512-NEXT:    cmoveq %rdx, %rsi
77; NOAVX512-NEXT:    movq %rsi, %rax
78; NOAVX512-NEXT:    retq
79;
80; AVX512-LABEL: select_cmov_i64:
81; AVX512:       ## BB#0:
82; AVX512-NEXT:    kmovw %edi, %k0
83; AVX512-NEXT:    kmovw %k0, %eax
84; AVX512-NEXT:    testb $1, %al
85; AVX512-NEXT:    cmoveq %rdx, %rsi
86; AVX512-NEXT:    movq %rsi, %rax
87; AVX512-NEXT:    retq
88  %1 = select i1 %cond, i64 %a, i64 %b
89  ret i64 %1
90}
91
92define i64 @select_cmp_cmov_i64(i64 %a, i64 %b) {
93; CHECK-LABEL: select_cmp_cmov_i64:
94; CHECK:       ## BB#0:
95; CHECK-NEXT:    cmpq %rsi, %rdi
96; CHECK-NEXT:    cmovbq %rdi, %rsi
97; CHECK-NEXT:    movq %rsi, %rax
98; CHECK-NEXT:    retq
99  %1 = icmp ult i64 %a, %b
100  %2 = select i1 %1, i64 %a, i64 %b
101  ret i64 %2
102}
103
104