1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE2
3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=X64,X64-SSSE3
4; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx  | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
5; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
6
7target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
8
9define i32 @t(<2 x i64>* %val) nounwind  {
10; X32-SSE2-LABEL: t:
11; X32-SSE2:       # %bb.0:
12; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
13; X32-SSE2-NEXT:    pshufd {{.*#+}} xmm0 = mem[2,3,2,3]
14; X32-SSE2-NEXT:    movd %xmm0, %eax
15; X32-SSE2-NEXT:    retl
16;
17; X64-SSSE3-LABEL: t:
18; X64-SSSE3:       # %bb.0:
19; X64-SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = mem[2,3,2,3]
20; X64-SSSE3-NEXT:    movd %xmm0, %eax
21; X64-SSSE3-NEXT:    retq
22;
23; X64-AVX-LABEL: t:
24; X64-AVX:       # %bb.0:
25; X64-AVX-NEXT:    movl 8(%rdi), %eax
26; X64-AVX-NEXT:    retq
27  %tmp2 = load <2 x i64>, <2 x i64>* %val, align 16		; <<2 x i64>> [#uses=1]
28  %tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
29  %tmp4 = extractelement <4 x i32> %tmp3, i32 2		; <i32> [#uses=1]
30  ret i32 %tmp4
31}
32
33; Case where extractelement of load ends up as undef.
34; (Making sure this doesn't crash.)
35define i32 @t2(<8 x i32>* %xp) {
36; X32-SSE2-LABEL: t2:
37; X32-SSE2:       # %bb.0:
38; X32-SSE2-NEXT:    retl
39;
40; X64-LABEL: t2:
41; X64:       # %bb.0:
42; X64-NEXT:    retq
43  %x = load <8 x i32>, <8 x i32>* %xp
44  %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
45  %y = extractelement <8 x i32> %Shuff68, i32 0
46  ret i32 %y
47}
48
49; This case could easily end up inf-looping in the DAG combiner due to an
50; low alignment load of the vector which prevents us from reliably forming a
51; narrow load.
52
53define void @t3(<2 x double>* %a0) {
54; X32-SSE2-LABEL: t3:
55; X32-SSE2:       # %bb.0: # %bb
56; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
57; X32-SSE2-NEXT:    movups (%eax), %xmm0
58; X32-SSE2-NEXT:    movhps %xmm0, (%eax)
59; X32-SSE2-NEXT:    retl
60;
61; X64-SSSE3-LABEL: t3:
62; X64-SSSE3:       # %bb.0: # %bb
63; X64-SSSE3-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
64; X64-SSSE3-NEXT:    movsd %xmm0, (%rax)
65; X64-SSSE3-NEXT:    retq
66;
67; X64-AVX-LABEL: t3:
68; X64-AVX:       # %bb.0: # %bb
69; X64-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
70; X64-AVX-NEXT:    vmovsd %xmm0, (%rax)
71; X64-AVX-NEXT:    retq
72bb:
73  %tmp13 = load <2 x double>, <2 x double>* %a0, align 1
74  %.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
75  store double %.sroa.3.24.vec.extract, double* undef, align 8
76  ret void
77}
78
79; Case where a load is unary shuffled, then bitcast (to a type with the same
80; number of elements) before extractelement.
81; This is testing for an assertion - the extraction was assuming that the undef
82; second shuffle operand was a post-bitcast type instead of a pre-bitcast type.
83define i64 @t4(<2 x double>* %a) {
84; X32-SSE2-LABEL: t4:
85; X32-SSE2:       # %bb.0:
86; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
87; X32-SSE2-NEXT:    movdqa (%eax), %xmm0
88; X32-SSE2-NEXT:    movd %xmm0, %eax
89; X32-SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
90; X32-SSE2-NEXT:    movd %xmm0, %edx
91; X32-SSE2-NEXT:    retl
92;
93; X64-LABEL: t4:
94; X64:       # %bb.0:
95; X64-NEXT:    movq (%rdi), %rax
96; X64-NEXT:    retq
97  %b = load <2 x double>, <2 x double>* %a, align 16
98  %c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
99  %d = bitcast <2 x double> %c to <2 x i64>
100  %e = extractelement <2 x i64> %d, i32 1
101  ret i64 %e
102}
103
104; Don't extract from a volatile.
105define void @t5(<2 x double> *%a0, double *%a1) {
106; X32-SSE2-LABEL: t5:
107; X32-SSE2:       # %bb.0:
108; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
109; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
110; X32-SSE2-NEXT:    movaps (%ecx), %xmm0
111; X32-SSE2-NEXT:    movhps %xmm0, (%eax)
112; X32-SSE2-NEXT:    retl
113;
114; X64-SSSE3-LABEL: t5:
115; X64-SSSE3:       # %bb.0:
116; X64-SSSE3-NEXT:    movaps (%rdi), %xmm0
117; X64-SSSE3-NEXT:    movhps %xmm0, (%rsi)
118; X64-SSSE3-NEXT:    retq
119;
120; X64-AVX-LABEL: t5:
121; X64-AVX:       # %bb.0:
122; X64-AVX-NEXT:    vmovaps (%rdi), %xmm0
123; X64-AVX-NEXT:    vmovhps %xmm0, (%rsi)
124; X64-AVX-NEXT:    retq
125  %vecload = load volatile <2 x double>, <2 x double>* %a0, align 16
126  %vecext = extractelement <2 x double> %vecload, i32 1
127  store volatile double %vecext, double* %a1, align 8
128  ret void
129}
130
131; Check for multiuse.
132define float @t6(<8 x float> *%a0) {
133; X32-SSE2-LABEL: t6:
134; X32-SSE2:       # %bb.0:
135; X32-SSE2-NEXT:    pushl %eax
136; X32-SSE2-NEXT:    .cfi_def_cfa_offset 8
137; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
138; X32-SSE2-NEXT:    movaps (%eax), %xmm0
139; X32-SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
140; X32-SSE2-NEXT:    xorps %xmm1, %xmm1
141; X32-SSE2-NEXT:    cmpeqss %xmm0, %xmm1
142; X32-SSE2-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
143; X32-SSE2-NEXT:    andps %xmm1, %xmm2
144; X32-SSE2-NEXT:    andnps %xmm0, %xmm1
145; X32-SSE2-NEXT:    orps %xmm2, %xmm1
146; X32-SSE2-NEXT:    movss %xmm1, (%esp)
147; X32-SSE2-NEXT:    flds (%esp)
148; X32-SSE2-NEXT:    popl %eax
149; X32-SSE2-NEXT:    .cfi_def_cfa_offset 4
150; X32-SSE2-NEXT:    retl
151;
152; X64-SSSE3-LABEL: t6:
153; X64-SSSE3:       # %bb.0:
154; X64-SSSE3-NEXT:    movshdup {{.*#+}} xmm1 = mem[1,1,3,3]
155; X64-SSSE3-NEXT:    xorps %xmm0, %xmm0
156; X64-SSSE3-NEXT:    cmpeqss %xmm1, %xmm0
157; X64-SSSE3-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
158; X64-SSSE3-NEXT:    andps %xmm0, %xmm2
159; X64-SSSE3-NEXT:    andnps %xmm1, %xmm0
160; X64-SSSE3-NEXT:    orps %xmm2, %xmm0
161; X64-SSSE3-NEXT:    retq
162;
163; X64-AVX-LABEL: t6:
164; X64-AVX:       # %bb.0:
165; X64-AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
166; X64-AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
167; X64-AVX-NEXT:    vcmpeqss %xmm1, %xmm0, %xmm1
168; X64-AVX-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
169; X64-AVX-NEXT:    vblendvps %xmm1, %xmm2, %xmm0, %xmm0
170; X64-AVX-NEXT:    retq
171  %vecload = load <8 x float>, <8 x float>* %a0, align 32
172  %vecext = extractelement <8 x float> %vecload, i32 1
173  %cmp = fcmp oeq float %vecext, 0.000000e+00
174  %cond = select i1 %cmp, float 1.000000e+00, float %vecext
175  ret float %cond
176}
177
178define void @PR43971(<8 x float> *%a0, float *%a1) {
179; X32-SSE2-LABEL: PR43971:
180; X32-SSE2:       # %bb.0: # %entry
181; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
182; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
183; X32-SSE2-NEXT:    movaps 16(%ecx), %xmm0
184; X32-SSE2-NEXT:    movhlps {{.*#+}} xmm0 = xmm0[1,1]
185; X32-SSE2-NEXT:    xorps %xmm1, %xmm1
186; X32-SSE2-NEXT:    cmpltss %xmm0, %xmm1
187; X32-SSE2-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
188; X32-SSE2-NEXT:    andps %xmm1, %xmm2
189; X32-SSE2-NEXT:    andnps %xmm0, %xmm1
190; X32-SSE2-NEXT:    orps %xmm2, %xmm1
191; X32-SSE2-NEXT:    movss %xmm1, (%eax)
192; X32-SSE2-NEXT:    retl
193;
194; X64-SSSE3-LABEL: PR43971:
195; X64-SSSE3:       # %bb.0: # %entry
196; X64-SSSE3-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
197; X64-SSSE3-NEXT:    xorps %xmm1, %xmm1
198; X64-SSSE3-NEXT:    cmpltss %xmm0, %xmm1
199; X64-SSSE3-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
200; X64-SSSE3-NEXT:    andps %xmm1, %xmm2
201; X64-SSSE3-NEXT:    andnps %xmm0, %xmm1
202; X64-SSSE3-NEXT:    orps %xmm2, %xmm1
203; X64-SSSE3-NEXT:    movss %xmm1, (%rsi)
204; X64-SSSE3-NEXT:    retq
205;
206; X64-AVX-LABEL: PR43971:
207; X64-AVX:       # %bb.0: # %entry
208; X64-AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
209; X64-AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
210; X64-AVX-NEXT:    vcmpltss %xmm0, %xmm1, %xmm1
211; X64-AVX-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
212; X64-AVX-NEXT:    vblendvps %xmm1, %xmm2, %xmm0, %xmm0
213; X64-AVX-NEXT:    vmovss %xmm0, (%rsi)
214; X64-AVX-NEXT:    retq
215entry:
216  %0 = load <8 x float>, <8 x float>* %a0, align 32
217  %vecext = extractelement <8 x float> %0, i32 6
218  %cmp = fcmp ogt float %vecext, 0.000000e+00
219  %1 = load float, float* %a1, align 4
220  %cond = select i1 %cmp, float %1, float %vecext
221  store float %cond, float* %a1, align 4
222  ret void
223}
224
225define float @PR43971_1(<8 x float> *%a0) nounwind {
226; X32-SSE2-LABEL: PR43971_1:
227; X32-SSE2:       # %bb.0: # %entry
228; X32-SSE2-NEXT:    pushl %eax
229; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
230; X32-SSE2-NEXT:    movaps (%eax), %xmm0
231; X32-SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
232; X32-SSE2-NEXT:    xorps %xmm1, %xmm1
233; X32-SSE2-NEXT:    cmpeqss %xmm0, %xmm1
234; X32-SSE2-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
235; X32-SSE2-NEXT:    andps %xmm1, %xmm2
236; X32-SSE2-NEXT:    andnps %xmm0, %xmm1
237; X32-SSE2-NEXT:    orps %xmm2, %xmm1
238; X32-SSE2-NEXT:    movss %xmm1, (%esp)
239; X32-SSE2-NEXT:    flds (%esp)
240; X32-SSE2-NEXT:    popl %eax
241; X32-SSE2-NEXT:    retl
242;
243; X64-SSSE3-LABEL: PR43971_1:
244; X64-SSSE3:       # %bb.0: # %entry
245; X64-SSSE3-NEXT:    movshdup {{.*#+}} xmm1 = mem[1,1,3,3]
246; X64-SSSE3-NEXT:    xorps %xmm0, %xmm0
247; X64-SSSE3-NEXT:    cmpeqss %xmm1, %xmm0
248; X64-SSSE3-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
249; X64-SSSE3-NEXT:    andps %xmm0, %xmm2
250; X64-SSSE3-NEXT:    andnps %xmm1, %xmm0
251; X64-SSSE3-NEXT:    orps %xmm2, %xmm0
252; X64-SSSE3-NEXT:    retq
253;
254; X64-AVX-LABEL: PR43971_1:
255; X64-AVX:       # %bb.0: # %entry
256; X64-AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
257; X64-AVX-NEXT:    vxorps %xmm1, %xmm1, %xmm1
258; X64-AVX-NEXT:    vcmpeqss %xmm1, %xmm0, %xmm1
259; X64-AVX-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
260; X64-AVX-NEXT:    vblendvps %xmm1, %xmm2, %xmm0, %xmm0
261; X64-AVX-NEXT:    retq
262entry:
263  %0 = load <8 x float>, <8 x float>* %a0, align 32
264  %vecext = extractelement <8 x float> %0, i32 1
265  %cmp = fcmp oeq float %vecext, 0.000000e+00
266  %cond = select i1 %cmp, float 1.000000e+00, float %vecext
267  ret float %cond
268}
269
270; Test for bad extractions from a VBROADCAST_LOAD of the <2 x i16> non-uniform constant bitcast as <4 x i32>.
271define void @subextract_broadcast_load_constant(<2 x i16>* nocapture %0, i16* nocapture %1, i16* nocapture %2) nounwind {
272; X32-SSE2-LABEL: subextract_broadcast_load_constant:
273; X32-SSE2:       # %bb.0:
274; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
275; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
276; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edx
277; X32-SSE2-NEXT:    movl $-1583308898, (%edx) # imm = 0xA1A09F9E
278; X32-SSE2-NEXT:    movw $-24674, (%ecx) # imm = 0x9F9E
279; X32-SSE2-NEXT:    movw $-24160, (%eax) # imm = 0xA1A0
280; X32-SSE2-NEXT:    retl
281;
282; X64-LABEL: subextract_broadcast_load_constant:
283; X64:       # %bb.0:
284; X64-NEXT:    movl $-1583308898, (%rdi) # imm = 0xA1A09F9E
285; X64-NEXT:    movw $-24674, (%rsi) # imm = 0x9F9E
286; X64-NEXT:    movw $-24160, (%rdx) # imm = 0xA1A0
287; X64-NEXT:    retq
288  %4 = bitcast <2 x i16>* %0 to i8*
289  store i8 -98, i8* %4, align 1
290  %5 = getelementptr inbounds i8, i8* %4, i64 1
291  store i8 -97, i8* %5, align 1
292  %6 = getelementptr inbounds i8, i8* %4, i64 2
293  store i8 -96, i8* %6, align 1
294  %7 = getelementptr inbounds i8, i8* %4, i64 3
295  store i8 -95, i8* %7, align 1
296  %8 = load <2 x i16>, <2 x i16>* %0, align 4
297  %9 = extractelement <2 x i16> %8, i32 0
298  store i16 %9, i16* %1, align 2
299  %10 = extractelement <2 x i16> %8, i32 1
300  store i16 %10, i16* %2, align 2
301  ret void
302}
303
304; A scalar load is favored over a XMM->GPR register transfer in this example.
305
306define i32 @multi_use_load_scalarization(<4 x i32>* %p) nounwind {
307; X32-SSE2-LABEL: multi_use_load_scalarization:
308; X32-SSE2:       # %bb.0:
309; X32-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
310; X32-SSE2-NEXT:    movl (%ecx), %eax
311; X32-SSE2-NEXT:    movdqu (%ecx), %xmm0
312; X32-SSE2-NEXT:    pcmpeqd %xmm1, %xmm1
313; X32-SSE2-NEXT:    psubd %xmm1, %xmm0
314; X32-SSE2-NEXT:    movdqa %xmm0, (%ecx)
315; X32-SSE2-NEXT:    retl
316;
317; X64-SSSE3-LABEL: multi_use_load_scalarization:
318; X64-SSSE3:       # %bb.0:
319; X64-SSSE3-NEXT:    movl (%rdi), %eax
320; X64-SSSE3-NEXT:    movdqu (%rdi), %xmm0
321; X64-SSSE3-NEXT:    pcmpeqd %xmm1, %xmm1
322; X64-SSSE3-NEXT:    psubd %xmm1, %xmm0
323; X64-SSSE3-NEXT:    movdqa %xmm0, (%rdi)
324; X64-SSSE3-NEXT:    retq
325;
326; X64-AVX-LABEL: multi_use_load_scalarization:
327; X64-AVX:       # %bb.0:
328; X64-AVX-NEXT:    movl (%rdi), %eax
329; X64-AVX-NEXT:    vmovdqu (%rdi), %xmm0
330; X64-AVX-NEXT:    vpcmpeqd %xmm1, %xmm1, %xmm1
331; X64-AVX-NEXT:    vpsubd %xmm1, %xmm0, %xmm0
332; X64-AVX-NEXT:    vmovdqa %xmm0, (%rdi)
333; X64-AVX-NEXT:    retq
334  %v = load <4 x i32>, <4 x i32>* %p, align 1
335  %v1 = add <4 x i32> %v, <i32 1, i32 1, i32 1, i32 1>
336  store <4 x i32> %v1, <4 x i32>* %p
337  %r = extractelement <4 x i32> %v, i64 0
338  ret i32 %r
339}
340
341; This test is reduced from a C source example that showed a miscompile:
342; https://github.com/llvm/llvm-project/issues/53695
343; The scalarized loads from 'zero' in the AVX asm must occur before
344; the vector store to 'zero' overwrites the values.
345; If compiled to a binary, this test should return 0 if correct.
346
347@n1 = local_unnamed_addr global <8 x i32> <i32 0, i32 42, i32 6, i32 0, i32 0, i32 0, i32 0, i32 0>, align 32
348@zero = internal unnamed_addr global <8 x i32> zeroinitializer, align 32
349
350define i32 @main() nounwind {
351; X32-SSE2-LABEL: main:
352; X32-SSE2:       # %bb.0:
353; X32-SSE2-NEXT:    pushl %ebp
354; X32-SSE2-NEXT:    movl %esp, %ebp
355; X32-SSE2-NEXT:    pushl %esi
356; X32-SSE2-NEXT:    andl $-32, %esp
357; X32-SSE2-NEXT:    subl $64, %esp
358; X32-SSE2-NEXT:    movdqa zero, %xmm0
359; X32-SSE2-NEXT:    movaps n1+16, %xmm1
360; X32-SSE2-NEXT:    movaps n1, %xmm2
361; X32-SSE2-NEXT:    movaps %xmm2, zero
362; X32-SSE2-NEXT:    movaps %xmm1, zero+16
363; X32-SSE2-NEXT:    movaps {{.*#+}} xmm1 = [2,2,2,2]
364; X32-SSE2-NEXT:    movaps %xmm1, {{[0-9]+}}(%esp)
365; X32-SSE2-NEXT:    movaps %xmm1, (%esp)
366; X32-SSE2-NEXT:    movdqa (%esp), %xmm1
367; X32-SSE2-NEXT:    movaps {{[0-9]+}}(%esp), %xmm2
368; X32-SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
369; X32-SSE2-NEXT:    movd %xmm2, %eax
370; X32-SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
371; X32-SSE2-NEXT:    movd %xmm2, %ecx
372; X32-SSE2-NEXT:    xorl %edx, %edx
373; X32-SSE2-NEXT:    divl %ecx
374; X32-SSE2-NEXT:    movl %eax, %ecx
375; X32-SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
376; X32-SSE2-NEXT:    movd %xmm0, %eax
377; X32-SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
378; X32-SSE2-NEXT:    movd %xmm0, %esi
379; X32-SSE2-NEXT:    xorl %edx, %edx
380; X32-SSE2-NEXT:    divl %esi
381; X32-SSE2-NEXT:    addl %ecx, %eax
382; X32-SSE2-NEXT:    leal -4(%ebp), %esp
383; X32-SSE2-NEXT:    popl %esi
384; X32-SSE2-NEXT:    popl %ebp
385; X32-SSE2-NEXT:    retl
386;
387; X64-SSSE3-LABEL: main:
388; X64-SSSE3:       # %bb.0:
389; X64-SSSE3-NEXT:    pushq %rbp
390; X64-SSSE3-NEXT:    movq %rsp, %rbp
391; X64-SSSE3-NEXT:    andq $-32, %rsp
392; X64-SSSE3-NEXT:    subq $64, %rsp
393; X64-SSSE3-NEXT:    movdqa zero(%rip), %xmm0
394; X64-SSSE3-NEXT:    movq n1@GOTPCREL(%rip), %rax
395; X64-SSSE3-NEXT:    movaps (%rax), %xmm1
396; X64-SSSE3-NEXT:    movaps 16(%rax), %xmm2
397; X64-SSSE3-NEXT:    movaps %xmm1, zero(%rip)
398; X64-SSSE3-NEXT:    movaps %xmm2, zero+16(%rip)
399; X64-SSSE3-NEXT:    movaps {{.*#+}} xmm1 = [2,2,2,2]
400; X64-SSSE3-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
401; X64-SSSE3-NEXT:    movaps %xmm1, (%rsp)
402; X64-SSSE3-NEXT:    movdqa (%rsp), %xmm1
403; X64-SSSE3-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm2
404; X64-SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
405; X64-SSSE3-NEXT:    movd %xmm2, %eax
406; X64-SSSE3-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
407; X64-SSSE3-NEXT:    movd %xmm2, %ecx
408; X64-SSSE3-NEXT:    xorl %edx, %edx
409; X64-SSSE3-NEXT:    divl %ecx
410; X64-SSSE3-NEXT:    movl %eax, %ecx
411; X64-SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
412; X64-SSSE3-NEXT:    movd %xmm0, %eax
413; X64-SSSE3-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
414; X64-SSSE3-NEXT:    movd %xmm0, %esi
415; X64-SSSE3-NEXT:    xorl %edx, %edx
416; X64-SSSE3-NEXT:    divl %esi
417; X64-SSSE3-NEXT:    addl %ecx, %eax
418; X64-SSSE3-NEXT:    movq %rbp, %rsp
419; X64-SSSE3-NEXT:    popq %rbp
420; X64-SSSE3-NEXT:    retq
421;
422; X64-AVX1-LABEL: main:
423; X64-AVX1:       # %bb.0:
424; X64-AVX1-NEXT:    pushq %rbp
425; X64-AVX1-NEXT:    movq %rsp, %rbp
426; X64-AVX1-NEXT:    andq $-32, %rsp
427; X64-AVX1-NEXT:    subq $64, %rsp
428; X64-AVX1-NEXT:    movq n1@GOTPCREL(%rip), %rax
429; X64-AVX1-NEXT:    vmovaps (%rax), %ymm0
430; X64-AVX1-NEXT:    movl zero+4(%rip), %ecx
431; X64-AVX1-NEXT:    movl zero+8(%rip), %eax
432; X64-AVX1-NEXT:    vmovaps %ymm0, zero(%rip)
433; X64-AVX1-NEXT:    vmovaps {{.*#+}} ymm0 = [2,2,2,2,2,2,2,2]
434; X64-AVX1-NEXT:    vmovaps %ymm0, (%rsp)
435; X64-AVX1-NEXT:    vmovaps (%rsp), %ymm0
436; X64-AVX1-NEXT:    vextractps $2, %xmm0, %esi
437; X64-AVX1-NEXT:    xorl %edx, %edx
438; X64-AVX1-NEXT:    divl %esi
439; X64-AVX1-NEXT:    movl %eax, %esi
440; X64-AVX1-NEXT:    vextractps $1, %xmm0, %edi
441; X64-AVX1-NEXT:    movl %ecx, %eax
442; X64-AVX1-NEXT:    xorl %edx, %edx
443; X64-AVX1-NEXT:    divl %edi
444; X64-AVX1-NEXT:    addl %esi, %eax
445; X64-AVX1-NEXT:    movq %rbp, %rsp
446; X64-AVX1-NEXT:    popq %rbp
447; X64-AVX1-NEXT:    vzeroupper
448; X64-AVX1-NEXT:    retq
449;
450; X64-AVX2-LABEL: main:
451; X64-AVX2:       # %bb.0:
452; X64-AVX2-NEXT:    pushq %rbp
453; X64-AVX2-NEXT:    movq %rsp, %rbp
454; X64-AVX2-NEXT:    andq $-32, %rsp
455; X64-AVX2-NEXT:    subq $64, %rsp
456; X64-AVX2-NEXT:    movq n1@GOTPCREL(%rip), %rax
457; X64-AVX2-NEXT:    vmovaps (%rax), %ymm0
458; X64-AVX2-NEXT:    movl zero+4(%rip), %ecx
459; X64-AVX2-NEXT:    movl zero+8(%rip), %eax
460; X64-AVX2-NEXT:    vmovaps %ymm0, zero(%rip)
461; X64-AVX2-NEXT:    vbroadcastss {{.*#+}} ymm0 = [2,2,2,2,2,2,2,2]
462; X64-AVX2-NEXT:    vmovaps %ymm0, (%rsp)
463; X64-AVX2-NEXT:    vmovaps (%rsp), %ymm0
464; X64-AVX2-NEXT:    vextractps $2, %xmm0, %esi
465; X64-AVX2-NEXT:    xorl %edx, %edx
466; X64-AVX2-NEXT:    divl %esi
467; X64-AVX2-NEXT:    movl %eax, %esi
468; X64-AVX2-NEXT:    vextractps $1, %xmm0, %edi
469; X64-AVX2-NEXT:    movl %ecx, %eax
470; X64-AVX2-NEXT:    xorl %edx, %edx
471; X64-AVX2-NEXT:    divl %edi
472; X64-AVX2-NEXT:    addl %esi, %eax
473; X64-AVX2-NEXT:    movq %rbp, %rsp
474; X64-AVX2-NEXT:    popq %rbp
475; X64-AVX2-NEXT:    vzeroupper
476; X64-AVX2-NEXT:    retq
477  %stackptr = alloca <8 x i32>, align 32
478  %z = load <8 x i32>, <8 x i32>* @zero, align 32
479  %t1 = load <8 x i32>, <8 x i32>* @n1, align 32
480  store <8 x i32> %t1, <8 x i32>* @zero, align 32
481  store volatile <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>, <8 x i32>* %stackptr, align 32
482  %stackload = load volatile <8 x i32>, <8 x i32>* %stackptr, align 32
483  %div = udiv <8 x i32> %z, %stackload
484  %e1 = extractelement <8 x i32> %div, i64 1
485  %e2 = extractelement <8 x i32> %div, i64 2
486  %r = add i32 %e1, %e2
487  ret i32 %r
488}
489