1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avxvnni | FileCheck %s --check-prefixes=ALL,AVXVNNI
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VNNI
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni -mattr=+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VLVNNI
5
6define i32 @mul_4xi8_zc_exceed(<4 x i8> %a, i32 %c) {
7; ALL-LABEL: mul_4xi8_zc_exceed:
8; ALL:       # %bb.0: # %entry
9; ALL-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
10; ALL-NEXT:    vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
11; ALL-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
12; ALL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
13; ALL-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
14; ALL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
15; ALL-NEXT:    vmovd %xmm0, %eax
16; ALL-NEXT:    addl %edi, %eax
17; ALL-NEXT:    retq
18entry:
19  %0 = zext <4 x i8> %a to <4 x i32>
20  %1 = mul nsw <4 x i32> %0, <i32 0, i32 1, i32 2, i32 128>
21  %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
22  %op.extra = add nsw i32 %2, %c
23  ret i32 %op.extra
24}
25
26define i32 @mul_4xi8_zc(<4 x i8> %a, i32 %c) {
27; AVXVNNI-LABEL: mul_4xi8_zc:
28; AVXVNNI:       # %bb.0: # %entry
29; AVXVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
30; AVXVNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
31; AVXVNNI-NEXT:    {vex} vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
32; AVXVNNI-NEXT:    vmovd %xmm1, %eax
33; AVXVNNI-NEXT:    addl %edi, %eax
34; AVXVNNI-NEXT:    retq
35;
36; AVX512VNNI-LABEL: mul_4xi8_zc:
37; AVX512VNNI:       # %bb.0: # %entry
38; AVX512VNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
39; AVX512VNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
40; AVX512VNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
41; AVX512VNNI-NEXT:    vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
42; AVX512VNNI-NEXT:    vmovd %xmm1, %eax
43; AVX512VNNI-NEXT:    addl %edi, %eax
44; AVX512VNNI-NEXT:    vzeroupper
45; AVX512VNNI-NEXT:    retq
46;
47; AVX512VLVNNI-LABEL: mul_4xi8_zc:
48; AVX512VLVNNI:       # %bb.0: # %entry
49; AVX512VLVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
50; AVX512VLVNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
51; AVX512VLVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
52; AVX512VLVNNI-NEXT:    vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
53; AVX512VLVNNI-NEXT:    vmovd %xmm1, %eax
54; AVX512VLVNNI-NEXT:    addl %edi, %eax
55; AVX512VLVNNI-NEXT:    retq
56entry:
57  %0 = zext <4 x i8> %a to <4 x i32>
58  %1 = mul nsw <4 x i32> %0, <i32 0, i32 1, i32 2, i32 127>
59  %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
60  %op.extra = add nsw i32 %2, %c
61  ret i32 %op.extra
62}
63
64define i32 @mul_4xi4_cz(<4 x i4> %a, i32 %c) {
65; AVXVNNI-LABEL: mul_4xi4_cz:
66; AVXVNNI:       # %bb.0: # %entry
67; AVXVNNI-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
68; AVXVNNI-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
69; AVXVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
70; AVXVNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
71; AVXVNNI-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,127,0,0,0,0,0,0,0,0,0,0,0,0]
72; AVXVNNI-NEXT:    {vex} vpdpbusd %xmm0, %xmm2, %xmm1
73; AVXVNNI-NEXT:    vmovd %xmm1, %eax
74; AVXVNNI-NEXT:    addl %edi, %eax
75; AVXVNNI-NEXT:    retq
76;
77; AVX512VNNI-LABEL: mul_4xi4_cz:
78; AVX512VNNI:       # %bb.0: # %entry
79; AVX512VNNI-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
80; AVX512VNNI-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
81; AVX512VNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
82; AVX512VNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
83; AVX512VNNI-NEXT:    vmovdqa {{.*#+}} xmm1 = [0,1,2,127,0,0,0,0,0,0,0,0,0,0,0,0]
84; AVX512VNNI-NEXT:    vpxor %xmm2, %xmm2, %xmm2
85; AVX512VNNI-NEXT:    vpdpbusd %zmm0, %zmm1, %zmm2
86; AVX512VNNI-NEXT:    vmovd %xmm2, %eax
87; AVX512VNNI-NEXT:    addl %edi, %eax
88; AVX512VNNI-NEXT:    vzeroupper
89; AVX512VNNI-NEXT:    retq
90;
91; AVX512VLVNNI-LABEL: mul_4xi4_cz:
92; AVX512VLVNNI:       # %bb.0: # %entry
93; AVX512VLVNNI-NEXT:    vpmovdb %xmm0, %xmm0
94; AVX512VLVNNI-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
95; AVX512VLVNNI-NEXT:    vmovdqa {{.*#+}} xmm1 = [0,1,2,127,0,0,0,0,0,0,0,0,0,0,0,0]
96; AVX512VLVNNI-NEXT:    vpxor %xmm2, %xmm2, %xmm2
97; AVX512VLVNNI-NEXT:    vpdpbusd %xmm0, %xmm1, %xmm2
98; AVX512VLVNNI-NEXT:    vmovd %xmm2, %eax
99; AVX512VLVNNI-NEXT:    addl %edi, %eax
100; AVX512VLVNNI-NEXT:    retq
101entry:
102  %0 = zext <4 x i4> %a to <4 x i32>
103  %1 = mul nsw <4 x i32> <i32 0, i32 1, i32 2, i32 127>, %0
104  %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
105  %op.extra = add nsw i32 %2, %c
106  ret i32 %op.extra
107}
108
109define i32 @mul_4xi8_cs(<4 x i8> %a, i32 %c) {
110; AVXVNNI-LABEL: mul_4xi8_cs:
111; AVXVNNI:       # %bb.0: # %entry
112; AVXVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
113; AVXVNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
114; AVXVNNI-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,1,2,255,0,0,0,0,0,0,0,0,0,0,0,0]
115; AVXVNNI-NEXT:    {vex} vpdpbusd %xmm0, %xmm2, %xmm1
116; AVXVNNI-NEXT:    vmovd %xmm1, %eax
117; AVXVNNI-NEXT:    addl %edi, %eax
118; AVXVNNI-NEXT:    retq
119;
120; AVX512VNNI-LABEL: mul_4xi8_cs:
121; AVX512VNNI:       # %bb.0: # %entry
122; AVX512VNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
123; AVX512VNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
124; AVX512VNNI-NEXT:    vmovdqa {{.*#+}} xmm1 = [0,1,2,255,0,0,0,0,0,0,0,0,0,0,0,0]
125; AVX512VNNI-NEXT:    vpxor %xmm2, %xmm2, %xmm2
126; AVX512VNNI-NEXT:    vpdpbusd %zmm0, %zmm1, %zmm2
127; AVX512VNNI-NEXT:    vmovd %xmm2, %eax
128; AVX512VNNI-NEXT:    addl %edi, %eax
129; AVX512VNNI-NEXT:    vzeroupper
130; AVX512VNNI-NEXT:    retq
131;
132; AVX512VLVNNI-LABEL: mul_4xi8_cs:
133; AVX512VLVNNI:       # %bb.0: # %entry
134; AVX512VLVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
135; AVX512VLVNNI-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
136; AVX512VLVNNI-NEXT:    vmovdqa {{.*#+}} xmm1 = [0,1,2,255,0,0,0,0,0,0,0,0,0,0,0,0]
137; AVX512VLVNNI-NEXT:    vpxor %xmm2, %xmm2, %xmm2
138; AVX512VLVNNI-NEXT:    vpdpbusd %xmm0, %xmm1, %xmm2
139; AVX512VLVNNI-NEXT:    vmovd %xmm2, %eax
140; AVX512VLVNNI-NEXT:    addl %edi, %eax
141; AVX512VLVNNI-NEXT:    retq
142entry:
143  %0 = sext <4 x i8> %a to <4 x i32>
144  %1 = mul nsw <4 x i32> <i32 0, i32 1, i32 2, i32 255>, %0
145  %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
146  %op.extra = add nsw i32 %2, %c
147  ret i32 %op.extra
148}
149
150define i32 @mul_4xi8_cs_exceed(<4 x i8> %a, i32 %c) {
151; ALL-LABEL: mul_4xi8_cs_exceed:
152; ALL:       # %bb.0: # %entry
153; ALL-NEXT:    vpmovsxbd %xmm0, %xmm0
154; ALL-NEXT:    vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
155; ALL-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
156; ALL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
157; ALL-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
158; ALL-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
159; ALL-NEXT:    vmovd %xmm0, %eax
160; ALL-NEXT:    addl %edi, %eax
161; ALL-NEXT:    retq
162entry:
163  %0 = sext <4 x i8> %a to <4 x i32>
164  %1 = mul nsw <4 x i32> <i32 0, i32 1, i32 2, i32 256>, %0
165  %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
166  %op.extra = add nsw i32 %2, %c
167  ret i32 %op.extra
168}
169
170define i32 @mul_16xi8_zc(<16 x i8> %a, i32 %c) {
171; AVXVNNI-LABEL: mul_16xi8_zc:
172; AVXVNNI:       # %bb.0: # %entry
173; AVXVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
174; AVXVNNI-NEXT:    {vex} vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
175; AVXVNNI-NEXT:    vpshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
176; AVXVNNI-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
177; AVXVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
178; AVXVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
179; AVXVNNI-NEXT:    vmovd %xmm0, %eax
180; AVXVNNI-NEXT:    addl %edi, %eax
181; AVXVNNI-NEXT:    retq
182;
183; AVX512VNNI-LABEL: mul_16xi8_zc:
184; AVX512VNNI:       # %bb.0: # %entry
185; AVX512VNNI-NEXT:    vmovdqa %xmm0, %xmm0
186; AVX512VNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
187; AVX512VNNI-NEXT:    vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
188; AVX512VNNI-NEXT:    vpshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
189; AVX512VNNI-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
190; AVX512VNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
191; AVX512VNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
192; AVX512VNNI-NEXT:    vmovd %xmm0, %eax
193; AVX512VNNI-NEXT:    addl %edi, %eax
194; AVX512VNNI-NEXT:    vzeroupper
195; AVX512VNNI-NEXT:    retq
196;
197; AVX512VLVNNI-LABEL: mul_16xi8_zc:
198; AVX512VLVNNI:       # %bb.0: # %entry
199; AVX512VLVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
200; AVX512VLVNNI-NEXT:    vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
201; AVX512VLVNNI-NEXT:    vpshufd {{.*#+}} xmm0 = xmm1[2,3,2,3]
202; AVX512VLVNNI-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
203; AVX512VLVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
204; AVX512VLVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
205; AVX512VLVNNI-NEXT:    vmovd %xmm0, %eax
206; AVX512VLVNNI-NEXT:    addl %edi, %eax
207; AVX512VLVNNI-NEXT:    retq
208entry:
209  %0 = zext <16 x i8> %a to <16 x i32>
210  %1 = mul nsw <16 x i32> %0, <i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64>
211  %2 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %1)
212  %op.extra = add nsw i32 %2, %c
213  ret i32 %op.extra
214}
215
216define i32 @mul_32xi8_zc(<32 x i8> %a, i32 %c) {
217; AVXVNNI-LABEL: mul_32xi8_zc:
218; AVXVNNI:       # %bb.0: # %entry
219; AVXVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
220; AVXVNNI-NEXT:    {vex} vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
221; AVXVNNI-NEXT:    vextracti128 $1, %ymm1, %xmm0
222; AVXVNNI-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
223; AVXVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
224; AVXVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
225; AVXVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
226; AVXVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
227; AVXVNNI-NEXT:    vmovd %xmm0, %eax
228; AVXVNNI-NEXT:    addl %edi, %eax
229; AVXVNNI-NEXT:    vzeroupper
230; AVXVNNI-NEXT:    retq
231;
232; AVX512VNNI-LABEL: mul_32xi8_zc:
233; AVX512VNNI:       # %bb.0: # %entry
234; AVX512VNNI-NEXT:    vmovdqa %ymm0, %ymm0
235; AVX512VNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
236; AVX512VNNI-NEXT:    vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
237; AVX512VNNI-NEXT:    vextracti128 $1, %ymm1, %xmm0
238; AVX512VNNI-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
239; AVX512VNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
240; AVX512VNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
241; AVX512VNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
242; AVX512VNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
243; AVX512VNNI-NEXT:    vmovd %xmm0, %eax
244; AVX512VNNI-NEXT:    addl %edi, %eax
245; AVX512VNNI-NEXT:    vzeroupper
246; AVX512VNNI-NEXT:    retq
247;
248; AVX512VLVNNI-LABEL: mul_32xi8_zc:
249; AVX512VLVNNI:       # %bb.0: # %entry
250; AVX512VLVNNI-NEXT:    vpxor %xmm1, %xmm1, %xmm1
251; AVX512VLVNNI-NEXT:    vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
252; AVX512VLVNNI-NEXT:    vextracti128 $1, %ymm1, %xmm0
253; AVX512VLVNNI-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
254; AVX512VLVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
255; AVX512VLVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
256; AVX512VLVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
257; AVX512VLVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
258; AVX512VLVNNI-NEXT:    vmovd %xmm0, %eax
259; AVX512VLVNNI-NEXT:    addl %edi, %eax
260; AVX512VLVNNI-NEXT:    vzeroupper
261; AVX512VLVNNI-NEXT:    retq
262entry:
263  %0 = zext <32 x i8> %a to <32 x i32>
264  %1 = mul nsw <32 x i32> %0, <i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64>
265  %2 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %1)
266  %op.extra = add nsw i32 %2, %c
267  ret i32 %op.extra
268}
269
270define i32 @mul_64xi8_zc(<64 x i8> %a, i32 %c) {
271; AVXVNNI-LABEL: mul_64xi8_zc:
272; AVXVNNI:       # %bb.0: # %entry
273; AVXVNNI-NEXT:    vpbroadcastd {{.*#+}} ymm2 = [1073873152,1073873152,1073873152,1073873152,1073873152,1073873152,1073873152,1073873152]
274; AVXVNNI-NEXT:    vpxor %xmm3, %xmm3, %xmm3
275; AVXVNNI-NEXT:    vpxor %xmm4, %xmm4, %xmm4
276; AVXVNNI-NEXT:    {vex} vpdpbusd %ymm2, %ymm1, %ymm4
277; AVXVNNI-NEXT:    {vex} vpdpbusd %ymm2, %ymm0, %ymm3
278; AVXVNNI-NEXT:    vpaddd %ymm4, %ymm3, %ymm0
279; AVXVNNI-NEXT:    vextracti128 $1, %ymm0, %xmm1
280; AVXVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
281; AVXVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
282; AVXVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
283; AVXVNNI-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
284; AVXVNNI-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
285; AVXVNNI-NEXT:    vmovd %xmm0, %eax
286; AVXVNNI-NEXT:    addl %edi, %eax
287; AVXVNNI-NEXT:    vzeroupper
288; AVXVNNI-NEXT:    retq
289;
290; AVX512-LABEL: mul_64xi8_zc:
291; AVX512:       # %bb.0: # %entry
292; AVX512-NEXT:    vpxor %xmm1, %xmm1, %xmm1
293; AVX512-NEXT:    vpdpbusd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
294; AVX512-NEXT:    vextracti64x4 $1, %zmm1, %ymm0
295; AVX512-NEXT:    vpaddd %zmm0, %zmm1, %zmm0
296; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm1
297; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
298; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
299; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
300; AVX512-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
301; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
302; AVX512-NEXT:    vmovd %xmm0, %eax
303; AVX512-NEXT:    addl %edi, %eax
304; AVX512-NEXT:    vzeroupper
305; AVX512-NEXT:    retq
306entry:
307  %0 = zext <64 x i8> %a to <64 x i32>
308  %1 = mul nsw <64 x i32> %0, <i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64>
309  %2 = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %1)
310  %op.extra = add nsw i32 %2, %c
311  ret i32 %op.extra
312}
313
314declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
315declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
316declare i32 @llvm.vector.reduce.add.v32i32(<32 x i32>)
317declare i32 @llvm.vector.reduce.add.v64i32(<64 x i32>)
318