1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
4
5; fold (sdiv undef, x) -> 0
6define <4 x i32> @combine_vec_sdiv_undef0(<4 x i32> %x) {
7; SSE-LABEL: combine_vec_sdiv_undef0:
8; SSE:       # BB#0:
9; SSE-NEXT:    retq
10;
11; AVX-LABEL: combine_vec_sdiv_undef0:
12; AVX:       # BB#0:
13; AVX-NEXT:    retq
14  %1 = sdiv <4 x i32> undef, %x
15  ret <4 x i32> %1
16}
17
18; fold (sdiv x, undef) -> undef
19define <4 x i32> @combine_vec_sdiv_undef1(<4 x i32> %x) {
20; SSE-LABEL: combine_vec_sdiv_undef1:
21; SSE:       # BB#0:
22; SSE-NEXT:    retq
23;
24; AVX-LABEL: combine_vec_sdiv_undef1:
25; AVX:       # BB#0:
26; AVX-NEXT:    retq
27  %1 = sdiv <4 x i32> %x, undef
28  ret <4 x i32> %1
29}
30
31; fold (sdiv x, 1) -> x
32define <4 x i32> @combine_vec_sdiv_by_one(<4 x i32> %x) {
33; SSE-LABEL: combine_vec_sdiv_by_one:
34; SSE:       # BB#0:
35; SSE-NEXT:    retq
36;
37; AVX-LABEL: combine_vec_sdiv_by_one:
38; AVX:       # BB#0:
39; AVX-NEXT:    retq
40  %1 = sdiv <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
41  ret <4 x i32> %1
42}
43
44; fold (sdiv x, -1) -> 0 - x
45define <4 x i32> @combine_vec_sdiv_by_negone(<4 x i32> %x) {
46; SSE-LABEL: combine_vec_sdiv_by_negone:
47; SSE:       # BB#0:
48; SSE-NEXT:    pxor %xmm1, %xmm1
49; SSE-NEXT:    psubd %xmm0, %xmm1
50; SSE-NEXT:    movdqa %xmm1, %xmm0
51; SSE-NEXT:    retq
52;
53; AVX-LABEL: combine_vec_sdiv_by_negone:
54; AVX:       # BB#0:
55; AVX-NEXT:    vpxor %xmm1, %xmm1, %xmm1
56; AVX-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
57; AVX-NEXT:    retq
58  %1 = sdiv <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
59  ret <4 x i32> %1
60}
61
62; fold (sdiv x, y) -> (udiv x, y) iff x and y are positive
63define <4 x i32> @combine_vec_sdiv_by_pos0(<4 x i32> %x) {
64; SSE-LABEL: combine_vec_sdiv_by_pos0:
65; SSE:       # BB#0:
66; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
67; SSE-NEXT:    psrld $2, %xmm0
68; SSE-NEXT:    retq
69;
70; AVX-LABEL: combine_vec_sdiv_by_pos0:
71; AVX:       # BB#0:
72; AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
73; AVX-NEXT:    vpsrld $2, %xmm0, %xmm0
74; AVX-NEXT:    retq
75  %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
76  %2 = sdiv <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
77  ret <4 x i32> %2
78}
79
80define <4 x i32> @combine_vec_sdiv_by_pos1(<4 x i32> %x) {
81; SSE-LABEL: combine_vec_sdiv_by_pos1:
82; SSE:       # BB#0:
83; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
84; SSE-NEXT:    pextrd $1, %xmm0, %eax
85; SSE-NEXT:    shrl $2, %eax
86; SSE-NEXT:    pextrd $2, %xmm0, %ecx
87; SSE-NEXT:    pextrd $3, %xmm0, %edx
88; SSE-NEXT:    pinsrd $1, %eax, %xmm0
89; SSE-NEXT:    shrl $3, %ecx
90; SSE-NEXT:    pinsrd $2, %ecx, %xmm0
91; SSE-NEXT:    shrl $4, %edx
92; SSE-NEXT:    pinsrd $3, %edx, %xmm0
93; SSE-NEXT:    retq
94;
95; AVX-LABEL: combine_vec_sdiv_by_pos1:
96; AVX:       # BB#0:
97; AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
98; AVX-NEXT:    vpextrd $1, %xmm0, %eax
99; AVX-NEXT:    shrl $2, %eax
100; AVX-NEXT:    vpinsrd $1, %eax, %xmm0, %xmm1
101; AVX-NEXT:    vpextrd $2, %xmm0, %eax
102; AVX-NEXT:    shrl $3, %eax
103; AVX-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
104; AVX-NEXT:    vpextrd $3, %xmm0, %eax
105; AVX-NEXT:    shrl $4, %eax
106; AVX-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
107; AVX-NEXT:    retq
108  %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
109  %2 = sdiv <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>
110  ret <4 x i32> %2
111}
112
113; fold (sdiv x, (1 << c)) -> x >>u c
114define <4 x i32> @combine_vec_sdiv_by_pow2a(<4 x i32> %x) {
115; SSE-LABEL: combine_vec_sdiv_by_pow2a:
116; SSE:       # BB#0:
117; SSE-NEXT:    movdqa %xmm0, %xmm1
118; SSE-NEXT:    psrad $31, %xmm1
119; SSE-NEXT:    psrld $30, %xmm1
120; SSE-NEXT:    paddd %xmm0, %xmm1
121; SSE-NEXT:    psrad $2, %xmm1
122; SSE-NEXT:    movdqa %xmm1, %xmm0
123; SSE-NEXT:    retq
124;
125; AVX-LABEL: combine_vec_sdiv_by_pow2a:
126; AVX:       # BB#0:
127; AVX-NEXT:    vpsrad $31, %xmm0, %xmm1
128; AVX-NEXT:    vpsrld $30, %xmm1, %xmm1
129; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
130; AVX-NEXT:    vpsrad $2, %xmm0, %xmm0
131; AVX-NEXT:    retq
132  %1 = sdiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
133  ret <4 x i32> %1
134}
135
136define <4 x i32> @combine_vec_sdiv_by_pow2b(<4 x i32> %x) {
137; SSE-LABEL: combine_vec_sdiv_by_pow2b:
138; SSE:       # BB#0:
139; SSE-NEXT:    pextrd $1, %xmm0, %eax
140; SSE-NEXT:    movl %eax, %ecx
141; SSE-NEXT:    sarl $31, %ecx
142; SSE-NEXT:    shrl $30, %ecx
143; SSE-NEXT:    addl %eax, %ecx
144; SSE-NEXT:    sarl $2, %ecx
145; SSE-NEXT:    pextrd $2, %xmm0, %eax
146; SSE-NEXT:    pextrd $3, %xmm0, %edx
147; SSE-NEXT:    pinsrd $1, %ecx, %xmm0
148; SSE-NEXT:    movl %eax, %ecx
149; SSE-NEXT:    sarl $31, %ecx
150; SSE-NEXT:    shrl $29, %ecx
151; SSE-NEXT:    addl %eax, %ecx
152; SSE-NEXT:    sarl $3, %ecx
153; SSE-NEXT:    pinsrd $2, %ecx, %xmm0
154; SSE-NEXT:    movl %edx, %eax
155; SSE-NEXT:    sarl $31, %eax
156; SSE-NEXT:    shrl $28, %eax
157; SSE-NEXT:    addl %edx, %eax
158; SSE-NEXT:    sarl $4, %eax
159; SSE-NEXT:    pinsrd $3, %eax, %xmm0
160; SSE-NEXT:    retq
161;
162; AVX-LABEL: combine_vec_sdiv_by_pow2b:
163; AVX:       # BB#0:
164; AVX-NEXT:    vpextrd $1, %xmm0, %eax
165; AVX-NEXT:    movl %eax, %ecx
166; AVX-NEXT:    sarl $31, %ecx
167; AVX-NEXT:    shrl $30, %ecx
168; AVX-NEXT:    addl %eax, %ecx
169; AVX-NEXT:    sarl $2, %ecx
170; AVX-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm1
171; AVX-NEXT:    vpextrd $2, %xmm0, %eax
172; AVX-NEXT:    movl %eax, %ecx
173; AVX-NEXT:    sarl $31, %ecx
174; AVX-NEXT:    shrl $29, %ecx
175; AVX-NEXT:    addl %eax, %ecx
176; AVX-NEXT:    sarl $3, %ecx
177; AVX-NEXT:    vpinsrd $2, %ecx, %xmm1, %xmm1
178; AVX-NEXT:    vpextrd $3, %xmm0, %eax
179; AVX-NEXT:    movl %eax, %ecx
180; AVX-NEXT:    sarl $31, %ecx
181; AVX-NEXT:    shrl $28, %ecx
182; AVX-NEXT:    addl %eax, %ecx
183; AVX-NEXT:    sarl $4, %ecx
184; AVX-NEXT:    vpinsrd $3, %ecx, %xmm1, %xmm0
185; AVX-NEXT:    retq
186  %1 = sdiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
187  ret <4 x i32> %1
188}
189