1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s 3 4define i32 @or_self(i32 %x) { 5; CHECK-LABEL: or_self: 6; CHECK: # BB#0: 7; CHECK-NEXT: movl %edi, %eax 8; CHECK-NEXT: retq 9 %or = or i32 %x, %x 10 ret i32 %or 11} 12 13define <4 x i32> @or_self_vec(<4 x i32> %x) { 14; CHECK-LABEL: or_self_vec: 15; CHECK: # BB#0: 16; CHECK-NEXT: retq 17 %or = or <4 x i32> %x, %x 18 ret <4 x i32> %or 19} 20 21; Verify that each of the following test cases is folded into a single 22; instruction which performs a blend operation. 23 24define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) { 25; CHECK-LABEL: test1: 26; CHECK: # BB#0: 27; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] 28; CHECK-NEXT: retq 29 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2> 30 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1> 31 %or = or <2 x i64> %shuf1, %shuf2 32 ret <2 x i64> %or 33} 34 35 36define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) { 37; CHECK-LABEL: test2: 38; CHECK: # BB#0: 39; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 40; CHECK-NEXT: retq 41 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3> 42 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4> 43 %or = or <4 x i32> %shuf1, %shuf2 44 ret <4 x i32> %or 45} 46 47 48define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) { 49; CHECK-LABEL: test3: 50; CHECK: # BB#0: 51; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 52; CHECK-NEXT: retq 53 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1> 54 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2> 55 %or = or <2 x i64> %shuf1, %shuf2 56 ret <2 x i64> %or 57} 58 59 60define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) { 61; CHECK-LABEL: test4: 62; CHECK: # BB#0: 63; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] 64; CHECK-NEXT: retq 65 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4> 66 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3> 67 %or = or <4 x i32> %shuf1, %shuf2 68 ret <4 x i32> %or 69} 70 71 72define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) { 73; CHECK-LABEL: test5: 74; CHECK: # BB#0: 75; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7] 76; CHECK-NEXT: retq 77 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3> 78 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4> 79 %or = or <4 x i32> %shuf1, %shuf2 80 ret <4 x i32> %or 81} 82 83 84define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) { 85; CHECK-LABEL: test6: 86; CHECK: # BB#0: 87; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] 88; CHECK-NEXT: retq 89 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4> 90 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3> 91 %or = or <4 x i32> %shuf1, %shuf2 92 ret <4 x i32> %or 93} 94 95 96define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) { 97; CHECK-LABEL: test7: 98; CHECK: # BB#0: 99; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] 100; CHECK-NEXT: retq 101 %and1 = and <4 x i32> %a, <i32 -1, i32 -1, i32 0, i32 0> 102 %and2 = and <4 x i32> %b, <i32 0, i32 0, i32 -1, i32 -1> 103 %or = or <4 x i32> %and1, %and2 104 ret <4 x i32> %or 105} 106 107 108define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) { 109; CHECK-LABEL: test8: 110; CHECK: # BB#0: 111; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] 112; CHECK-NEXT: retq 113 %and1 = and <2 x i64> %a, <i64 -1, i64 0> 114 %and2 = and <2 x i64> %b, <i64 0, i64 -1> 115 %or = or <2 x i64> %and1, %and2 116 ret <2 x i64> %or 117} 118 119 120define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) { 121; CHECK-LABEL: test9: 122; CHECK: # BB#0: 123; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 124; CHECK-NEXT: retq 125 %and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1> 126 %and2 = and <4 x i32> %b, <i32 -1, i32 -1, i32 0, i32 0> 127 %or = or <4 x i32> %and1, %and2 128 ret <4 x i32> %or 129} 130 131 132define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) { 133; CHECK-LABEL: test10: 134; CHECK: # BB#0: 135; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 136; CHECK-NEXT: retq 137 %and1 = and <2 x i64> %a, <i64 0, i64 -1> 138 %and2 = and <2 x i64> %b, <i64 -1, i64 0> 139 %or = or <2 x i64> %and1, %and2 140 ret <2 x i64> %or 141} 142 143 144define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) { 145; CHECK-LABEL: test11: 146; CHECK: # BB#0: 147; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] 148; CHECK-NEXT: retq 149 %and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0> 150 %and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 -1> 151 %or = or <4 x i32> %and1, %and2 152 ret <4 x i32> %or 153} 154 155 156define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) { 157; CHECK-LABEL: test12: 158; CHECK: # BB#0: 159; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7] 160; CHECK-NEXT: retq 161 %and1 = and <4 x i32> %a, <i32 0, i32 -1, i32 -1, i32 -1> 162 %and2 = and <4 x i32> %b, <i32 -1, i32 0, i32 0, i32 0> 163 %or = or <4 x i32> %and1, %and2 164 ret <4 x i32> %or 165} 166 167 168; Verify that the following test cases are folded into single shuffles. 169 170define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) { 171; CHECK-LABEL: test13: 172; CHECK: # BB#0: 173; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 174; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] 175; CHECK-NEXT: retq 176 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 1, i32 1, i32 4, i32 4> 177 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3> 178 %or = or <4 x i32> %shuf1, %shuf2 179 ret <4 x i32> %or 180} 181 182 183define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) { 184; CHECK-LABEL: test14: 185; CHECK: # BB#0: 186; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 187; CHECK-NEXT: retq 188 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2> 189 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0> 190 %or = or <2 x i64> %shuf1, %shuf2 191 ret <2 x i64> %or 192} 193 194 195define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) { 196; CHECK-LABEL: test15: 197; CHECK: # BB#0: 198; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,2,1] 199; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,1,2,3] 200; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] 201; CHECK-NEXT: retq 202 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 1> 203 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 2, i32 1, i32 4, i32 4> 204 %or = or <4 x i32> %shuf1, %shuf2 205 ret <4 x i32> %or 206} 207 208 209define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) { 210; CHECK-LABEL: test16: 211; CHECK: # BB#0: 212; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] 213; CHECK-NEXT: movdqa %xmm1, %xmm0 214; CHECK-NEXT: retq 215 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0> 216 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2> 217 %or = or <2 x i64> %shuf1, %shuf2 218 ret <2 x i64> %or 219} 220 221 222; Verify that the dag-combiner does not fold a OR of two shuffles into a single 223; shuffle instruction when the shuffle indexes are not compatible. 224 225define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) { 226; CHECK-LABEL: test17: 227; CHECK: # BB#0: 228; CHECK-NEXT: psllq $32, %xmm0 229; CHECK-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero 230; CHECK-NEXT: por %xmm1, %xmm0 231; CHECK-NEXT: retq 232 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 2> 233 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4> 234 %or = or <4 x i32> %shuf1, %shuf2 235 ret <4 x i32> %or 236} 237 238 239define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) { 240; CHECK-LABEL: test18: 241; CHECK: # BB#0: 242; CHECK-NEXT: pxor %xmm2, %xmm2 243; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7] 244; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1] 245; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] 246; CHECK-NEXT: por %xmm1, %xmm0 247; CHECK-NEXT: retq 248 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4> 249 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4> 250 %or = or <4 x i32> %shuf1, %shuf2 251 ret <4 x i32> %or 252} 253 254 255define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) { 256; CHECK-LABEL: test19: 257; CHECK: # BB#0: 258; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,3] 259; CHECK-NEXT: pxor %xmm3, %xmm3 260; CHECK-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] 261; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2] 262; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5,6,7] 263; CHECK-NEXT: por %xmm2, %xmm0 264; CHECK-NEXT: retq 265 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3> 266 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2> 267 %or = or <4 x i32> %shuf1, %shuf2 268 ret <4 x i32> %or 269} 270 271 272define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) { 273; CHECK-LABEL: test20: 274; CHECK: # BB#0: 275; CHECK-NEXT: por %xmm1, %xmm0 276; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero 277; CHECK-NEXT: retq 278 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2> 279 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2> 280 %or = or <2 x i64> %shuf1, %shuf2 281 ret <2 x i64> %or 282} 283 284 285define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) { 286; CHECK-LABEL: test21: 287; CHECK: # BB#0: 288; CHECK-NEXT: por %xmm1, %xmm0 289; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] 290; CHECK-NEXT: retq 291 %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0> 292 %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 0> 293 %or = or <2 x i64> %shuf1, %shuf2 294 ret <2 x i64> %or 295} 296 297 298; Verify that the dag-combiner keeps the correct domain for float/double vectors 299; bitcast to use the mask-or blend combine. 300 301define <2 x double> @test22(<2 x double> %a0, <2 x double> %a1) { 302; CHECK-LABEL: test22: 303; CHECK: # BB#0: 304; CHECK-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1] 305; CHECK-NEXT: retq 306 %bc1 = bitcast <2 x double> %a0 to <2 x i64> 307 %bc2 = bitcast <2 x double> %a1 to <2 x i64> 308 %and1 = and <2 x i64> %bc1, <i64 0, i64 -1> 309 %and2 = and <2 x i64> %bc2, <i64 -1, i64 0> 310 %or = or <2 x i64> %and1, %and2 311 %bc3 = bitcast <2 x i64> %or to <2 x double> 312 ret <2 x double> %bc3 313} 314 315 316define <4 x float> @test23(<4 x float> %a0, <4 x float> %a1) { 317; CHECK-LABEL: test23: 318; CHECK: # BB#0: 319; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] 320; CHECK-NEXT: retq 321 %bc1 = bitcast <4 x float> %a0 to <4 x i32> 322 %bc2 = bitcast <4 x float> %a1 to <4 x i32> 323 %and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0> 324 %and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1> 325 %or = or <4 x i32> %and1, %and2 326 %bc3 = bitcast <4 x i32> %or to <4 x float> 327 ret <4 x float> %bc3 328} 329 330 331define <4 x float> @test24(<4 x float> %a0, <4 x float> %a1) { 332; CHECK-LABEL: test24: 333; CHECK: # BB#0: 334; CHECK-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1] 335; CHECK-NEXT: retq 336 %bc1 = bitcast <4 x float> %a0 to <2 x i64> 337 %bc2 = bitcast <4 x float> %a1 to <2 x i64> 338 %and1 = and <2 x i64> %bc1, <i64 0, i64 -1> 339 %and2 = and <2 x i64> %bc2, <i64 -1, i64 0> 340 %or = or <2 x i64> %and1, %and2 341 %bc3 = bitcast <2 x i64> %or to <4 x float> 342 ret <4 x float> %bc3 343} 344 345 346define <4 x float> @test25(<4 x float> %a0) { 347; CHECK-LABEL: test25: 348; CHECK: # BB#0: 349; CHECK-NEXT: blendps {{.*#+}} xmm0 = mem[0],xmm0[1,2],mem[3] 350; CHECK-NEXT: retq 351 %bc1 = bitcast <4 x float> %a0 to <4 x i32> 352 %bc2 = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <4 x i32> 353 %and1 = and <4 x i32> %bc1, <i32 0, i32 -1, i32 -1, i32 0> 354 %and2 = and <4 x i32> %bc2, <i32 -1, i32 0, i32 0, i32 -1> 355 %or = or <4 x i32> %and1, %and2 356 %bc3 = bitcast <4 x i32> %or to <4 x float> 357 ret <4 x float> %bc3 358} 359 360 361; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle 362; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to 363; handle legal vector value types. 364define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) { 365; CHECK-LABEL: test_crash: 366; CHECK: # BB#0: 367; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 368; CHECK-NEXT: retq 369 %shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3> 370 %shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4> 371 %or = or <4 x i8> %shuf1, %shuf2 372 ret <4 x i8> %or 373} 374 375; Verify that we can fold regardless of which operand is the zeroinitializer 376 377define <4 x i32> @test2b(<4 x i32> %a, <4 x i32> %b) { 378; CHECK-LABEL: test2b: 379; CHECK: # BB#0: 380; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 381; CHECK-NEXT: retq 382 %shuf1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32><i32 0, i32 0, i32 6, i32 7> 383 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4> 384 %or = or <4 x i32> %shuf1, %shuf2 385 ret <4 x i32> %or 386} 387 388define <4 x i32> @test2c(<4 x i32> %a, <4 x i32> %b) { 389; CHECK-LABEL: test2c: 390; CHECK: # BB#0: 391; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 392; CHECK-NEXT: retq 393 %shuf1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32><i32 0, i32 0, i32 6, i32 7> 394 %shuf2 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %b, <4 x i32><i32 4, i32 5, i32 0, i32 0> 395 %or = or <4 x i32> %shuf1, %shuf2 396 ret <4 x i32> %or 397} 398 399 400define <4 x i32> @test2d(<4 x i32> %a, <4 x i32> %b) { 401; CHECK-LABEL: test2d: 402; CHECK: # BB#0: 403; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 404; CHECK-NEXT: retq 405 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3> 406 %shuf2 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %b, <4 x i32><i32 4, i32 5, i32 0, i32 0> 407 %or = or <4 x i32> %shuf1, %shuf2 408 ret <4 x i32> %or 409} 410 411; Make sure we can have an undef where an index pointing to the zero vector should be 412 413define <4 x i32> @test2e(<4 x i32> %a, <4 x i32> %b) { 414; CHECK-LABEL: test2e: 415; CHECK: # BB#0: 416; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 417; CHECK-NEXT: retq 418 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>, <4 x i32><i32 undef, i32 4, i32 2, i32 3> 419 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>, <4 x i32><i32 0, i32 1, i32 4, i32 4> 420 %or = or <4 x i32> %shuf1, %shuf2 421 ret <4 x i32> %or 422} 423 424define <4 x i32> @test2f(<4 x i32> %a, <4 x i32> %b) { 425; CHECK-LABEL: test2f: 426; CHECK: # BB#0: 427; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 428; CHECK-NEXT: retq 429 %shuf1 = shufflevector <4 x i32> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>, <4 x i32><i32 4, i32 4, i32 2, i32 3> 430 %shuf2 = shufflevector <4 x i32> %b, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>, <4 x i32><i32 undef, i32 1, i32 4, i32 4> 431 %or = or <4 x i32> %shuf1, %shuf2 432 ret <4 x i32> %or 433} 434 435; (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 436 437define <2 x i64> @or_and_v2i64(<2 x i64> %a0) { 438; CHECK-LABEL: or_and_v2i64: 439; CHECK: # BB#0: 440; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 441; CHECK-NEXT: orps {{.*}}(%rip), %xmm0 442; CHECK-NEXT: retq 443 %1 = and <2 x i64> %a0, <i64 1, i64 1> 444 %2 = or <2 x i64> %1, <i64 3, i64 3> 445 ret <2 x i64> %2 446} 447 448define <4 x i32> @or_and_v4i32(<4 x i32> %a0) { 449; CHECK-LABEL: or_and_v4i32: 450; CHECK: # BB#0: 451; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 452; CHECK-NEXT: orps {{.*}}(%rip), %xmm0 453; CHECK-NEXT: retq 454 %1 = and <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1> 455 %2 = or <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3> 456 ret <4 x i32> %2 457} 458 459; fold (or x, c) -> c iff (x & ~c) == 0 460 461define <2 x i64> @or_zext_v2i32(<2 x i32> %a0) { 462; CHECK-LABEL: or_zext_v2i32: 463; CHECK: # BB#0: 464; CHECK-NEXT: pxor %xmm1, %xmm1 465; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 466; CHECK-NEXT: por {{.*}}(%rip), %xmm0 467; CHECK-NEXT: retq 468 %1 = zext <2 x i32> %a0 to <2 x i64> 469 %2 = or <2 x i64> %1, <i64 4294967295, i64 4294967295> 470 ret <2 x i64> %2 471} 472 473define <4 x i32> @or_zext_v4i16(<4 x i16> %a0) { 474; CHECK-LABEL: or_zext_v4i16: 475; CHECK: # BB#0: 476; CHECK-NEXT: pxor %xmm1, %xmm1 477; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 478; CHECK-NEXT: por {{.*}}(%rip), %xmm0 479; CHECK-NEXT: retq 480 %1 = zext <4 x i16> %a0 to <4 x i32> 481 %2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535> 482 ret <4 x i32> %2 483} 484 485