1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 5 6; 7; PR6455 'Clear Upper Bits' Patterns 8; 9 10define <2 x i64> @_clearupper2xi64a(<2 x i64>) nounwind { 11; SSE-LABEL: _clearupper2xi64a: 12; SSE: # BB#0: 13; SSE-NEXT: andps {{.*}}(%rip), %xmm0 14; SSE-NEXT: retq 15; 16; AVX1-LABEL: _clearupper2xi64a: 17; AVX1: # BB#0: 18; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 19; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 20; AVX1-NEXT: retq 21; 22; AVX2-LABEL: _clearupper2xi64a: 23; AVX2: # BB#0: 24; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1 25; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 26; AVX2-NEXT: retq 27 %x0 = extractelement <2 x i64> %0, i32 0 28 %x1 = extractelement <2 x i64> %0, i32 1 29 %trunc0 = trunc i64 %x0 to i32 30 %trunc1 = trunc i64 %x1 to i32 31 %ext0 = zext i32 %trunc0 to i64 32 %ext1 = zext i32 %trunc1 to i64 33 %v0 = insertelement <2 x i64> undef, i64 %ext0, i32 0 34 %v1 = insertelement <2 x i64> %v0, i64 %ext1, i32 1 35 ret <2 x i64> %v1 36} 37 38define <4 x i64> @_clearupper4xi64a(<4 x i64>) nounwind { 39; SSE-LABEL: _clearupper4xi64a: 40; SSE: # BB#0: 41; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,4294967295] 42; SSE-NEXT: andps %xmm2, %xmm0 43; SSE-NEXT: andps %xmm2, %xmm1 44; SSE-NEXT: retq 45; 46; AVX-LABEL: _clearupper4xi64a: 47; AVX: # BB#0: 48; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 49; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 50; AVX-NEXT: retq 51 %x0 = extractelement <4 x i64> %0, i32 0 52 %x1 = extractelement <4 x i64> %0, i32 1 53 %x2 = extractelement <4 x i64> %0, i32 2 54 %x3 = extractelement <4 x i64> %0, i32 3 55 %trunc0 = trunc i64 %x0 to i32 56 %trunc1 = trunc i64 %x1 to i32 57 %trunc2 = trunc i64 %x2 to i32 58 %trunc3 = trunc i64 %x3 to i32 59 %ext0 = zext i32 %trunc0 to i64 60 %ext1 = zext i32 %trunc1 to i64 61 %ext2 = zext i32 %trunc2 to i64 62 %ext3 = zext i32 %trunc3 to i64 63 %v0 = insertelement <4 x i64> undef, i64 %ext0, i32 0 64 %v1 = insertelement <4 x i64> %v0, i64 %ext1, i32 1 65 %v2 = insertelement <4 x i64> %v1, i64 %ext2, i32 2 66 %v3 = insertelement <4 x i64> %v2, i64 %ext3, i32 3 67 ret <4 x i64> %v3 68} 69 70define <4 x i32> @_clearupper4xi32a(<4 x i32>) nounwind { 71; SSE-LABEL: _clearupper4xi32a: 72; SSE: # BB#0: 73; SSE-NEXT: andps {{.*}}(%rip), %xmm0 74; SSE-NEXT: retq 75; 76; AVX-LABEL: _clearupper4xi32a: 77; AVX: # BB#0: 78; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 79; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 80; AVX-NEXT: retq 81 %x0 = extractelement <4 x i32> %0, i32 0 82 %x1 = extractelement <4 x i32> %0, i32 1 83 %x2 = extractelement <4 x i32> %0, i32 2 84 %x3 = extractelement <4 x i32> %0, i32 3 85 %trunc0 = trunc i32 %x0 to i16 86 %trunc1 = trunc i32 %x1 to i16 87 %trunc2 = trunc i32 %x2 to i16 88 %trunc3 = trunc i32 %x3 to i16 89 %ext0 = zext i16 %trunc0 to i32 90 %ext1 = zext i16 %trunc1 to i32 91 %ext2 = zext i16 %trunc2 to i32 92 %ext3 = zext i16 %trunc3 to i32 93 %v0 = insertelement <4 x i32> undef, i32 %ext0, i32 0 94 %v1 = insertelement <4 x i32> %v0, i32 %ext1, i32 1 95 %v2 = insertelement <4 x i32> %v1, i32 %ext2, i32 2 96 %v3 = insertelement <4 x i32> %v2, i32 %ext3, i32 3 97 ret <4 x i32> %v3 98} 99 100define <8 x i32> @_clearupper8xi32a(<8 x i32>) nounwind { 101; SSE-LABEL: _clearupper8xi32a: 102; SSE: # BB#0: 103; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,65535,65535,65535] 104; SSE-NEXT: andps %xmm2, %xmm0 105; SSE-NEXT: andps %xmm2, %xmm1 106; SSE-NEXT: retq 107; 108; AVX1-LABEL: _clearupper8xi32a: 109; AVX1: # BB#0: 110; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 111; AVX1-NEXT: retq 112; 113; AVX2-LABEL: _clearupper8xi32a: 114; AVX2: # BB#0: 115; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 116; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] 117; AVX2-NEXT: retq 118 %x0 = extractelement <8 x i32> %0, i32 0 119 %x1 = extractelement <8 x i32> %0, i32 1 120 %x2 = extractelement <8 x i32> %0, i32 2 121 %x3 = extractelement <8 x i32> %0, i32 3 122 %x4 = extractelement <8 x i32> %0, i32 4 123 %x5 = extractelement <8 x i32> %0, i32 5 124 %x6 = extractelement <8 x i32> %0, i32 6 125 %x7 = extractelement <8 x i32> %0, i32 7 126 %trunc0 = trunc i32 %x0 to i16 127 %trunc1 = trunc i32 %x1 to i16 128 %trunc2 = trunc i32 %x2 to i16 129 %trunc3 = trunc i32 %x3 to i16 130 %trunc4 = trunc i32 %x4 to i16 131 %trunc5 = trunc i32 %x5 to i16 132 %trunc6 = trunc i32 %x6 to i16 133 %trunc7 = trunc i32 %x7 to i16 134 %ext0 = zext i16 %trunc0 to i32 135 %ext1 = zext i16 %trunc1 to i32 136 %ext2 = zext i16 %trunc2 to i32 137 %ext3 = zext i16 %trunc3 to i32 138 %ext4 = zext i16 %trunc4 to i32 139 %ext5 = zext i16 %trunc5 to i32 140 %ext6 = zext i16 %trunc6 to i32 141 %ext7 = zext i16 %trunc7 to i32 142 %v0 = insertelement <8 x i32> undef, i32 %ext0, i32 0 143 %v1 = insertelement <8 x i32> %v0, i32 %ext1, i32 1 144 %v2 = insertelement <8 x i32> %v1, i32 %ext2, i32 2 145 %v3 = insertelement <8 x i32> %v2, i32 %ext3, i32 3 146 %v4 = insertelement <8 x i32> %v3, i32 %ext4, i32 4 147 %v5 = insertelement <8 x i32> %v4, i32 %ext5, i32 5 148 %v6 = insertelement <8 x i32> %v5, i32 %ext6, i32 6 149 %v7 = insertelement <8 x i32> %v6, i32 %ext7, i32 7 150 ret <8 x i32> %v7 151} 152 153define <8 x i16> @_clearupper8xi16a(<8 x i16>) nounwind { 154; SSE-LABEL: _clearupper8xi16a: 155; SSE: # BB#0: 156; SSE-NEXT: andps {{.*}}(%rip), %xmm0 157; SSE-NEXT: retq 158; 159; AVX-LABEL: _clearupper8xi16a: 160; AVX: # BB#0: 161; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 162; AVX-NEXT: retq 163 %x0 = extractelement <8 x i16> %0, i32 0 164 %x1 = extractelement <8 x i16> %0, i32 1 165 %x2 = extractelement <8 x i16> %0, i32 2 166 %x3 = extractelement <8 x i16> %0, i32 3 167 %x4 = extractelement <8 x i16> %0, i32 4 168 %x5 = extractelement <8 x i16> %0, i32 5 169 %x6 = extractelement <8 x i16> %0, i32 6 170 %x7 = extractelement <8 x i16> %0, i32 7 171 %trunc0 = trunc i16 %x0 to i8 172 %trunc1 = trunc i16 %x1 to i8 173 %trunc2 = trunc i16 %x2 to i8 174 %trunc3 = trunc i16 %x3 to i8 175 %trunc4 = trunc i16 %x4 to i8 176 %trunc5 = trunc i16 %x5 to i8 177 %trunc6 = trunc i16 %x6 to i8 178 %trunc7 = trunc i16 %x7 to i8 179 %ext0 = zext i8 %trunc0 to i16 180 %ext1 = zext i8 %trunc1 to i16 181 %ext2 = zext i8 %trunc2 to i16 182 %ext3 = zext i8 %trunc3 to i16 183 %ext4 = zext i8 %trunc4 to i16 184 %ext5 = zext i8 %trunc5 to i16 185 %ext6 = zext i8 %trunc6 to i16 186 %ext7 = zext i8 %trunc7 to i16 187 %v0 = insertelement <8 x i16> undef, i16 %ext0, i32 0 188 %v1 = insertelement <8 x i16> %v0, i16 %ext1, i32 1 189 %v2 = insertelement <8 x i16> %v1, i16 %ext2, i32 2 190 %v3 = insertelement <8 x i16> %v2, i16 %ext3, i32 3 191 %v4 = insertelement <8 x i16> %v3, i16 %ext4, i32 4 192 %v5 = insertelement <8 x i16> %v4, i16 %ext5, i32 5 193 %v6 = insertelement <8 x i16> %v5, i16 %ext6, i32 6 194 %v7 = insertelement <8 x i16> %v6, i16 %ext7, i32 7 195 ret <8 x i16> %v7 196} 197 198define <16 x i16> @_clearupper16xi16a(<16 x i16>) nounwind { 199; SSE-LABEL: _clearupper16xi16a: 200; SSE: # BB#0: 201; SSE-NEXT: movaps {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] 202; SSE-NEXT: andps %xmm2, %xmm0 203; SSE-NEXT: andps %xmm2, %xmm1 204; SSE-NEXT: retq 205; 206; AVX-LABEL: _clearupper16xi16a: 207; AVX: # BB#0: 208; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 209; AVX-NEXT: retq 210 %x0 = extractelement <16 x i16> %0, i32 0 211 %x1 = extractelement <16 x i16> %0, i32 1 212 %x2 = extractelement <16 x i16> %0, i32 2 213 %x3 = extractelement <16 x i16> %0, i32 3 214 %x4 = extractelement <16 x i16> %0, i32 4 215 %x5 = extractelement <16 x i16> %0, i32 5 216 %x6 = extractelement <16 x i16> %0, i32 6 217 %x7 = extractelement <16 x i16> %0, i32 7 218 %x8 = extractelement <16 x i16> %0, i32 8 219 %x9 = extractelement <16 x i16> %0, i32 9 220 %x10 = extractelement <16 x i16> %0, i32 10 221 %x11 = extractelement <16 x i16> %0, i32 11 222 %x12 = extractelement <16 x i16> %0, i32 12 223 %x13 = extractelement <16 x i16> %0, i32 13 224 %x14 = extractelement <16 x i16> %0, i32 14 225 %x15 = extractelement <16 x i16> %0, i32 15 226 %trunc0 = trunc i16 %x0 to i8 227 %trunc1 = trunc i16 %x1 to i8 228 %trunc2 = trunc i16 %x2 to i8 229 %trunc3 = trunc i16 %x3 to i8 230 %trunc4 = trunc i16 %x4 to i8 231 %trunc5 = trunc i16 %x5 to i8 232 %trunc6 = trunc i16 %x6 to i8 233 %trunc7 = trunc i16 %x7 to i8 234 %trunc8 = trunc i16 %x8 to i8 235 %trunc9 = trunc i16 %x9 to i8 236 %trunc10 = trunc i16 %x10 to i8 237 %trunc11 = trunc i16 %x11 to i8 238 %trunc12 = trunc i16 %x12 to i8 239 %trunc13 = trunc i16 %x13 to i8 240 %trunc14 = trunc i16 %x14 to i8 241 %trunc15 = trunc i16 %x15 to i8 242 %ext0 = zext i8 %trunc0 to i16 243 %ext1 = zext i8 %trunc1 to i16 244 %ext2 = zext i8 %trunc2 to i16 245 %ext3 = zext i8 %trunc3 to i16 246 %ext4 = zext i8 %trunc4 to i16 247 %ext5 = zext i8 %trunc5 to i16 248 %ext6 = zext i8 %trunc6 to i16 249 %ext7 = zext i8 %trunc7 to i16 250 %ext8 = zext i8 %trunc8 to i16 251 %ext9 = zext i8 %trunc9 to i16 252 %ext10 = zext i8 %trunc10 to i16 253 %ext11 = zext i8 %trunc11 to i16 254 %ext12 = zext i8 %trunc12 to i16 255 %ext13 = zext i8 %trunc13 to i16 256 %ext14 = zext i8 %trunc14 to i16 257 %ext15 = zext i8 %trunc15 to i16 258 %v0 = insertelement <16 x i16> undef, i16 %ext0, i32 0 259 %v1 = insertelement <16 x i16> %v0, i16 %ext1, i32 1 260 %v2 = insertelement <16 x i16> %v1, i16 %ext2, i32 2 261 %v3 = insertelement <16 x i16> %v2, i16 %ext3, i32 3 262 %v4 = insertelement <16 x i16> %v3, i16 %ext4, i32 4 263 %v5 = insertelement <16 x i16> %v4, i16 %ext5, i32 5 264 %v6 = insertelement <16 x i16> %v5, i16 %ext6, i32 6 265 %v7 = insertelement <16 x i16> %v6, i16 %ext7, i32 7 266 %v8 = insertelement <16 x i16> %v7, i16 %ext8, i32 8 267 %v9 = insertelement <16 x i16> %v8, i16 %ext9, i32 9 268 %v10 = insertelement <16 x i16> %v9, i16 %ext10, i32 10 269 %v11 = insertelement <16 x i16> %v10, i16 %ext11, i32 11 270 %v12 = insertelement <16 x i16> %v11, i16 %ext12, i32 12 271 %v13 = insertelement <16 x i16> %v12, i16 %ext13, i32 13 272 %v14 = insertelement <16 x i16> %v13, i16 %ext14, i32 14 273 %v15 = insertelement <16 x i16> %v14, i16 %ext15, i32 15 274 ret <16 x i16> %v15 275} 276 277define <16 x i8> @_clearupper16xi8a(<16 x i8>) nounwind { 278; SSE-LABEL: _clearupper16xi8a: 279; SSE: # BB#0: 280; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) 281; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 282; SSE-NEXT: movd %eax, %xmm0 283; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 284; SSE-NEXT: movd %eax, %xmm1 285; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 286; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 287; SSE-NEXT: movd %eax, %xmm0 288; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero 289; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 290; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 291; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 292; SSE-NEXT: movd %eax, %xmm0 293; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 294; SSE-NEXT: movd %eax, %xmm3 295; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 296; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 297; SSE-NEXT: movd %eax, %xmm0 298; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 299; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 300; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3] 301; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] 302; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 303; SSE-NEXT: movd %eax, %xmm0 304; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 305; SSE-NEXT: movd %eax, %xmm2 306; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 307; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 308; SSE-NEXT: movd %eax, %xmm0 309; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero 310; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 311; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] 312; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 313; SSE-NEXT: movd %eax, %xmm0 314; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 315; SSE-NEXT: movd %eax, %xmm2 316; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 317; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 318; SSE-NEXT: movd %eax, %xmm4 319; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 320; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] 321; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] 322; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] 323; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 324; SSE-NEXT: pand {{.*}}(%rip), %xmm0 325; SSE-NEXT: retq 326; 327; AVX-LABEL: _clearupper16xi8a: 328; AVX: # BB#0: 329; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 330; AVX-NEXT: retq 331 %x0 = extractelement <16 x i8> %0, i32 0 332 %x1 = extractelement <16 x i8> %0, i32 1 333 %x2 = extractelement <16 x i8> %0, i32 2 334 %x3 = extractelement <16 x i8> %0, i32 3 335 %x4 = extractelement <16 x i8> %0, i32 4 336 %x5 = extractelement <16 x i8> %0, i32 5 337 %x6 = extractelement <16 x i8> %0, i32 6 338 %x7 = extractelement <16 x i8> %0, i32 7 339 %x8 = extractelement <16 x i8> %0, i32 8 340 %x9 = extractelement <16 x i8> %0, i32 9 341 %x10 = extractelement <16 x i8> %0, i32 10 342 %x11 = extractelement <16 x i8> %0, i32 11 343 %x12 = extractelement <16 x i8> %0, i32 12 344 %x13 = extractelement <16 x i8> %0, i32 13 345 %x14 = extractelement <16 x i8> %0, i32 14 346 %x15 = extractelement <16 x i8> %0, i32 15 347 %trunc0 = trunc i8 %x0 to i4 348 %trunc1 = trunc i8 %x1 to i4 349 %trunc2 = trunc i8 %x2 to i4 350 %trunc3 = trunc i8 %x3 to i4 351 %trunc4 = trunc i8 %x4 to i4 352 %trunc5 = trunc i8 %x5 to i4 353 %trunc6 = trunc i8 %x6 to i4 354 %trunc7 = trunc i8 %x7 to i4 355 %trunc8 = trunc i8 %x8 to i4 356 %trunc9 = trunc i8 %x9 to i4 357 %trunc10 = trunc i8 %x10 to i4 358 %trunc11 = trunc i8 %x11 to i4 359 %trunc12 = trunc i8 %x12 to i4 360 %trunc13 = trunc i8 %x13 to i4 361 %trunc14 = trunc i8 %x14 to i4 362 %trunc15 = trunc i8 %x15 to i4 363 %ext0 = zext i4 %trunc0 to i8 364 %ext1 = zext i4 %trunc1 to i8 365 %ext2 = zext i4 %trunc2 to i8 366 %ext3 = zext i4 %trunc3 to i8 367 %ext4 = zext i4 %trunc4 to i8 368 %ext5 = zext i4 %trunc5 to i8 369 %ext6 = zext i4 %trunc6 to i8 370 %ext7 = zext i4 %trunc7 to i8 371 %ext8 = zext i4 %trunc8 to i8 372 %ext9 = zext i4 %trunc9 to i8 373 %ext10 = zext i4 %trunc10 to i8 374 %ext11 = zext i4 %trunc11 to i8 375 %ext12 = zext i4 %trunc12 to i8 376 %ext13 = zext i4 %trunc13 to i8 377 %ext14 = zext i4 %trunc14 to i8 378 %ext15 = zext i4 %trunc15 to i8 379 %v0 = insertelement <16 x i8> undef, i8 %ext0, i32 0 380 %v1 = insertelement <16 x i8> %v0, i8 %ext1, i32 1 381 %v2 = insertelement <16 x i8> %v1, i8 %ext2, i32 2 382 %v3 = insertelement <16 x i8> %v2, i8 %ext3, i32 3 383 %v4 = insertelement <16 x i8> %v3, i8 %ext4, i32 4 384 %v5 = insertelement <16 x i8> %v4, i8 %ext5, i32 5 385 %v6 = insertelement <16 x i8> %v5, i8 %ext6, i32 6 386 %v7 = insertelement <16 x i8> %v6, i8 %ext7, i32 7 387 %v8 = insertelement <16 x i8> %v7, i8 %ext8, i32 8 388 %v9 = insertelement <16 x i8> %v8, i8 %ext9, i32 9 389 %v10 = insertelement <16 x i8> %v9, i8 %ext10, i32 10 390 %v11 = insertelement <16 x i8> %v10, i8 %ext11, i32 11 391 %v12 = insertelement <16 x i8> %v11, i8 %ext12, i32 12 392 %v13 = insertelement <16 x i8> %v12, i8 %ext13, i32 13 393 %v14 = insertelement <16 x i8> %v13, i8 %ext14, i32 14 394 %v15 = insertelement <16 x i8> %v14, i8 %ext15, i32 15 395 ret <16 x i8> %v15 396} 397 398define <32 x i8> @_clearupper32xi8a(<32 x i8>) nounwind { 399; SSE-LABEL: _clearupper32xi8a: 400; SSE: # BB#0: 401; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) 402; SSE-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) 403; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 404; SSE-NEXT: movd %eax, %xmm0 405; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 406; SSE-NEXT: movd %eax, %xmm1 407; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 408; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 409; SSE-NEXT: movd %eax, %xmm0 410; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero 411; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 412; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 413; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 414; SSE-NEXT: movd %eax, %xmm0 415; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 416; SSE-NEXT: movd %eax, %xmm3 417; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 418; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 419; SSE-NEXT: movd %eax, %xmm0 420; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 421; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 422; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3] 423; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] 424; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 425; SSE-NEXT: movd %eax, %xmm0 426; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 427; SSE-NEXT: movd %eax, %xmm2 428; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 429; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 430; SSE-NEXT: movd %eax, %xmm0 431; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero 432; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 433; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] 434; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 435; SSE-NEXT: movd %eax, %xmm0 436; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 437; SSE-NEXT: movd %eax, %xmm2 438; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 439; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 440; SSE-NEXT: movd %eax, %xmm4 441; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 442; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] 443; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] 444; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] 445; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 446; SSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] 447; SSE-NEXT: pand %xmm2, %xmm0 448; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 449; SSE-NEXT: movd %eax, %xmm1 450; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 451; SSE-NEXT: movd %eax, %xmm3 452; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 453; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 454; SSE-NEXT: movd %eax, %xmm1 455; SSE-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero 456; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3],xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] 457; SSE-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] 458; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 459; SSE-NEXT: movd %eax, %xmm1 460; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 461; SSE-NEXT: movd %eax, %xmm5 462; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3],xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] 463; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 464; SSE-NEXT: movd %eax, %xmm1 465; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero 466; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 467; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3] 468; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] 469; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 470; SSE-NEXT: movd %eax, %xmm1 471; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 472; SSE-NEXT: movd %eax, %xmm4 473; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3],xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] 474; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 475; SSE-NEXT: movd %eax, %xmm1 476; SSE-NEXT: movd {{.*#+}} xmm5 = mem[0],zero,zero,zero 477; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3],xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] 478; SSE-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3] 479; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 480; SSE-NEXT: movd %eax, %xmm1 481; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 482; SSE-NEXT: movd %eax, %xmm4 483; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3],xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] 484; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 485; SSE-NEXT: movd %eax, %xmm6 486; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 487; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1],xmm1[2],xmm6[2],xmm1[3],xmm6[3],xmm1[4],xmm6[4],xmm1[5],xmm6[5],xmm1[6],xmm6[6],xmm1[7],xmm6[7] 488; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3] 489; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1] 490; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] 491; SSE-NEXT: pand %xmm2, %xmm1 492; SSE-NEXT: retq 493; 494; AVX-LABEL: _clearupper32xi8a: 495; AVX: # BB#0: 496; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 497; AVX-NEXT: retq 498 %x0 = extractelement <32 x i8> %0, i32 0 499 %x1 = extractelement <32 x i8> %0, i32 1 500 %x2 = extractelement <32 x i8> %0, i32 2 501 %x3 = extractelement <32 x i8> %0, i32 3 502 %x4 = extractelement <32 x i8> %0, i32 4 503 %x5 = extractelement <32 x i8> %0, i32 5 504 %x6 = extractelement <32 x i8> %0, i32 6 505 %x7 = extractelement <32 x i8> %0, i32 7 506 %x8 = extractelement <32 x i8> %0, i32 8 507 %x9 = extractelement <32 x i8> %0, i32 9 508 %x10 = extractelement <32 x i8> %0, i32 10 509 %x11 = extractelement <32 x i8> %0, i32 11 510 %x12 = extractelement <32 x i8> %0, i32 12 511 %x13 = extractelement <32 x i8> %0, i32 13 512 %x14 = extractelement <32 x i8> %0, i32 14 513 %x15 = extractelement <32 x i8> %0, i32 15 514 %x16 = extractelement <32 x i8> %0, i32 16 515 %x17 = extractelement <32 x i8> %0, i32 17 516 %x18 = extractelement <32 x i8> %0, i32 18 517 %x19 = extractelement <32 x i8> %0, i32 19 518 %x20 = extractelement <32 x i8> %0, i32 20 519 %x21 = extractelement <32 x i8> %0, i32 21 520 %x22 = extractelement <32 x i8> %0, i32 22 521 %x23 = extractelement <32 x i8> %0, i32 23 522 %x24 = extractelement <32 x i8> %0, i32 24 523 %x25 = extractelement <32 x i8> %0, i32 25 524 %x26 = extractelement <32 x i8> %0, i32 26 525 %x27 = extractelement <32 x i8> %0, i32 27 526 %x28 = extractelement <32 x i8> %0, i32 28 527 %x29 = extractelement <32 x i8> %0, i32 29 528 %x30 = extractelement <32 x i8> %0, i32 30 529 %x31 = extractelement <32 x i8> %0, i32 31 530 %trunc0 = trunc i8 %x0 to i4 531 %trunc1 = trunc i8 %x1 to i4 532 %trunc2 = trunc i8 %x2 to i4 533 %trunc3 = trunc i8 %x3 to i4 534 %trunc4 = trunc i8 %x4 to i4 535 %trunc5 = trunc i8 %x5 to i4 536 %trunc6 = trunc i8 %x6 to i4 537 %trunc7 = trunc i8 %x7 to i4 538 %trunc8 = trunc i8 %x8 to i4 539 %trunc9 = trunc i8 %x9 to i4 540 %trunc10 = trunc i8 %x10 to i4 541 %trunc11 = trunc i8 %x11 to i4 542 %trunc12 = trunc i8 %x12 to i4 543 %trunc13 = trunc i8 %x13 to i4 544 %trunc14 = trunc i8 %x14 to i4 545 %trunc15 = trunc i8 %x15 to i4 546 %trunc16 = trunc i8 %x16 to i4 547 %trunc17 = trunc i8 %x17 to i4 548 %trunc18 = trunc i8 %x18 to i4 549 %trunc19 = trunc i8 %x19 to i4 550 %trunc20 = trunc i8 %x20 to i4 551 %trunc21 = trunc i8 %x21 to i4 552 %trunc22 = trunc i8 %x22 to i4 553 %trunc23 = trunc i8 %x23 to i4 554 %trunc24 = trunc i8 %x24 to i4 555 %trunc25 = trunc i8 %x25 to i4 556 %trunc26 = trunc i8 %x26 to i4 557 %trunc27 = trunc i8 %x27 to i4 558 %trunc28 = trunc i8 %x28 to i4 559 %trunc29 = trunc i8 %x29 to i4 560 %trunc30 = trunc i8 %x30 to i4 561 %trunc31 = trunc i8 %x31 to i4 562 %ext0 = zext i4 %trunc0 to i8 563 %ext1 = zext i4 %trunc1 to i8 564 %ext2 = zext i4 %trunc2 to i8 565 %ext3 = zext i4 %trunc3 to i8 566 %ext4 = zext i4 %trunc4 to i8 567 %ext5 = zext i4 %trunc5 to i8 568 %ext6 = zext i4 %trunc6 to i8 569 %ext7 = zext i4 %trunc7 to i8 570 %ext8 = zext i4 %trunc8 to i8 571 %ext9 = zext i4 %trunc9 to i8 572 %ext10 = zext i4 %trunc10 to i8 573 %ext11 = zext i4 %trunc11 to i8 574 %ext12 = zext i4 %trunc12 to i8 575 %ext13 = zext i4 %trunc13 to i8 576 %ext14 = zext i4 %trunc14 to i8 577 %ext15 = zext i4 %trunc15 to i8 578 %ext16 = zext i4 %trunc16 to i8 579 %ext17 = zext i4 %trunc17 to i8 580 %ext18 = zext i4 %trunc18 to i8 581 %ext19 = zext i4 %trunc19 to i8 582 %ext20 = zext i4 %trunc20 to i8 583 %ext21 = zext i4 %trunc21 to i8 584 %ext22 = zext i4 %trunc22 to i8 585 %ext23 = zext i4 %trunc23 to i8 586 %ext24 = zext i4 %trunc24 to i8 587 %ext25 = zext i4 %trunc25 to i8 588 %ext26 = zext i4 %trunc26 to i8 589 %ext27 = zext i4 %trunc27 to i8 590 %ext28 = zext i4 %trunc28 to i8 591 %ext29 = zext i4 %trunc29 to i8 592 %ext30 = zext i4 %trunc30 to i8 593 %ext31 = zext i4 %trunc31 to i8 594 %v0 = insertelement <32 x i8> undef, i8 %ext0, i32 0 595 %v1 = insertelement <32 x i8> %v0, i8 %ext1, i32 1 596 %v2 = insertelement <32 x i8> %v1, i8 %ext2, i32 2 597 %v3 = insertelement <32 x i8> %v2, i8 %ext3, i32 3 598 %v4 = insertelement <32 x i8> %v3, i8 %ext4, i32 4 599 %v5 = insertelement <32 x i8> %v4, i8 %ext5, i32 5 600 %v6 = insertelement <32 x i8> %v5, i8 %ext6, i32 6 601 %v7 = insertelement <32 x i8> %v6, i8 %ext7, i32 7 602 %v8 = insertelement <32 x i8> %v7, i8 %ext8, i32 8 603 %v9 = insertelement <32 x i8> %v8, i8 %ext9, i32 9 604 %v10 = insertelement <32 x i8> %v9, i8 %ext10, i32 10 605 %v11 = insertelement <32 x i8> %v10, i8 %ext11, i32 11 606 %v12 = insertelement <32 x i8> %v11, i8 %ext12, i32 12 607 %v13 = insertelement <32 x i8> %v12, i8 %ext13, i32 13 608 %v14 = insertelement <32 x i8> %v13, i8 %ext14, i32 14 609 %v15 = insertelement <32 x i8> %v14, i8 %ext15, i32 15 610 %v16 = insertelement <32 x i8> %v15, i8 %ext16, i32 16 611 %v17 = insertelement <32 x i8> %v16, i8 %ext17, i32 17 612 %v18 = insertelement <32 x i8> %v17, i8 %ext18, i32 18 613 %v19 = insertelement <32 x i8> %v18, i8 %ext19, i32 19 614 %v20 = insertelement <32 x i8> %v19, i8 %ext20, i32 20 615 %v21 = insertelement <32 x i8> %v20, i8 %ext21, i32 21 616 %v22 = insertelement <32 x i8> %v21, i8 %ext22, i32 22 617 %v23 = insertelement <32 x i8> %v22, i8 %ext23, i32 23 618 %v24 = insertelement <32 x i8> %v23, i8 %ext24, i32 24 619 %v25 = insertelement <32 x i8> %v24, i8 %ext25, i32 25 620 %v26 = insertelement <32 x i8> %v25, i8 %ext26, i32 26 621 %v27 = insertelement <32 x i8> %v26, i8 %ext27, i32 27 622 %v28 = insertelement <32 x i8> %v27, i8 %ext28, i32 28 623 %v29 = insertelement <32 x i8> %v28, i8 %ext29, i32 29 624 %v30 = insertelement <32 x i8> %v29, i8 %ext30, i32 30 625 %v31 = insertelement <32 x i8> %v30, i8 %ext31, i32 31 626 ret <32 x i8> %v31 627} 628 629define <2 x i64> @_clearupper2xi64b(<2 x i64>) nounwind { 630; SSE-LABEL: _clearupper2xi64b: 631; SSE: # BB#0: 632; SSE-NEXT: andps {{.*}}(%rip), %xmm0 633; SSE-NEXT: retq 634; 635; AVX1-LABEL: _clearupper2xi64b: 636; AVX1: # BB#0: 637; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 638; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 639; AVX1-NEXT: retq 640; 641; AVX2-LABEL: _clearupper2xi64b: 642; AVX2: # BB#0: 643; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1 644; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 645; AVX2-NEXT: retq 646 %x32 = bitcast <2 x i64> %0 to <4 x i32> 647 %r0 = insertelement <4 x i32> %x32, i32 zeroinitializer, i32 1 648 %r1 = insertelement <4 x i32> %r0, i32 zeroinitializer, i32 3 649 %r = bitcast <4 x i32> %r1 to <2 x i64> 650 ret <2 x i64> %r 651} 652 653define <4 x i64> @_clearupper4xi64b(<4 x i64>) nounwind { 654; SSE-LABEL: _clearupper4xi64b: 655; SSE: # BB#0: 656; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0] 657; SSE-NEXT: andps %xmm2, %xmm0 658; SSE-NEXT: andps %xmm2, %xmm1 659; SSE-NEXT: retq 660; 661; AVX-LABEL: _clearupper4xi64b: 662; AVX: # BB#0: 663; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 664; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 665; AVX-NEXT: retq 666 %x32 = bitcast <4 x i64> %0 to <8 x i32> 667 %r0 = insertelement <8 x i32> %x32, i32 zeroinitializer, i32 1 668 %r1 = insertelement <8 x i32> %r0, i32 zeroinitializer, i32 3 669 %r2 = insertelement <8 x i32> %r1, i32 zeroinitializer, i32 5 670 %r3 = insertelement <8 x i32> %r2, i32 zeroinitializer, i32 7 671 %r = bitcast <8 x i32> %r3 to <4 x i64> 672 ret <4 x i64> %r 673} 674 675define <4 x i32> @_clearupper4xi32b(<4 x i32>) nounwind { 676; SSE-LABEL: _clearupper4xi32b: 677; SSE: # BB#0: 678; SSE-NEXT: andps {{.*}}(%rip), %xmm0 679; SSE-NEXT: retq 680; 681; AVX-LABEL: _clearupper4xi32b: 682; AVX: # BB#0: 683; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 684; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 685; AVX-NEXT: retq 686 %x16 = bitcast <4 x i32> %0 to <8 x i16> 687 %r0 = insertelement <8 x i16> %x16, i16 zeroinitializer, i32 1 688 %r1 = insertelement <8 x i16> %r0, i16 zeroinitializer, i32 3 689 %r2 = insertelement <8 x i16> %r1, i16 zeroinitializer, i32 5 690 %r3 = insertelement <8 x i16> %r2, i16 zeroinitializer, i32 7 691 %r = bitcast <8 x i16> %r3 to <4 x i32> 692 ret <4 x i32> %r 693} 694 695define <8 x i32> @_clearupper8xi32b(<8 x i32>) nounwind { 696; SSE-LABEL: _clearupper8xi32b: 697; SSE: # BB#0: 698; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,0,65535,0,65535,0] 699; SSE-NEXT: andps %xmm2, %xmm0 700; SSE-NEXT: andps %xmm2, %xmm1 701; SSE-NEXT: retq 702; 703; AVX1-LABEL: _clearupper8xi32b: 704; AVX1: # BB#0: 705; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 706; AVX1-NEXT: retq 707; 708; AVX2-LABEL: _clearupper8xi32b: 709; AVX2: # BB#0: 710; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 711; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] 712; AVX2-NEXT: retq 713 %x16 = bitcast <8 x i32> %0 to <16 x i16> 714 %r0 = insertelement <16 x i16> %x16, i16 zeroinitializer, i32 1 715 %r1 = insertelement <16 x i16> %r0, i16 zeroinitializer, i32 3 716 %r2 = insertelement <16 x i16> %r1, i16 zeroinitializer, i32 5 717 %r3 = insertelement <16 x i16> %r2, i16 zeroinitializer, i32 7 718 %r4 = insertelement <16 x i16> %r3, i16 zeroinitializer, i32 9 719 %r5 = insertelement <16 x i16> %r4, i16 zeroinitializer, i32 11 720 %r6 = insertelement <16 x i16> %r5, i16 zeroinitializer, i32 13 721 %r7 = insertelement <16 x i16> %r6, i16 zeroinitializer, i32 15 722 %r = bitcast <16 x i16> %r7 to <8 x i32> 723 ret <8 x i32> %r 724} 725 726define <8 x i16> @_clearupper8xi16b(<8 x i16>) nounwind { 727; SSE-LABEL: _clearupper8xi16b: 728; SSE: # BB#0: 729; SSE-NEXT: andps {{.*}}(%rip), %xmm0 730; SSE-NEXT: retq 731; 732; AVX-LABEL: _clearupper8xi16b: 733; AVX: # BB#0: 734; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 735; AVX-NEXT: retq 736 %x8 = bitcast <8 x i16> %0 to <16 x i8> 737 %r0 = insertelement <16 x i8> %x8, i8 zeroinitializer, i32 1 738 %r1 = insertelement <16 x i8> %r0, i8 zeroinitializer, i32 3 739 %r2 = insertelement <16 x i8> %r1, i8 zeroinitializer, i32 5 740 %r3 = insertelement <16 x i8> %r2, i8 zeroinitializer, i32 7 741 %r4 = insertelement <16 x i8> %r3, i8 zeroinitializer, i32 9 742 %r5 = insertelement <16 x i8> %r4, i8 zeroinitializer, i32 11 743 %r6 = insertelement <16 x i8> %r5, i8 zeroinitializer, i32 13 744 %r7 = insertelement <16 x i8> %r6, i8 zeroinitializer, i32 15 745 %r = bitcast <16 x i8> %r7 to <8 x i16> 746 ret <8 x i16> %r 747} 748 749define <16 x i16> @_clearupper16xi16b(<16 x i16>) nounwind { 750; SSE-LABEL: _clearupper16xi16b: 751; SSE: # BB#0: 752; SSE-NEXT: movaps {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] 753; SSE-NEXT: andps %xmm2, %xmm0 754; SSE-NEXT: andps %xmm2, %xmm1 755; SSE-NEXT: retq 756; 757; AVX-LABEL: _clearupper16xi16b: 758; AVX: # BB#0: 759; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] 760; AVX-NEXT: vandps %xmm1, %xmm0, %xmm2 761; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0 762; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0 763; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 764; AVX-NEXT: retq 765 %x8 = bitcast <16 x i16> %0 to <32 x i8> 766 %r0 = insertelement <32 x i8> %x8, i8 zeroinitializer, i32 1 767 %r1 = insertelement <32 x i8> %r0, i8 zeroinitializer, i32 3 768 %r2 = insertelement <32 x i8> %r1, i8 zeroinitializer, i32 5 769 %r3 = insertelement <32 x i8> %r2, i8 zeroinitializer, i32 7 770 %r4 = insertelement <32 x i8> %r3, i8 zeroinitializer, i32 9 771 %r5 = insertelement <32 x i8> %r4, i8 zeroinitializer, i32 11 772 %r6 = insertelement <32 x i8> %r5, i8 zeroinitializer, i32 13 773 %r7 = insertelement <32 x i8> %r6, i8 zeroinitializer, i32 15 774 %r8 = insertelement <32 x i8> %r7, i8 zeroinitializer, i32 17 775 %r9 = insertelement <32 x i8> %r8, i8 zeroinitializer, i32 19 776 %r10 = insertelement <32 x i8> %r9, i8 zeroinitializer, i32 21 777 %r11 = insertelement <32 x i8> %r10, i8 zeroinitializer, i32 23 778 %r12 = insertelement <32 x i8> %r11, i8 zeroinitializer, i32 25 779 %r13 = insertelement <32 x i8> %r12, i8 zeroinitializer, i32 27 780 %r14 = insertelement <32 x i8> %r13, i8 zeroinitializer, i32 29 781 %r15 = insertelement <32 x i8> %r14, i8 zeroinitializer, i32 31 782 %r = bitcast <32 x i8> %r15 to <16 x i16> 783 ret <16 x i16> %r 784} 785 786define <16 x i8> @_clearupper16xi8b(<16 x i8>) nounwind { 787; SSE-LABEL: _clearupper16xi8b: 788; SSE: # BB#0: 789; SSE-NEXT: pushq %r14 790; SSE-NEXT: pushq %rbx 791; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] 792; SSE-NEXT: movq %xmm0, %rcx 793; SSE-NEXT: movq %rcx, %r8 794; SSE-NEXT: movq %rcx, %r9 795; SSE-NEXT: movq %rcx, %r10 796; SSE-NEXT: movq %rcx, %rax 797; SSE-NEXT: movq %rcx, %rdx 798; SSE-NEXT: movq %rcx, %rsi 799; SSE-NEXT: movq %rcx, %rdi 800; SSE-NEXT: andb $15, %cl 801; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 802; SSE-NEXT: movq %xmm1, %rcx 803; SSE-NEXT: shrq $56, %rdi 804; SSE-NEXT: andb $15, %dil 805; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 806; SSE-NEXT: movq %rcx, %r11 807; SSE-NEXT: shrq $48, %rsi 808; SSE-NEXT: andb $15, %sil 809; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 810; SSE-NEXT: movq %rcx, %r14 811; SSE-NEXT: shrq $40, %rdx 812; SSE-NEXT: andb $15, %dl 813; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 814; SSE-NEXT: movq %rcx, %rdx 815; SSE-NEXT: shrq $32, %rax 816; SSE-NEXT: andb $15, %al 817; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 818; SSE-NEXT: movq %rcx, %rax 819; SSE-NEXT: shrq $24, %r10 820; SSE-NEXT: andb $15, %r10b 821; SSE-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 822; SSE-NEXT: movq %rcx, %rdi 823; SSE-NEXT: shrq $16, %r9 824; SSE-NEXT: andb $15, %r9b 825; SSE-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 826; SSE-NEXT: movq %rcx, %rsi 827; SSE-NEXT: shrq $8, %r8 828; SSE-NEXT: andb $15, %r8b 829; SSE-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 830; SSE-NEXT: movq %rcx, %rbx 831; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 832; SSE-NEXT: andb $15, %cl 833; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 834; SSE-NEXT: shrq $56, %rbx 835; SSE-NEXT: andb $15, %bl 836; SSE-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 837; SSE-NEXT: shrq $48, %rsi 838; SSE-NEXT: andb $15, %sil 839; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 840; SSE-NEXT: shrq $40, %rdi 841; SSE-NEXT: andb $15, %dil 842; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 843; SSE-NEXT: shrq $32, %rax 844; SSE-NEXT: andb $15, %al 845; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 846; SSE-NEXT: shrq $24, %rdx 847; SSE-NEXT: andb $15, %dl 848; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 849; SSE-NEXT: shrq $16, %r14 850; SSE-NEXT: andb $15, %r14b 851; SSE-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 852; SSE-NEXT: shrq $8, %r11 853; SSE-NEXT: andb $15, %r11b 854; SSE-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 855; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 856; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero 857; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero 858; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 859; SSE-NEXT: popq %rbx 860; SSE-NEXT: popq %r14 861; SSE-NEXT: retq 862; 863; AVX-LABEL: _clearupper16xi8b: 864; AVX: # BB#0: 865; AVX-NEXT: pushq %rbp 866; AVX-NEXT: pushq %r15 867; AVX-NEXT: pushq %r14 868; AVX-NEXT: pushq %r13 869; AVX-NEXT: pushq %r12 870; AVX-NEXT: pushq %rbx 871; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) 872; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rcx 873; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rdx 874; AVX-NEXT: movq %rcx, %r8 875; AVX-NEXT: movq %rcx, %r9 876; AVX-NEXT: movq %rcx, %r10 877; AVX-NEXT: movq %rcx, %r11 878; AVX-NEXT: movq %rcx, %r14 879; AVX-NEXT: movq %rcx, %r15 880; AVX-NEXT: movq %rdx, %r12 881; AVX-NEXT: movq %rdx, %r13 882; AVX-NEXT: movq %rdx, %rdi 883; AVX-NEXT: movq %rdx, %rax 884; AVX-NEXT: movq %rdx, %rsi 885; AVX-NEXT: movq %rdx, %rbx 886; AVX-NEXT: movq %rdx, %rbp 887; AVX-NEXT: andb $15, %dl 888; AVX-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 889; AVX-NEXT: movq %rcx, %rdx 890; AVX-NEXT: andb $15, %cl 891; AVX-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 892; AVX-NEXT: shrq $56, %rbp 893; AVX-NEXT: andb $15, %bpl 894; AVX-NEXT: movb %bpl, -{{[0-9]+}}(%rsp) 895; AVX-NEXT: shrq $48, %rbx 896; AVX-NEXT: andb $15, %bl 897; AVX-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 898; AVX-NEXT: shrq $40, %rsi 899; AVX-NEXT: andb $15, %sil 900; AVX-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 901; AVX-NEXT: shrq $32, %rax 902; AVX-NEXT: andb $15, %al 903; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) 904; AVX-NEXT: shrq $24, %rdi 905; AVX-NEXT: andb $15, %dil 906; AVX-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 907; AVX-NEXT: shrq $16, %r13 908; AVX-NEXT: andb $15, %r13b 909; AVX-NEXT: movb %r13b, -{{[0-9]+}}(%rsp) 910; AVX-NEXT: shrq $8, %r12 911; AVX-NEXT: andb $15, %r12b 912; AVX-NEXT: movb %r12b, -{{[0-9]+}}(%rsp) 913; AVX-NEXT: shrq $56, %rdx 914; AVX-NEXT: andb $15, %dl 915; AVX-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 916; AVX-NEXT: shrq $48, %r15 917; AVX-NEXT: andb $15, %r15b 918; AVX-NEXT: movb %r15b, -{{[0-9]+}}(%rsp) 919; AVX-NEXT: shrq $40, %r14 920; AVX-NEXT: andb $15, %r14b 921; AVX-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 922; AVX-NEXT: shrq $32, %r11 923; AVX-NEXT: andb $15, %r11b 924; AVX-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 925; AVX-NEXT: shrq $24, %r10 926; AVX-NEXT: andb $15, %r10b 927; AVX-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 928; AVX-NEXT: shrq $16, %r9 929; AVX-NEXT: andb $15, %r9b 930; AVX-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 931; AVX-NEXT: shrq $8, %r8 932; AVX-NEXT: andb $15, %r8b 933; AVX-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 934; AVX-NEXT: movb $0, -{{[0-9]+}}(%rsp) 935; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0 936; AVX-NEXT: popq %rbx 937; AVX-NEXT: popq %r12 938; AVX-NEXT: popq %r13 939; AVX-NEXT: popq %r14 940; AVX-NEXT: popq %r15 941; AVX-NEXT: popq %rbp 942; AVX-NEXT: retq 943 %x4 = bitcast <16 x i8> %0 to <32 x i4> 944 %r0 = insertelement <32 x i4> %x4, i4 zeroinitializer, i32 1 945 %r1 = insertelement <32 x i4> %r0, i4 zeroinitializer, i32 3 946 %r2 = insertelement <32 x i4> %r1, i4 zeroinitializer, i32 5 947 %r3 = insertelement <32 x i4> %r2, i4 zeroinitializer, i32 7 948 %r4 = insertelement <32 x i4> %r3, i4 zeroinitializer, i32 9 949 %r5 = insertelement <32 x i4> %r4, i4 zeroinitializer, i32 11 950 %r6 = insertelement <32 x i4> %r5, i4 zeroinitializer, i32 13 951 %r7 = insertelement <32 x i4> %r6, i4 zeroinitializer, i32 15 952 %r8 = insertelement <32 x i4> %r7, i4 zeroinitializer, i32 17 953 %r9 = insertelement <32 x i4> %r8, i4 zeroinitializer, i32 19 954 %r10 = insertelement <32 x i4> %r9, i4 zeroinitializer, i32 21 955 %r11 = insertelement <32 x i4> %r10, i4 zeroinitializer, i32 23 956 %r12 = insertelement <32 x i4> %r11, i4 zeroinitializer, i32 25 957 %r13 = insertelement <32 x i4> %r12, i4 zeroinitializer, i32 27 958 %r14 = insertelement <32 x i4> %r13, i4 zeroinitializer, i32 29 959 %r15 = insertelement <32 x i4> %r14, i4 zeroinitializer, i32 31 960 %r = bitcast <32 x i4> %r15 to <16 x i8> 961 ret <16 x i8> %r 962} 963 964define <32 x i8> @_clearupper32xi8b(<32 x i8>) nounwind { 965; SSE-LABEL: _clearupper32xi8b: 966; SSE: # BB#0: 967; SSE-NEXT: pushq %r14 968; SSE-NEXT: pushq %rbx 969; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1] 970; SSE-NEXT: movq %xmm0, %rcx 971; SSE-NEXT: movq %rcx, %r8 972; SSE-NEXT: movq %rcx, %r9 973; SSE-NEXT: movq %rcx, %r10 974; SSE-NEXT: movq %rcx, %rax 975; SSE-NEXT: movq %rcx, %rdx 976; SSE-NEXT: movq %rcx, %rsi 977; SSE-NEXT: movq %rcx, %rdi 978; SSE-NEXT: andb $15, %cl 979; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 980; SSE-NEXT: movq %xmm2, %rcx 981; SSE-NEXT: shrq $56, %rdi 982; SSE-NEXT: andb $15, %dil 983; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 984; SSE-NEXT: movq %rcx, %r11 985; SSE-NEXT: shrq $48, %rsi 986; SSE-NEXT: andb $15, %sil 987; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 988; SSE-NEXT: movq %rcx, %r14 989; SSE-NEXT: shrq $40, %rdx 990; SSE-NEXT: andb $15, %dl 991; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 992; SSE-NEXT: movq %rcx, %rdx 993; SSE-NEXT: shrq $32, %rax 994; SSE-NEXT: andb $15, %al 995; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 996; SSE-NEXT: movq %rcx, %rax 997; SSE-NEXT: shrq $24, %r10 998; SSE-NEXT: andb $15, %r10b 999; SSE-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 1000; SSE-NEXT: movq %rcx, %rdi 1001; SSE-NEXT: shrq $16, %r9 1002; SSE-NEXT: andb $15, %r9b 1003; SSE-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 1004; SSE-NEXT: movq %rcx, %rsi 1005; SSE-NEXT: shrq $8, %r8 1006; SSE-NEXT: andb $15, %r8b 1007; SSE-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 1008; SSE-NEXT: movq %rcx, %rbx 1009; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1010; SSE-NEXT: andb $15, %cl 1011; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1012; SSE-NEXT: shrq $56, %rbx 1013; SSE-NEXT: andb $15, %bl 1014; SSE-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 1015; SSE-NEXT: shrq $48, %rsi 1016; SSE-NEXT: andb $15, %sil 1017; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1018; SSE-NEXT: shrq $40, %rdi 1019; SSE-NEXT: andb $15, %dil 1020; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1021; SSE-NEXT: shrq $32, %rax 1022; SSE-NEXT: andb $15, %al 1023; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1024; SSE-NEXT: shrq $24, %rdx 1025; SSE-NEXT: andb $15, %dl 1026; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1027; SSE-NEXT: shrq $16, %r14 1028; SSE-NEXT: andb $15, %r14b 1029; SSE-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 1030; SSE-NEXT: shrq $8, %r11 1031; SSE-NEXT: andb $15, %r11b 1032; SSE-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 1033; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1034; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero 1035; SSE-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero 1036; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 1037; SSE-NEXT: popq %rbx 1038; SSE-NEXT: popq %r14 1039; SSE-NEXT: retq 1040; 1041; AVX1-LABEL: _clearupper32xi8b: 1042; AVX1: # BB#0: 1043; AVX1-NEXT: pushq %rbp 1044; AVX1-NEXT: pushq %r15 1045; AVX1-NEXT: pushq %r14 1046; AVX1-NEXT: pushq %r13 1047; AVX1-NEXT: pushq %r12 1048; AVX1-NEXT: pushq %rbx 1049; AVX1-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) 1050; AVX1-NEXT: movq -{{[0-9]+}}(%rsp), %rcx 1051; AVX1-NEXT: movq -{{[0-9]+}}(%rsp), %rdx 1052; AVX1-NEXT: movq %rcx, %r8 1053; AVX1-NEXT: movq %rcx, %r9 1054; AVX1-NEXT: movq %rcx, %r10 1055; AVX1-NEXT: movq %rcx, %r11 1056; AVX1-NEXT: movq %rcx, %r14 1057; AVX1-NEXT: movq %rcx, %r15 1058; AVX1-NEXT: movq %rdx, %r12 1059; AVX1-NEXT: movq %rdx, %r13 1060; AVX1-NEXT: movq %rdx, %rdi 1061; AVX1-NEXT: movq %rdx, %rax 1062; AVX1-NEXT: movq %rdx, %rsi 1063; AVX1-NEXT: movq %rdx, %rbx 1064; AVX1-NEXT: movq %rdx, %rbp 1065; AVX1-NEXT: andb $15, %dl 1066; AVX1-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1067; AVX1-NEXT: movq %rcx, %rdx 1068; AVX1-NEXT: andb $15, %cl 1069; AVX1-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1070; AVX1-NEXT: shrq $56, %rbp 1071; AVX1-NEXT: andb $15, %bpl 1072; AVX1-NEXT: movb %bpl, -{{[0-9]+}}(%rsp) 1073; AVX1-NEXT: shrq $48, %rbx 1074; AVX1-NEXT: andb $15, %bl 1075; AVX1-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 1076; AVX1-NEXT: shrq $40, %rsi 1077; AVX1-NEXT: andb $15, %sil 1078; AVX1-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1079; AVX1-NEXT: shrq $32, %rax 1080; AVX1-NEXT: andb $15, %al 1081; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1082; AVX1-NEXT: shrq $24, %rdi 1083; AVX1-NEXT: andb $15, %dil 1084; AVX1-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1085; AVX1-NEXT: shrq $16, %r13 1086; AVX1-NEXT: andb $15, %r13b 1087; AVX1-NEXT: movb %r13b, -{{[0-9]+}}(%rsp) 1088; AVX1-NEXT: shrq $8, %r12 1089; AVX1-NEXT: andb $15, %r12b 1090; AVX1-NEXT: movb %r12b, -{{[0-9]+}}(%rsp) 1091; AVX1-NEXT: shrq $8, %r8 1092; AVX1-NEXT: shrq $16, %r9 1093; AVX1-NEXT: shrq $24, %r10 1094; AVX1-NEXT: shrq $32, %r11 1095; AVX1-NEXT: shrq $40, %r14 1096; AVX1-NEXT: shrq $48, %r15 1097; AVX1-NEXT: shrq $56, %rdx 1098; AVX1-NEXT: andb $15, %dl 1099; AVX1-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1100; AVX1-NEXT: andb $15, %r15b 1101; AVX1-NEXT: movb %r15b, -{{[0-9]+}}(%rsp) 1102; AVX1-NEXT: andb $15, %r14b 1103; AVX1-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 1104; AVX1-NEXT: andb $15, %r11b 1105; AVX1-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 1106; AVX1-NEXT: andb $15, %r10b 1107; AVX1-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 1108; AVX1-NEXT: andb $15, %r9b 1109; AVX1-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 1110; AVX1-NEXT: andb $15, %r8b 1111; AVX1-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 1112; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 1113; AVX1-NEXT: vmovq %xmm0, %rax 1114; AVX1-NEXT: movq %rax, %rcx 1115; AVX1-NEXT: movq %rax, %rdx 1116; AVX1-NEXT: movq %rax, %rsi 1117; AVX1-NEXT: movq %rax, %rdi 1118; AVX1-NEXT: movl %eax, %ebp 1119; AVX1-NEXT: movl %eax, %ebx 1120; AVX1-NEXT: vmovd %eax, %xmm1 1121; AVX1-NEXT: shrl $8, %eax 1122; AVX1-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1123; AVX1-NEXT: shrl $16, %ebx 1124; AVX1-NEXT: vpinsrb $2, %ebx, %xmm1, %xmm1 1125; AVX1-NEXT: shrl $24, %ebp 1126; AVX1-NEXT: vpinsrb $3, %ebp, %xmm1, %xmm1 1127; AVX1-NEXT: shrq $32, %rdi 1128; AVX1-NEXT: vpinsrb $4, %edi, %xmm1, %xmm1 1129; AVX1-NEXT: shrq $40, %rsi 1130; AVX1-NEXT: vpinsrb $5, %esi, %xmm1, %xmm1 1131; AVX1-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1132; AVX1-NEXT: vmovdqa -{{[0-9]+}}(%rsp), %xmm2 1133; AVX1-NEXT: shrq $48, %rdx 1134; AVX1-NEXT: vpinsrb $6, %edx, %xmm1, %xmm1 1135; AVX1-NEXT: vpextrq $1, %xmm0, %rax 1136; AVX1-NEXT: shrq $56, %rcx 1137; AVX1-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm0 1138; AVX1-NEXT: movl %eax, %ecx 1139; AVX1-NEXT: shrl $8, %ecx 1140; AVX1-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0 1141; AVX1-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0 1142; AVX1-NEXT: movl %eax, %ecx 1143; AVX1-NEXT: shrl $16, %ecx 1144; AVX1-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0 1145; AVX1-NEXT: movl %eax, %ecx 1146; AVX1-NEXT: shrl $24, %ecx 1147; AVX1-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0 1148; AVX1-NEXT: movq %rax, %rcx 1149; AVX1-NEXT: shrq $32, %rcx 1150; AVX1-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0 1151; AVX1-NEXT: movq %rax, %rcx 1152; AVX1-NEXT: shrq $40, %rcx 1153; AVX1-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0 1154; AVX1-NEXT: movq %rax, %rcx 1155; AVX1-NEXT: shrq $48, %rcx 1156; AVX1-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 1157; AVX1-NEXT: vmovq %xmm2, %rcx 1158; AVX1-NEXT: shrq $56, %rax 1159; AVX1-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 1160; AVX1-NEXT: movl %ecx, %eax 1161; AVX1-NEXT: shrl $8, %eax 1162; AVX1-NEXT: vmovd %ecx, %xmm1 1163; AVX1-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1164; AVX1-NEXT: movl %ecx, %eax 1165; AVX1-NEXT: shrl $16, %eax 1166; AVX1-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1 1167; AVX1-NEXT: movl %ecx, %eax 1168; AVX1-NEXT: shrl $24, %eax 1169; AVX1-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1 1170; AVX1-NEXT: movq %rcx, %rax 1171; AVX1-NEXT: shrq $32, %rax 1172; AVX1-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1 1173; AVX1-NEXT: movq %rcx, %rax 1174; AVX1-NEXT: shrq $40, %rax 1175; AVX1-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1 1176; AVX1-NEXT: movq %rcx, %rax 1177; AVX1-NEXT: shrq $48, %rax 1178; AVX1-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1 1179; AVX1-NEXT: vpextrq $1, %xmm2, %rax 1180; AVX1-NEXT: shrq $56, %rcx 1181; AVX1-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm1 1182; AVX1-NEXT: movl %eax, %ecx 1183; AVX1-NEXT: shrl $8, %ecx 1184; AVX1-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1 1185; AVX1-NEXT: vpinsrb $9, %ecx, %xmm1, %xmm1 1186; AVX1-NEXT: movl %eax, %ecx 1187; AVX1-NEXT: shrl $16, %ecx 1188; AVX1-NEXT: vpinsrb $10, %ecx, %xmm1, %xmm1 1189; AVX1-NEXT: movl %eax, %ecx 1190; AVX1-NEXT: shrl $24, %ecx 1191; AVX1-NEXT: vpinsrb $11, %ecx, %xmm1, %xmm1 1192; AVX1-NEXT: movq %rax, %rcx 1193; AVX1-NEXT: shrq $32, %rcx 1194; AVX1-NEXT: vpinsrb $12, %ecx, %xmm1, %xmm1 1195; AVX1-NEXT: movq %rax, %rcx 1196; AVX1-NEXT: shrq $40, %rcx 1197; AVX1-NEXT: vpinsrb $13, %ecx, %xmm1, %xmm1 1198; AVX1-NEXT: movq %rax, %rcx 1199; AVX1-NEXT: shrq $48, %rcx 1200; AVX1-NEXT: vpinsrb $14, %ecx, %xmm1, %xmm1 1201; AVX1-NEXT: shrq $56, %rax 1202; AVX1-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1 1203; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 1204; AVX1-NEXT: popq %rbx 1205; AVX1-NEXT: popq %r12 1206; AVX1-NEXT: popq %r13 1207; AVX1-NEXT: popq %r14 1208; AVX1-NEXT: popq %r15 1209; AVX1-NEXT: popq %rbp 1210; AVX1-NEXT: retq 1211; 1212; AVX2-LABEL: _clearupper32xi8b: 1213; AVX2: # BB#0: 1214; AVX2-NEXT: pushq %rbp 1215; AVX2-NEXT: pushq %r15 1216; AVX2-NEXT: pushq %r14 1217; AVX2-NEXT: pushq %r13 1218; AVX2-NEXT: pushq %r12 1219; AVX2-NEXT: pushq %rbx 1220; AVX2-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp) 1221; AVX2-NEXT: movq -{{[0-9]+}}(%rsp), %rcx 1222; AVX2-NEXT: movq -{{[0-9]+}}(%rsp), %rdx 1223; AVX2-NEXT: movq %rcx, %r8 1224; AVX2-NEXT: movq %rcx, %r9 1225; AVX2-NEXT: movq %rcx, %r10 1226; AVX2-NEXT: movq %rcx, %r11 1227; AVX2-NEXT: movq %rcx, %r14 1228; AVX2-NEXT: movq %rcx, %r15 1229; AVX2-NEXT: movq %rdx, %r12 1230; AVX2-NEXT: movq %rdx, %r13 1231; AVX2-NEXT: movq %rdx, %rdi 1232; AVX2-NEXT: movq %rdx, %rax 1233; AVX2-NEXT: movq %rdx, %rsi 1234; AVX2-NEXT: movq %rdx, %rbx 1235; AVX2-NEXT: movq %rdx, %rbp 1236; AVX2-NEXT: andb $15, %dl 1237; AVX2-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1238; AVX2-NEXT: movq %rcx, %rdx 1239; AVX2-NEXT: andb $15, %cl 1240; AVX2-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1241; AVX2-NEXT: shrq $56, %rbp 1242; AVX2-NEXT: andb $15, %bpl 1243; AVX2-NEXT: movb %bpl, -{{[0-9]+}}(%rsp) 1244; AVX2-NEXT: shrq $48, %rbx 1245; AVX2-NEXT: andb $15, %bl 1246; AVX2-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 1247; AVX2-NEXT: shrq $40, %rsi 1248; AVX2-NEXT: andb $15, %sil 1249; AVX2-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1250; AVX2-NEXT: shrq $32, %rax 1251; AVX2-NEXT: andb $15, %al 1252; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1253; AVX2-NEXT: shrq $24, %rdi 1254; AVX2-NEXT: andb $15, %dil 1255; AVX2-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1256; AVX2-NEXT: shrq $16, %r13 1257; AVX2-NEXT: andb $15, %r13b 1258; AVX2-NEXT: movb %r13b, -{{[0-9]+}}(%rsp) 1259; AVX2-NEXT: shrq $8, %r12 1260; AVX2-NEXT: andb $15, %r12b 1261; AVX2-NEXT: movb %r12b, -{{[0-9]+}}(%rsp) 1262; AVX2-NEXT: shrq $8, %r8 1263; AVX2-NEXT: shrq $16, %r9 1264; AVX2-NEXT: shrq $24, %r10 1265; AVX2-NEXT: shrq $32, %r11 1266; AVX2-NEXT: shrq $40, %r14 1267; AVX2-NEXT: shrq $48, %r15 1268; AVX2-NEXT: shrq $56, %rdx 1269; AVX2-NEXT: andb $15, %dl 1270; AVX2-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1271; AVX2-NEXT: andb $15, %r15b 1272; AVX2-NEXT: movb %r15b, -{{[0-9]+}}(%rsp) 1273; AVX2-NEXT: andb $15, %r14b 1274; AVX2-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 1275; AVX2-NEXT: andb $15, %r11b 1276; AVX2-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 1277; AVX2-NEXT: andb $15, %r10b 1278; AVX2-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 1279; AVX2-NEXT: andb $15, %r9b 1280; AVX2-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 1281; AVX2-NEXT: andb $15, %r8b 1282; AVX2-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 1283; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 1284; AVX2-NEXT: vmovq %xmm0, %rax 1285; AVX2-NEXT: movq %rax, %rcx 1286; AVX2-NEXT: movq %rax, %rdx 1287; AVX2-NEXT: movq %rax, %rsi 1288; AVX2-NEXT: movq %rax, %rdi 1289; AVX2-NEXT: movl %eax, %ebp 1290; AVX2-NEXT: movl %eax, %ebx 1291; AVX2-NEXT: vmovd %eax, %xmm1 1292; AVX2-NEXT: shrl $8, %eax 1293; AVX2-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1294; AVX2-NEXT: shrl $16, %ebx 1295; AVX2-NEXT: vpinsrb $2, %ebx, %xmm1, %xmm1 1296; AVX2-NEXT: shrl $24, %ebp 1297; AVX2-NEXT: vpinsrb $3, %ebp, %xmm1, %xmm1 1298; AVX2-NEXT: shrq $32, %rdi 1299; AVX2-NEXT: vpinsrb $4, %edi, %xmm1, %xmm1 1300; AVX2-NEXT: shrq $40, %rsi 1301; AVX2-NEXT: vpinsrb $5, %esi, %xmm1, %xmm1 1302; AVX2-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1303; AVX2-NEXT: vmovdqa -{{[0-9]+}}(%rsp), %xmm2 1304; AVX2-NEXT: shrq $48, %rdx 1305; AVX2-NEXT: vpinsrb $6, %edx, %xmm1, %xmm1 1306; AVX2-NEXT: vpextrq $1, %xmm0, %rax 1307; AVX2-NEXT: shrq $56, %rcx 1308; AVX2-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm0 1309; AVX2-NEXT: movl %eax, %ecx 1310; AVX2-NEXT: shrl $8, %ecx 1311; AVX2-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0 1312; AVX2-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0 1313; AVX2-NEXT: movl %eax, %ecx 1314; AVX2-NEXT: shrl $16, %ecx 1315; AVX2-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0 1316; AVX2-NEXT: movl %eax, %ecx 1317; AVX2-NEXT: shrl $24, %ecx 1318; AVX2-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0 1319; AVX2-NEXT: movq %rax, %rcx 1320; AVX2-NEXT: shrq $32, %rcx 1321; AVX2-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0 1322; AVX2-NEXT: movq %rax, %rcx 1323; AVX2-NEXT: shrq $40, %rcx 1324; AVX2-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0 1325; AVX2-NEXT: movq %rax, %rcx 1326; AVX2-NEXT: shrq $48, %rcx 1327; AVX2-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 1328; AVX2-NEXT: vmovq %xmm2, %rcx 1329; AVX2-NEXT: shrq $56, %rax 1330; AVX2-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 1331; AVX2-NEXT: movl %ecx, %eax 1332; AVX2-NEXT: shrl $8, %eax 1333; AVX2-NEXT: vmovd %ecx, %xmm1 1334; AVX2-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1335; AVX2-NEXT: movl %ecx, %eax 1336; AVX2-NEXT: shrl $16, %eax 1337; AVX2-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1 1338; AVX2-NEXT: movl %ecx, %eax 1339; AVX2-NEXT: shrl $24, %eax 1340; AVX2-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1 1341; AVX2-NEXT: movq %rcx, %rax 1342; AVX2-NEXT: shrq $32, %rax 1343; AVX2-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1 1344; AVX2-NEXT: movq %rcx, %rax 1345; AVX2-NEXT: shrq $40, %rax 1346; AVX2-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1 1347; AVX2-NEXT: movq %rcx, %rax 1348; AVX2-NEXT: shrq $48, %rax 1349; AVX2-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1 1350; AVX2-NEXT: vpextrq $1, %xmm2, %rax 1351; AVX2-NEXT: shrq $56, %rcx 1352; AVX2-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm1 1353; AVX2-NEXT: movl %eax, %ecx 1354; AVX2-NEXT: shrl $8, %ecx 1355; AVX2-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1 1356; AVX2-NEXT: vpinsrb $9, %ecx, %xmm1, %xmm1 1357; AVX2-NEXT: movl %eax, %ecx 1358; AVX2-NEXT: shrl $16, %ecx 1359; AVX2-NEXT: vpinsrb $10, %ecx, %xmm1, %xmm1 1360; AVX2-NEXT: movl %eax, %ecx 1361; AVX2-NEXT: shrl $24, %ecx 1362; AVX2-NEXT: vpinsrb $11, %ecx, %xmm1, %xmm1 1363; AVX2-NEXT: movq %rax, %rcx 1364; AVX2-NEXT: shrq $32, %rcx 1365; AVX2-NEXT: vpinsrb $12, %ecx, %xmm1, %xmm1 1366; AVX2-NEXT: movq %rax, %rcx 1367; AVX2-NEXT: shrq $40, %rcx 1368; AVX2-NEXT: vpinsrb $13, %ecx, %xmm1, %xmm1 1369; AVX2-NEXT: movq %rax, %rcx 1370; AVX2-NEXT: shrq $48, %rcx 1371; AVX2-NEXT: vpinsrb $14, %ecx, %xmm1, %xmm1 1372; AVX2-NEXT: shrq $56, %rax 1373; AVX2-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1 1374; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 1375; AVX2-NEXT: popq %rbx 1376; AVX2-NEXT: popq %r12 1377; AVX2-NEXT: popq %r13 1378; AVX2-NEXT: popq %r14 1379; AVX2-NEXT: popq %r15 1380; AVX2-NEXT: popq %rbp 1381; AVX2-NEXT: retq 1382 %x4 = bitcast <32 x i8> %0 to <64 x i4> 1383 %r0 = insertelement <64 x i4> %x4, i4 zeroinitializer, i32 1 1384 %r1 = insertelement <64 x i4> %r0, i4 zeroinitializer, i32 3 1385 %r2 = insertelement <64 x i4> %r1, i4 zeroinitializer, i32 5 1386 %r3 = insertelement <64 x i4> %r2, i4 zeroinitializer, i32 7 1387 %r4 = insertelement <64 x i4> %r3, i4 zeroinitializer, i32 9 1388 %r5 = insertelement <64 x i4> %r4, i4 zeroinitializer, i32 11 1389 %r6 = insertelement <64 x i4> %r5, i4 zeroinitializer, i32 13 1390 %r7 = insertelement <64 x i4> %r6, i4 zeroinitializer, i32 15 1391 %r8 = insertelement <64 x i4> %r7, i4 zeroinitializer, i32 17 1392 %r9 = insertelement <64 x i4> %r8, i4 zeroinitializer, i32 19 1393 %r10 = insertelement <64 x i4> %r9, i4 zeroinitializer, i32 21 1394 %r11 = insertelement <64 x i4> %r10, i4 zeroinitializer, i32 23 1395 %r12 = insertelement <64 x i4> %r11, i4 zeroinitializer, i32 25 1396 %r13 = insertelement <64 x i4> %r12, i4 zeroinitializer, i32 27 1397 %r14 = insertelement <64 x i4> %r13, i4 zeroinitializer, i32 29 1398 %r15 = insertelement <64 x i4> %r14, i4 zeroinitializer, i32 31 1399 %r16 = insertelement <64 x i4> %r15, i4 zeroinitializer, i32 33 1400 %r17 = insertelement <64 x i4> %r16, i4 zeroinitializer, i32 35 1401 %r18 = insertelement <64 x i4> %r17, i4 zeroinitializer, i32 37 1402 %r19 = insertelement <64 x i4> %r18, i4 zeroinitializer, i32 39 1403 %r20 = insertelement <64 x i4> %r19, i4 zeroinitializer, i32 41 1404 %r21 = insertelement <64 x i4> %r20, i4 zeroinitializer, i32 43 1405 %r22 = insertelement <64 x i4> %r21, i4 zeroinitializer, i32 45 1406 %r23 = insertelement <64 x i4> %r22, i4 zeroinitializer, i32 47 1407 %r24 = insertelement <64 x i4> %r23, i4 zeroinitializer, i32 49 1408 %r25 = insertelement <64 x i4> %r24, i4 zeroinitializer, i32 51 1409 %r26 = insertelement <64 x i4> %r25, i4 zeroinitializer, i32 53 1410 %r27 = insertelement <64 x i4> %r26, i4 zeroinitializer, i32 55 1411 %r28 = insertelement <64 x i4> %r27, i4 zeroinitializer, i32 57 1412 %r29 = insertelement <64 x i4> %r28, i4 zeroinitializer, i32 59 1413 %r30 = insertelement <64 x i4> %r29, i4 zeroinitializer, i32 61 1414 %r31 = insertelement <64 x i4> %r30, i4 zeroinitializer, i32 63 1415 %r = bitcast <64 x i4> %r15 to <32 x i8> 1416 ret <32 x i8> %r 1417} 1418 1419define <2 x i64> @_clearupper2xi64c(<2 x i64>) nounwind { 1420; SSE-LABEL: _clearupper2xi64c: 1421; SSE: # BB#0: 1422; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1423; SSE-NEXT: retq 1424; 1425; AVX1-LABEL: _clearupper2xi64c: 1426; AVX1: # BB#0: 1427; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 1428; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 1429; AVX1-NEXT: retq 1430; 1431; AVX2-LABEL: _clearupper2xi64c: 1432; AVX2: # BB#0: 1433; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1 1434; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 1435; AVX2-NEXT: retq 1436 %r = and <2 x i64> <i64 4294967295, i64 4294967295>, %0 1437 ret <2 x i64> %r 1438} 1439 1440define <4 x i64> @_clearupper4xi64c(<4 x i64>) nounwind { 1441; SSE-LABEL: _clearupper4xi64c: 1442; SSE: # BB#0: 1443; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0] 1444; SSE-NEXT: andps %xmm2, %xmm0 1445; SSE-NEXT: andps %xmm2, %xmm1 1446; SSE-NEXT: retq 1447; 1448; AVX-LABEL: _clearupper4xi64c: 1449; AVX: # BB#0: 1450; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 1451; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 1452; AVX-NEXT: retq 1453 %r = and <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>, %0 1454 ret <4 x i64> %r 1455} 1456 1457define <4 x i32> @_clearupper4xi32c(<4 x i32>) nounwind { 1458; SSE-LABEL: _clearupper4xi32c: 1459; SSE: # BB#0: 1460; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1461; SSE-NEXT: retq 1462; 1463; AVX-LABEL: _clearupper4xi32c: 1464; AVX: # BB#0: 1465; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 1466; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 1467; AVX-NEXT: retq 1468 %r = and <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>, %0 1469 ret <4 x i32> %r 1470} 1471 1472define <8 x i32> @_clearupper8xi32c(<8 x i32>) nounwind { 1473; SSE-LABEL: _clearupper8xi32c: 1474; SSE: # BB#0: 1475; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,0,65535,0,65535,0] 1476; SSE-NEXT: andps %xmm2, %xmm0 1477; SSE-NEXT: andps %xmm2, %xmm1 1478; SSE-NEXT: retq 1479; 1480; AVX1-LABEL: _clearupper8xi32c: 1481; AVX1: # BB#0: 1482; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 1483; AVX1-NEXT: retq 1484; 1485; AVX2-LABEL: _clearupper8xi32c: 1486; AVX2: # BB#0: 1487; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 1488; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] 1489; AVX2-NEXT: retq 1490 %r = and <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>, %0 1491 ret <8 x i32> %r 1492} 1493 1494define <8 x i16> @_clearupper8xi16c(<8 x i16>) nounwind { 1495; SSE-LABEL: _clearupper8xi16c: 1496; SSE: # BB#0: 1497; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1498; SSE-NEXT: retq 1499; 1500; AVX-LABEL: _clearupper8xi16c: 1501; AVX: # BB#0: 1502; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 1503; AVX-NEXT: retq 1504 %r = and <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, %0 1505 ret <8 x i16> %r 1506} 1507 1508define <16 x i16> @_clearupper16xi16c(<16 x i16>) nounwind { 1509; SSE-LABEL: _clearupper16xi16c: 1510; SSE: # BB#0: 1511; SSE-NEXT: movaps {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] 1512; SSE-NEXT: andps %xmm2, %xmm0 1513; SSE-NEXT: andps %xmm2, %xmm1 1514; SSE-NEXT: retq 1515; 1516; AVX-LABEL: _clearupper16xi16c: 1517; AVX: # BB#0: 1518; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 1519; AVX-NEXT: retq 1520 %r = and <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, %0 1521 ret <16 x i16> %r 1522} 1523 1524define <16 x i8> @_clearupper16xi8c(<16 x i8>) nounwind { 1525; SSE-LABEL: _clearupper16xi8c: 1526; SSE: # BB#0: 1527; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1528; SSE-NEXT: retq 1529; 1530; AVX-LABEL: _clearupper16xi8c: 1531; AVX: # BB#0: 1532; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 1533; AVX-NEXT: retq 1534 %r = and <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, %0 1535 ret <16 x i8> %r 1536} 1537 1538define <32 x i8> @_clearupper32xi8c(<32 x i8>) nounwind { 1539; SSE-LABEL: _clearupper32xi8c: 1540; SSE: # BB#0: 1541; SSE-NEXT: movaps {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] 1542; SSE-NEXT: andps %xmm2, %xmm0 1543; SSE-NEXT: andps %xmm2, %xmm1 1544; SSE-NEXT: retq 1545; 1546; AVX-LABEL: _clearupper32xi8c: 1547; AVX: # BB#0: 1548; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 1549; AVX-NEXT: retq 1550 %r = and <32 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, %0 1551 ret <32 x i8> %r 1552} 1553