1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 5 6; 7; PR6455 'Clear Upper Bits' Patterns 8; 9 10define <2 x i64> @_clearupper2xi64a(<2 x i64>) nounwind { 11; SSE-LABEL: _clearupper2xi64a: 12; SSE: # BB#0: 13; SSE-NEXT: andps {{.*}}(%rip), %xmm0 14; SSE-NEXT: retq 15; 16; AVX1-LABEL: _clearupper2xi64a: 17; AVX1: # BB#0: 18; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 19; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 20; AVX1-NEXT: retq 21; 22; AVX2-LABEL: _clearupper2xi64a: 23; AVX2: # BB#0: 24; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 25; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 26; AVX2-NEXT: retq 27 %x0 = extractelement <2 x i64> %0, i32 0 28 %x1 = extractelement <2 x i64> %0, i32 1 29 %trunc0 = trunc i64 %x0 to i32 30 %trunc1 = trunc i64 %x1 to i32 31 %ext0 = zext i32 %trunc0 to i64 32 %ext1 = zext i32 %trunc1 to i64 33 %v0 = insertelement <2 x i64> undef, i64 %ext0, i32 0 34 %v1 = insertelement <2 x i64> %v0, i64 %ext1, i32 1 35 ret <2 x i64> %v1 36} 37 38define <4 x i64> @_clearupper4xi64a(<4 x i64>) nounwind { 39; SSE-LABEL: _clearupper4xi64a: 40; SSE: # BB#0: 41; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,4294967295] 42; SSE-NEXT: andps %xmm2, %xmm0 43; SSE-NEXT: andps %xmm2, %xmm1 44; SSE-NEXT: retq 45; 46; AVX1-LABEL: _clearupper4xi64a: 47; AVX1: # BB#0: 48; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 49; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 50; AVX1-NEXT: retq 51; 52; AVX2-LABEL: _clearupper4xi64a: 53; AVX2: # BB#0: 54; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 55; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 56; AVX2-NEXT: retq 57 %x0 = extractelement <4 x i64> %0, i32 0 58 %x1 = extractelement <4 x i64> %0, i32 1 59 %x2 = extractelement <4 x i64> %0, i32 2 60 %x3 = extractelement <4 x i64> %0, i32 3 61 %trunc0 = trunc i64 %x0 to i32 62 %trunc1 = trunc i64 %x1 to i32 63 %trunc2 = trunc i64 %x2 to i32 64 %trunc3 = trunc i64 %x3 to i32 65 %ext0 = zext i32 %trunc0 to i64 66 %ext1 = zext i32 %trunc1 to i64 67 %ext2 = zext i32 %trunc2 to i64 68 %ext3 = zext i32 %trunc3 to i64 69 %v0 = insertelement <4 x i64> undef, i64 %ext0, i32 0 70 %v1 = insertelement <4 x i64> %v0, i64 %ext1, i32 1 71 %v2 = insertelement <4 x i64> %v1, i64 %ext2, i32 2 72 %v3 = insertelement <4 x i64> %v2, i64 %ext3, i32 3 73 ret <4 x i64> %v3 74} 75 76define <4 x i32> @_clearupper4xi32a(<4 x i32>) nounwind { 77; SSE-LABEL: _clearupper4xi32a: 78; SSE: # BB#0: 79; SSE-NEXT: andps {{.*}}(%rip), %xmm0 80; SSE-NEXT: retq 81; 82; AVX-LABEL: _clearupper4xi32a: 83; AVX: # BB#0: 84; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 85; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 86; AVX-NEXT: retq 87 %x0 = extractelement <4 x i32> %0, i32 0 88 %x1 = extractelement <4 x i32> %0, i32 1 89 %x2 = extractelement <4 x i32> %0, i32 2 90 %x3 = extractelement <4 x i32> %0, i32 3 91 %trunc0 = trunc i32 %x0 to i16 92 %trunc1 = trunc i32 %x1 to i16 93 %trunc2 = trunc i32 %x2 to i16 94 %trunc3 = trunc i32 %x3 to i16 95 %ext0 = zext i16 %trunc0 to i32 96 %ext1 = zext i16 %trunc1 to i32 97 %ext2 = zext i16 %trunc2 to i32 98 %ext3 = zext i16 %trunc3 to i32 99 %v0 = insertelement <4 x i32> undef, i32 %ext0, i32 0 100 %v1 = insertelement <4 x i32> %v0, i32 %ext1, i32 1 101 %v2 = insertelement <4 x i32> %v1, i32 %ext2, i32 2 102 %v3 = insertelement <4 x i32> %v2, i32 %ext3, i32 3 103 ret <4 x i32> %v3 104} 105 106; FIXME: Missed vpblendw on AVX2 target 107define <8 x i32> @_clearupper8xi32a(<8 x i32>) nounwind { 108; SSE-LABEL: _clearupper8xi32a: 109; SSE: # BB#0: 110; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,65535,65535,65535] 111; SSE-NEXT: andps %xmm2, %xmm0 112; SSE-NEXT: andps %xmm2, %xmm1 113; SSE-NEXT: retq 114; 115; AVX1-LABEL: _clearupper8xi32a: 116; AVX1: # BB#0: 117; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 118; AVX1-NEXT: retq 119; 120; AVX2-LABEL: _clearupper8xi32a: 121; AVX2: # BB#0: 122; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1 123; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0 124; AVX2-NEXT: retq 125 %x0 = extractelement <8 x i32> %0, i32 0 126 %x1 = extractelement <8 x i32> %0, i32 1 127 %x2 = extractelement <8 x i32> %0, i32 2 128 %x3 = extractelement <8 x i32> %0, i32 3 129 %x4 = extractelement <8 x i32> %0, i32 4 130 %x5 = extractelement <8 x i32> %0, i32 5 131 %x6 = extractelement <8 x i32> %0, i32 6 132 %x7 = extractelement <8 x i32> %0, i32 7 133 %trunc0 = trunc i32 %x0 to i16 134 %trunc1 = trunc i32 %x1 to i16 135 %trunc2 = trunc i32 %x2 to i16 136 %trunc3 = trunc i32 %x3 to i16 137 %trunc4 = trunc i32 %x4 to i16 138 %trunc5 = trunc i32 %x5 to i16 139 %trunc6 = trunc i32 %x6 to i16 140 %trunc7 = trunc i32 %x7 to i16 141 %ext0 = zext i16 %trunc0 to i32 142 %ext1 = zext i16 %trunc1 to i32 143 %ext2 = zext i16 %trunc2 to i32 144 %ext3 = zext i16 %trunc3 to i32 145 %ext4 = zext i16 %trunc4 to i32 146 %ext5 = zext i16 %trunc5 to i32 147 %ext6 = zext i16 %trunc6 to i32 148 %ext7 = zext i16 %trunc7 to i32 149 %v0 = insertelement <8 x i32> undef, i32 %ext0, i32 0 150 %v1 = insertelement <8 x i32> %v0, i32 %ext1, i32 1 151 %v2 = insertelement <8 x i32> %v1, i32 %ext2, i32 2 152 %v3 = insertelement <8 x i32> %v2, i32 %ext3, i32 3 153 %v4 = insertelement <8 x i32> %v3, i32 %ext4, i32 4 154 %v5 = insertelement <8 x i32> %v4, i32 %ext5, i32 5 155 %v6 = insertelement <8 x i32> %v5, i32 %ext6, i32 6 156 %v7 = insertelement <8 x i32> %v6, i32 %ext7, i32 7 157 ret <8 x i32> %v7 158} 159 160define <8 x i16> @_clearupper8xi16a(<8 x i16>) nounwind { 161; SSE-LABEL: _clearupper8xi16a: 162; SSE: # BB#0: 163; SSE-NEXT: pextrw $1, %xmm0, %eax 164; SSE-NEXT: pextrw $2, %xmm0, %r9d 165; SSE-NEXT: pextrw $3, %xmm0, %edx 166; SSE-NEXT: pextrw $4, %xmm0, %r8d 167; SSE-NEXT: pextrw $5, %xmm0, %edi 168; SSE-NEXT: pextrw $6, %xmm0, %esi 169; SSE-NEXT: pextrw $7, %xmm0, %ecx 170; SSE-NEXT: movd %ecx, %xmm1 171; SSE-NEXT: movd %edx, %xmm2 172; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 173; SSE-NEXT: movd %edi, %xmm1 174; SSE-NEXT: movd %eax, %xmm3 175; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3] 176; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] 177; SSE-NEXT: movd %esi, %xmm1 178; SSE-NEXT: movd %r9d, %xmm2 179; SSE-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 180; SSE-NEXT: movd %r8d, %xmm1 181; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 182; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] 183; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] 184; SSE-NEXT: pand {{.*}}(%rip), %xmm0 185; SSE-NEXT: retq 186; 187; AVX-LABEL: _clearupper8xi16a: 188; AVX: # BB#0: 189; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 190; AVX-NEXT: retq 191 %x0 = extractelement <8 x i16> %0, i32 0 192 %x1 = extractelement <8 x i16> %0, i32 1 193 %x2 = extractelement <8 x i16> %0, i32 2 194 %x3 = extractelement <8 x i16> %0, i32 3 195 %x4 = extractelement <8 x i16> %0, i32 4 196 %x5 = extractelement <8 x i16> %0, i32 5 197 %x6 = extractelement <8 x i16> %0, i32 6 198 %x7 = extractelement <8 x i16> %0, i32 7 199 %trunc0 = trunc i16 %x0 to i8 200 %trunc1 = trunc i16 %x1 to i8 201 %trunc2 = trunc i16 %x2 to i8 202 %trunc3 = trunc i16 %x3 to i8 203 %trunc4 = trunc i16 %x4 to i8 204 %trunc5 = trunc i16 %x5 to i8 205 %trunc6 = trunc i16 %x6 to i8 206 %trunc7 = trunc i16 %x7 to i8 207 %ext0 = zext i8 %trunc0 to i16 208 %ext1 = zext i8 %trunc1 to i16 209 %ext2 = zext i8 %trunc2 to i16 210 %ext3 = zext i8 %trunc3 to i16 211 %ext4 = zext i8 %trunc4 to i16 212 %ext5 = zext i8 %trunc5 to i16 213 %ext6 = zext i8 %trunc6 to i16 214 %ext7 = zext i8 %trunc7 to i16 215 %v0 = insertelement <8 x i16> undef, i16 %ext0, i32 0 216 %v1 = insertelement <8 x i16> %v0, i16 %ext1, i32 1 217 %v2 = insertelement <8 x i16> %v1, i16 %ext2, i32 2 218 %v3 = insertelement <8 x i16> %v2, i16 %ext3, i32 3 219 %v4 = insertelement <8 x i16> %v3, i16 %ext4, i32 4 220 %v5 = insertelement <8 x i16> %v4, i16 %ext5, i32 5 221 %v6 = insertelement <8 x i16> %v5, i16 %ext6, i32 6 222 %v7 = insertelement <8 x i16> %v6, i16 %ext7, i32 7 223 ret <8 x i16> %v7 224} 225 226define <16 x i16> @_clearupper16xi16a(<16 x i16>) nounwind { 227; SSE-LABEL: _clearupper16xi16a: 228; SSE: # BB#0: 229; SSE-NEXT: pushq %rbp 230; SSE-NEXT: pushq %r15 231; SSE-NEXT: pushq %r14 232; SSE-NEXT: pushq %r12 233; SSE-NEXT: pushq %rbx 234; SSE-NEXT: pextrw $1, %xmm0, %edi 235; SSE-NEXT: pextrw $2, %xmm0, %eax 236; SSE-NEXT: pextrw $3, %xmm0, %ecx 237; SSE-NEXT: pextrw $4, %xmm0, %edx 238; SSE-NEXT: pextrw $5, %xmm0, %esi 239; SSE-NEXT: pextrw $6, %xmm0, %ebx 240; SSE-NEXT: pextrw $7, %xmm0, %ebp 241; SSE-NEXT: pextrw $1, %xmm1, %r10d 242; SSE-NEXT: pextrw $2, %xmm1, %r9d 243; SSE-NEXT: pextrw $3, %xmm1, %r14d 244; SSE-NEXT: pextrw $4, %xmm1, %r8d 245; SSE-NEXT: pextrw $5, %xmm1, %r15d 246; SSE-NEXT: pextrw $6, %xmm1, %r11d 247; SSE-NEXT: pextrw $7, %xmm1, %r12d 248; SSE-NEXT: movd %ebp, %xmm2 249; SSE-NEXT: movd %ecx, %xmm3 250; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] 251; SSE-NEXT: movd %esi, %xmm2 252; SSE-NEXT: movd %edi, %xmm4 253; SSE-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] 254; SSE-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] 255; SSE-NEXT: movd %ebx, %xmm2 256; SSE-NEXT: movd %eax, %xmm3 257; SSE-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] 258; SSE-NEXT: movd %edx, %xmm2 259; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] 260; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] 261; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] 262; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] 263; SSE-NEXT: pand %xmm2, %xmm0 264; SSE-NEXT: movd %r12d, %xmm3 265; SSE-NEXT: movd %r14d, %xmm4 266; SSE-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] 267; SSE-NEXT: movd %r15d, %xmm3 268; SSE-NEXT: movd %r10d, %xmm5 269; SSE-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3] 270; SSE-NEXT: punpcklwd {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3] 271; SSE-NEXT: movd %r11d, %xmm3 272; SSE-NEXT: movd %r9d, %xmm4 273; SSE-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] 274; SSE-NEXT: movd %r8d, %xmm3 275; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3] 276; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3] 277; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1],xmm1[2],xmm5[2],xmm1[3],xmm5[3] 278; SSE-NEXT: pand %xmm2, %xmm1 279; SSE-NEXT: popq %rbx 280; SSE-NEXT: popq %r12 281; SSE-NEXT: popq %r14 282; SSE-NEXT: popq %r15 283; SSE-NEXT: popq %rbp 284; SSE-NEXT: retq 285; 286; AVX-LABEL: _clearupper16xi16a: 287; AVX: # BB#0: 288; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 289; AVX-NEXT: retq 290 %x0 = extractelement <16 x i16> %0, i32 0 291 %x1 = extractelement <16 x i16> %0, i32 1 292 %x2 = extractelement <16 x i16> %0, i32 2 293 %x3 = extractelement <16 x i16> %0, i32 3 294 %x4 = extractelement <16 x i16> %0, i32 4 295 %x5 = extractelement <16 x i16> %0, i32 5 296 %x6 = extractelement <16 x i16> %0, i32 6 297 %x7 = extractelement <16 x i16> %0, i32 7 298 %x8 = extractelement <16 x i16> %0, i32 8 299 %x9 = extractelement <16 x i16> %0, i32 9 300 %x10 = extractelement <16 x i16> %0, i32 10 301 %x11 = extractelement <16 x i16> %0, i32 11 302 %x12 = extractelement <16 x i16> %0, i32 12 303 %x13 = extractelement <16 x i16> %0, i32 13 304 %x14 = extractelement <16 x i16> %0, i32 14 305 %x15 = extractelement <16 x i16> %0, i32 15 306 %trunc0 = trunc i16 %x0 to i8 307 %trunc1 = trunc i16 %x1 to i8 308 %trunc2 = trunc i16 %x2 to i8 309 %trunc3 = trunc i16 %x3 to i8 310 %trunc4 = trunc i16 %x4 to i8 311 %trunc5 = trunc i16 %x5 to i8 312 %trunc6 = trunc i16 %x6 to i8 313 %trunc7 = trunc i16 %x7 to i8 314 %trunc8 = trunc i16 %x8 to i8 315 %trunc9 = trunc i16 %x9 to i8 316 %trunc10 = trunc i16 %x10 to i8 317 %trunc11 = trunc i16 %x11 to i8 318 %trunc12 = trunc i16 %x12 to i8 319 %trunc13 = trunc i16 %x13 to i8 320 %trunc14 = trunc i16 %x14 to i8 321 %trunc15 = trunc i16 %x15 to i8 322 %ext0 = zext i8 %trunc0 to i16 323 %ext1 = zext i8 %trunc1 to i16 324 %ext2 = zext i8 %trunc2 to i16 325 %ext3 = zext i8 %trunc3 to i16 326 %ext4 = zext i8 %trunc4 to i16 327 %ext5 = zext i8 %trunc5 to i16 328 %ext6 = zext i8 %trunc6 to i16 329 %ext7 = zext i8 %trunc7 to i16 330 %ext8 = zext i8 %trunc8 to i16 331 %ext9 = zext i8 %trunc9 to i16 332 %ext10 = zext i8 %trunc10 to i16 333 %ext11 = zext i8 %trunc11 to i16 334 %ext12 = zext i8 %trunc12 to i16 335 %ext13 = zext i8 %trunc13 to i16 336 %ext14 = zext i8 %trunc14 to i16 337 %ext15 = zext i8 %trunc15 to i16 338 %v0 = insertelement <16 x i16> undef, i16 %ext0, i32 0 339 %v1 = insertelement <16 x i16> %v0, i16 %ext1, i32 1 340 %v2 = insertelement <16 x i16> %v1, i16 %ext2, i32 2 341 %v3 = insertelement <16 x i16> %v2, i16 %ext3, i32 3 342 %v4 = insertelement <16 x i16> %v3, i16 %ext4, i32 4 343 %v5 = insertelement <16 x i16> %v4, i16 %ext5, i32 5 344 %v6 = insertelement <16 x i16> %v5, i16 %ext6, i32 6 345 %v7 = insertelement <16 x i16> %v6, i16 %ext7, i32 7 346 %v8 = insertelement <16 x i16> %v7, i16 %ext8, i32 8 347 %v9 = insertelement <16 x i16> %v8, i16 %ext9, i32 9 348 %v10 = insertelement <16 x i16> %v9, i16 %ext10, i32 10 349 %v11 = insertelement <16 x i16> %v10, i16 %ext11, i32 11 350 %v12 = insertelement <16 x i16> %v11, i16 %ext12, i32 12 351 %v13 = insertelement <16 x i16> %v12, i16 %ext13, i32 13 352 %v14 = insertelement <16 x i16> %v13, i16 %ext14, i32 14 353 %v15 = insertelement <16 x i16> %v14, i16 %ext15, i32 15 354 ret <16 x i16> %v15 355} 356 357define <16 x i8> @_clearupper16xi8a(<16 x i8>) nounwind { 358; SSE-LABEL: _clearupper16xi8a: 359; SSE: # BB#0: 360; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) 361; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 362; SSE-NEXT: movd %eax, %xmm0 363; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d 364; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx 365; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi 366; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d 367; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi 368; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 369; SSE-NEXT: movd %eax, %xmm1 370; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 371; SSE-NEXT: movd %esi, %xmm0 372; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 373; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi 374; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx 375; SSE-NEXT: movd %ecx, %xmm2 376; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 377; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] 378; SSE-NEXT: movd %edx, %xmm0 379; SSE-NEXT: movd %esi, %xmm1 380; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 381; SSE-NEXT: movd %edi, %xmm0 382; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx 383; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx 384; SSE-NEXT: movd %edx, %xmm3 385; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 386; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 387; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] 388; SSE-NEXT: movd %r9d, %xmm0 389; SSE-NEXT: movd %eax, %xmm1 390; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 391; SSE-NEXT: movd %r8d, %xmm0 392; SSE-NEXT: movd %ecx, %xmm2 393; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 394; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] 395; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 396; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 397; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 398; SSE-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero 399; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 400; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] 401; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 402; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] 403; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] 404; SSE-NEXT: pand {{.*}}(%rip), %xmm0 405; SSE-NEXT: retq 406; 407; AVX-LABEL: _clearupper16xi8a: 408; AVX: # BB#0: 409; AVX-NEXT: vpextrb $0, %xmm0, %eax 410; AVX-NEXT: vpextrb $1, %xmm0, %ecx 411; AVX-NEXT: vmovd %eax, %xmm1 412; AVX-NEXT: vpinsrb $1, %ecx, %xmm1, %xmm1 413; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3,4,5,6,7] 414; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 415; AVX-NEXT: retq 416 %x0 = extractelement <16 x i8> %0, i32 0 417 %x1 = extractelement <16 x i8> %0, i32 1 418 %x2 = extractelement <16 x i8> %0, i32 2 419 %x3 = extractelement <16 x i8> %0, i32 3 420 %x4 = extractelement <16 x i8> %0, i32 4 421 %x5 = extractelement <16 x i8> %0, i32 5 422 %x6 = extractelement <16 x i8> %0, i32 6 423 %x7 = extractelement <16 x i8> %0, i32 7 424 %x8 = extractelement <16 x i8> %0, i32 8 425 %x9 = extractelement <16 x i8> %0, i32 9 426 %x10 = extractelement <16 x i8> %0, i32 10 427 %x11 = extractelement <16 x i8> %0, i32 11 428 %x12 = extractelement <16 x i8> %0, i32 12 429 %x13 = extractelement <16 x i8> %0, i32 13 430 %x14 = extractelement <16 x i8> %0, i32 14 431 %x15 = extractelement <16 x i8> %0, i32 15 432 %trunc0 = trunc i8 %x0 to i4 433 %trunc1 = trunc i8 %x1 to i4 434 %trunc2 = trunc i8 %x2 to i4 435 %trunc3 = trunc i8 %x3 to i4 436 %trunc4 = trunc i8 %x4 to i4 437 %trunc5 = trunc i8 %x5 to i4 438 %trunc6 = trunc i8 %x6 to i4 439 %trunc7 = trunc i8 %x7 to i4 440 %trunc8 = trunc i8 %x8 to i4 441 %trunc9 = trunc i8 %x9 to i4 442 %trunc10 = trunc i8 %x10 to i4 443 %trunc11 = trunc i8 %x11 to i4 444 %trunc12 = trunc i8 %x12 to i4 445 %trunc13 = trunc i8 %x13 to i4 446 %trunc14 = trunc i8 %x14 to i4 447 %trunc15 = trunc i8 %x15 to i4 448 %ext0 = zext i4 %trunc0 to i8 449 %ext1 = zext i4 %trunc1 to i8 450 %ext2 = zext i4 %trunc2 to i8 451 %ext3 = zext i4 %trunc3 to i8 452 %ext4 = zext i4 %trunc4 to i8 453 %ext5 = zext i4 %trunc5 to i8 454 %ext6 = zext i4 %trunc6 to i8 455 %ext7 = zext i4 %trunc7 to i8 456 %ext8 = zext i4 %trunc8 to i8 457 %ext9 = zext i4 %trunc9 to i8 458 %ext10 = zext i4 %trunc10 to i8 459 %ext11 = zext i4 %trunc11 to i8 460 %ext12 = zext i4 %trunc12 to i8 461 %ext13 = zext i4 %trunc13 to i8 462 %ext14 = zext i4 %trunc14 to i8 463 %ext15 = zext i4 %trunc15 to i8 464 %v0 = insertelement <16 x i8> undef, i8 %ext0, i32 0 465 %v1 = insertelement <16 x i8> %v0, i8 %ext1, i32 1 466 %v2 = insertelement <16 x i8> %v1, i8 %ext2, i32 2 467 %v3 = insertelement <16 x i8> %v2, i8 %ext3, i32 3 468 %v4 = insertelement <16 x i8> %v3, i8 %ext4, i32 4 469 %v5 = insertelement <16 x i8> %v4, i8 %ext5, i32 5 470 %v6 = insertelement <16 x i8> %v5, i8 %ext6, i32 6 471 %v7 = insertelement <16 x i8> %v6, i8 %ext7, i32 7 472 %v8 = insertelement <16 x i8> %v7, i8 %ext8, i32 8 473 %v9 = insertelement <16 x i8> %v8, i8 %ext9, i32 9 474 %v10 = insertelement <16 x i8> %v9, i8 %ext10, i32 10 475 %v11 = insertelement <16 x i8> %v10, i8 %ext11, i32 11 476 %v12 = insertelement <16 x i8> %v11, i8 %ext12, i32 12 477 %v13 = insertelement <16 x i8> %v12, i8 %ext13, i32 13 478 %v14 = insertelement <16 x i8> %v13, i8 %ext14, i32 14 479 %v15 = insertelement <16 x i8> %v14, i8 %ext15, i32 15 480 ret <16 x i8> %v15 481} 482 483define <32 x i8> @_clearupper32xi8a(<32 x i8>) nounwind { 484; SSE-LABEL: _clearupper32xi8a: 485; SSE: # BB#0: 486; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) 487; SSE-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) 488; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 489; SSE-NEXT: movd %eax, %xmm0 490; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d 491; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx 492; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi 493; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d 494; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi 495; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 496; SSE-NEXT: movd %eax, %xmm1 497; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 498; SSE-NEXT: movd %esi, %xmm0 499; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 500; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi 501; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx 502; SSE-NEXT: movd %ecx, %xmm2 503; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 504; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] 505; SSE-NEXT: movd %edx, %xmm0 506; SSE-NEXT: movd %esi, %xmm1 507; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 508; SSE-NEXT: movd %edi, %xmm0 509; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx 510; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx 511; SSE-NEXT: movd %edx, %xmm3 512; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 513; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 514; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] 515; SSE-NEXT: movd %r9d, %xmm0 516; SSE-NEXT: movd %eax, %xmm1 517; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 518; SSE-NEXT: movd %r8d, %xmm0 519; SSE-NEXT: movd %ecx, %xmm2 520; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 521; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3],xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] 522; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 523; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 524; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 525; SSE-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero 526; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 527; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] 528; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 529; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] 530; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] 531; SSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] 532; SSE-NEXT: pand %xmm2, %xmm0 533; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 534; SSE-NEXT: movd %eax, %xmm1 535; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d 536; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx 537; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi 538; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d 539; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi 540; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 541; SSE-NEXT: movd %eax, %xmm3 542; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 543; SSE-NEXT: movd %esi, %xmm1 544; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 545; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi 546; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx 547; SSE-NEXT: movd %ecx, %xmm4 548; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3],xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] 549; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] 550; SSE-NEXT: movd %edx, %xmm1 551; SSE-NEXT: movd %esi, %xmm3 552; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 553; SSE-NEXT: movd %edi, %xmm1 554; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx 555; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx 556; SSE-NEXT: movd %edx, %xmm5 557; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3],xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] 558; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3],xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7] 559; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3],xmm5[4],xmm4[4],xmm5[5],xmm4[5],xmm5[6],xmm4[6],xmm5[7],xmm4[7] 560; SSE-NEXT: movd %r9d, %xmm1 561; SSE-NEXT: movd %eax, %xmm3 562; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 563; SSE-NEXT: movd %r8d, %xmm1 564; SSE-NEXT: movd %ecx, %xmm4 565; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3],xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] 566; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] 567; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 568; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero 569; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] 570; SSE-NEXT: movd {{.*#+}} xmm6 = mem[0],zero,zero,zero 571; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 572; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1],xmm1[2],xmm6[2],xmm1[3],xmm6[3],xmm1[4],xmm6[4],xmm1[5],xmm6[5],xmm1[6],xmm6[6],xmm1[7],xmm6[7] 573; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7] 574; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] 575; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[1],xmm1[2],xmm5[2],xmm1[3],xmm5[3],xmm1[4],xmm5[4],xmm1[5],xmm5[5],xmm1[6],xmm5[6],xmm1[7],xmm5[7] 576; SSE-NEXT: pand %xmm2, %xmm1 577; SSE-NEXT: retq 578; 579; AVX1-LABEL: _clearupper32xi8a: 580; AVX1: # BB#0: 581; AVX1-NEXT: vpextrb $0, %xmm0, %eax 582; AVX1-NEXT: vpextrb $1, %xmm0, %ecx 583; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 584; AVX1-NEXT: vpextrb $0, %xmm1, %edx 585; AVX1-NEXT: vpextrb $1, %xmm1, %esi 586; AVX1-NEXT: vmovd %edx, %xmm2 587; AVX1-NEXT: vpinsrb $1, %esi, %xmm2, %xmm2 588; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4,5,6,7] 589; AVX1-NEXT: vmovd %eax, %xmm2 590; AVX1-NEXT: vpinsrb $1, %ecx, %xmm2, %xmm2 591; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5,6,7] 592; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 593; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 594; AVX1-NEXT: retq 595; 596; AVX2-LABEL: _clearupper32xi8a: 597; AVX2: # BB#0: 598; AVX2-NEXT: vpextrb $0, %xmm0, %eax 599; AVX2-NEXT: vpextrb $1, %xmm0, %ecx 600; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 601; AVX2-NEXT: vpextrb $0, %xmm1, %edx 602; AVX2-NEXT: vpextrb $1, %xmm1, %esi 603; AVX2-NEXT: vmovd %edx, %xmm2 604; AVX2-NEXT: vpinsrb $1, %esi, %xmm2, %xmm2 605; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4,5,6,7] 606; AVX2-NEXT: vmovd %eax, %xmm2 607; AVX2-NEXT: vpinsrb $1, %ecx, %xmm2, %xmm2 608; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3,4,5,6,7] 609; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 610; AVX2-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 611; AVX2-NEXT: retq 612 %x0 = extractelement <32 x i8> %0, i32 0 613 %x1 = extractelement <32 x i8> %0, i32 1 614 %x2 = extractelement <32 x i8> %0, i32 2 615 %x3 = extractelement <32 x i8> %0, i32 3 616 %x4 = extractelement <32 x i8> %0, i32 4 617 %x5 = extractelement <32 x i8> %0, i32 5 618 %x6 = extractelement <32 x i8> %0, i32 6 619 %x7 = extractelement <32 x i8> %0, i32 7 620 %x8 = extractelement <32 x i8> %0, i32 8 621 %x9 = extractelement <32 x i8> %0, i32 9 622 %x10 = extractelement <32 x i8> %0, i32 10 623 %x11 = extractelement <32 x i8> %0, i32 11 624 %x12 = extractelement <32 x i8> %0, i32 12 625 %x13 = extractelement <32 x i8> %0, i32 13 626 %x14 = extractelement <32 x i8> %0, i32 14 627 %x15 = extractelement <32 x i8> %0, i32 15 628 %x16 = extractelement <32 x i8> %0, i32 16 629 %x17 = extractelement <32 x i8> %0, i32 17 630 %x18 = extractelement <32 x i8> %0, i32 18 631 %x19 = extractelement <32 x i8> %0, i32 19 632 %x20 = extractelement <32 x i8> %0, i32 20 633 %x21 = extractelement <32 x i8> %0, i32 21 634 %x22 = extractelement <32 x i8> %0, i32 22 635 %x23 = extractelement <32 x i8> %0, i32 23 636 %x24 = extractelement <32 x i8> %0, i32 24 637 %x25 = extractelement <32 x i8> %0, i32 25 638 %x26 = extractelement <32 x i8> %0, i32 26 639 %x27 = extractelement <32 x i8> %0, i32 27 640 %x28 = extractelement <32 x i8> %0, i32 28 641 %x29 = extractelement <32 x i8> %0, i32 29 642 %x30 = extractelement <32 x i8> %0, i32 30 643 %x31 = extractelement <32 x i8> %0, i32 31 644 %trunc0 = trunc i8 %x0 to i4 645 %trunc1 = trunc i8 %x1 to i4 646 %trunc2 = trunc i8 %x2 to i4 647 %trunc3 = trunc i8 %x3 to i4 648 %trunc4 = trunc i8 %x4 to i4 649 %trunc5 = trunc i8 %x5 to i4 650 %trunc6 = trunc i8 %x6 to i4 651 %trunc7 = trunc i8 %x7 to i4 652 %trunc8 = trunc i8 %x8 to i4 653 %trunc9 = trunc i8 %x9 to i4 654 %trunc10 = trunc i8 %x10 to i4 655 %trunc11 = trunc i8 %x11 to i4 656 %trunc12 = trunc i8 %x12 to i4 657 %trunc13 = trunc i8 %x13 to i4 658 %trunc14 = trunc i8 %x14 to i4 659 %trunc15 = trunc i8 %x15 to i4 660 %trunc16 = trunc i8 %x16 to i4 661 %trunc17 = trunc i8 %x17 to i4 662 %trunc18 = trunc i8 %x18 to i4 663 %trunc19 = trunc i8 %x19 to i4 664 %trunc20 = trunc i8 %x20 to i4 665 %trunc21 = trunc i8 %x21 to i4 666 %trunc22 = trunc i8 %x22 to i4 667 %trunc23 = trunc i8 %x23 to i4 668 %trunc24 = trunc i8 %x24 to i4 669 %trunc25 = trunc i8 %x25 to i4 670 %trunc26 = trunc i8 %x26 to i4 671 %trunc27 = trunc i8 %x27 to i4 672 %trunc28 = trunc i8 %x28 to i4 673 %trunc29 = trunc i8 %x29 to i4 674 %trunc30 = trunc i8 %x30 to i4 675 %trunc31 = trunc i8 %x31 to i4 676 %ext0 = zext i4 %trunc0 to i8 677 %ext1 = zext i4 %trunc1 to i8 678 %ext2 = zext i4 %trunc2 to i8 679 %ext3 = zext i4 %trunc3 to i8 680 %ext4 = zext i4 %trunc4 to i8 681 %ext5 = zext i4 %trunc5 to i8 682 %ext6 = zext i4 %trunc6 to i8 683 %ext7 = zext i4 %trunc7 to i8 684 %ext8 = zext i4 %trunc8 to i8 685 %ext9 = zext i4 %trunc9 to i8 686 %ext10 = zext i4 %trunc10 to i8 687 %ext11 = zext i4 %trunc11 to i8 688 %ext12 = zext i4 %trunc12 to i8 689 %ext13 = zext i4 %trunc13 to i8 690 %ext14 = zext i4 %trunc14 to i8 691 %ext15 = zext i4 %trunc15 to i8 692 %ext16 = zext i4 %trunc16 to i8 693 %ext17 = zext i4 %trunc17 to i8 694 %ext18 = zext i4 %trunc18 to i8 695 %ext19 = zext i4 %trunc19 to i8 696 %ext20 = zext i4 %trunc20 to i8 697 %ext21 = zext i4 %trunc21 to i8 698 %ext22 = zext i4 %trunc22 to i8 699 %ext23 = zext i4 %trunc23 to i8 700 %ext24 = zext i4 %trunc24 to i8 701 %ext25 = zext i4 %trunc25 to i8 702 %ext26 = zext i4 %trunc26 to i8 703 %ext27 = zext i4 %trunc27 to i8 704 %ext28 = zext i4 %trunc28 to i8 705 %ext29 = zext i4 %trunc29 to i8 706 %ext30 = zext i4 %trunc30 to i8 707 %ext31 = zext i4 %trunc31 to i8 708 %v0 = insertelement <32 x i8> undef, i8 %ext0, i32 0 709 %v1 = insertelement <32 x i8> %v0, i8 %ext1, i32 1 710 %v2 = insertelement <32 x i8> %v1, i8 %ext2, i32 2 711 %v3 = insertelement <32 x i8> %v2, i8 %ext3, i32 3 712 %v4 = insertelement <32 x i8> %v3, i8 %ext4, i32 4 713 %v5 = insertelement <32 x i8> %v4, i8 %ext5, i32 5 714 %v6 = insertelement <32 x i8> %v5, i8 %ext6, i32 6 715 %v7 = insertelement <32 x i8> %v6, i8 %ext7, i32 7 716 %v8 = insertelement <32 x i8> %v7, i8 %ext8, i32 8 717 %v9 = insertelement <32 x i8> %v8, i8 %ext9, i32 9 718 %v10 = insertelement <32 x i8> %v9, i8 %ext10, i32 10 719 %v11 = insertelement <32 x i8> %v10, i8 %ext11, i32 11 720 %v12 = insertelement <32 x i8> %v11, i8 %ext12, i32 12 721 %v13 = insertelement <32 x i8> %v12, i8 %ext13, i32 13 722 %v14 = insertelement <32 x i8> %v13, i8 %ext14, i32 14 723 %v15 = insertelement <32 x i8> %v14, i8 %ext15, i32 15 724 %v16 = insertelement <32 x i8> %v15, i8 %ext16, i32 16 725 %v17 = insertelement <32 x i8> %v16, i8 %ext17, i32 17 726 %v18 = insertelement <32 x i8> %v17, i8 %ext18, i32 18 727 %v19 = insertelement <32 x i8> %v18, i8 %ext19, i32 19 728 %v20 = insertelement <32 x i8> %v19, i8 %ext20, i32 20 729 %v21 = insertelement <32 x i8> %v20, i8 %ext21, i32 21 730 %v22 = insertelement <32 x i8> %v21, i8 %ext22, i32 22 731 %v23 = insertelement <32 x i8> %v22, i8 %ext23, i32 23 732 %v24 = insertelement <32 x i8> %v23, i8 %ext24, i32 24 733 %v25 = insertelement <32 x i8> %v24, i8 %ext25, i32 25 734 %v26 = insertelement <32 x i8> %v25, i8 %ext26, i32 26 735 %v27 = insertelement <32 x i8> %v26, i8 %ext27, i32 27 736 %v28 = insertelement <32 x i8> %v27, i8 %ext28, i32 28 737 %v29 = insertelement <32 x i8> %v28, i8 %ext29, i32 29 738 %v30 = insertelement <32 x i8> %v29, i8 %ext30, i32 30 739 %v31 = insertelement <32 x i8> %v30, i8 %ext31, i32 31 740 ret <32 x i8> %v31 741} 742 743define <2 x i64> @_clearupper2xi64b(<2 x i64>) nounwind { 744; SSE-LABEL: _clearupper2xi64b: 745; SSE: # BB#0: 746; SSE-NEXT: andps {{.*}}(%rip), %xmm0 747; SSE-NEXT: retq 748; 749; AVX1-LABEL: _clearupper2xi64b: 750; AVX1: # BB#0: 751; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 752; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 753; AVX1-NEXT: retq 754; 755; AVX2-LABEL: _clearupper2xi64b: 756; AVX2: # BB#0: 757; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 758; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 759; AVX2-NEXT: retq 760 %x32 = bitcast <2 x i64> %0 to <4 x i32> 761 %r0 = insertelement <4 x i32> %x32, i32 zeroinitializer, i32 1 762 %r1 = insertelement <4 x i32> %r0, i32 zeroinitializer, i32 3 763 %r = bitcast <4 x i32> %r1 to <2 x i64> 764 ret <2 x i64> %r 765} 766 767define <4 x i64> @_clearupper4xi64b(<4 x i64>) nounwind { 768; SSE-LABEL: _clearupper4xi64b: 769; SSE: # BB#0: 770; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0] 771; SSE-NEXT: andps %xmm2, %xmm0 772; SSE-NEXT: andps %xmm2, %xmm1 773; SSE-NEXT: retq 774; 775; AVX1-LABEL: _clearupper4xi64b: 776; AVX1: # BB#0: 777; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 778; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 779; AVX1-NEXT: retq 780; 781; AVX2-LABEL: _clearupper4xi64b: 782; AVX2: # BB#0: 783; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 784; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 785; AVX2-NEXT: retq 786 %x32 = bitcast <4 x i64> %0 to <8 x i32> 787 %r0 = insertelement <8 x i32> %x32, i32 zeroinitializer, i32 1 788 %r1 = insertelement <8 x i32> %r0, i32 zeroinitializer, i32 3 789 %r2 = insertelement <8 x i32> %r1, i32 zeroinitializer, i32 5 790 %r3 = insertelement <8 x i32> %r2, i32 zeroinitializer, i32 7 791 %r = bitcast <8 x i32> %r3 to <4 x i64> 792 ret <4 x i64> %r 793} 794 795define <4 x i32> @_clearupper4xi32b(<4 x i32>) nounwind { 796; SSE-LABEL: _clearupper4xi32b: 797; SSE: # BB#0: 798; SSE-NEXT: andps {{.*}}(%rip), %xmm0 799; SSE-NEXT: retq 800; 801; AVX-LABEL: _clearupper4xi32b: 802; AVX: # BB#0: 803; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 804; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 805; AVX-NEXT: retq 806 %x16 = bitcast <4 x i32> %0 to <8 x i16> 807 %r0 = insertelement <8 x i16> %x16, i16 zeroinitializer, i32 1 808 %r1 = insertelement <8 x i16> %r0, i16 zeroinitializer, i32 3 809 %r2 = insertelement <8 x i16> %r1, i16 zeroinitializer, i32 5 810 %r3 = insertelement <8 x i16> %r2, i16 zeroinitializer, i32 7 811 %r = bitcast <8 x i16> %r3 to <4 x i32> 812 ret <4 x i32> %r 813} 814 815define <8 x i32> @_clearupper8xi32b(<8 x i32>) nounwind { 816; SSE-LABEL: _clearupper8xi32b: 817; SSE: # BB#0: 818; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,0,65535,0,65535,0] 819; SSE-NEXT: andps %xmm2, %xmm0 820; SSE-NEXT: andps %xmm2, %xmm1 821; SSE-NEXT: retq 822; 823; AVX1-LABEL: _clearupper8xi32b: 824; AVX1: # BB#0: 825; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 826; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 827; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm0[4,5,6,7] 828; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 829; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 830; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 831; AVX1-NEXT: retq 832; 833; AVX2-LABEL: _clearupper8xi32b: 834; AVX2: # BB#0: 835; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 836; AVX2-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 837; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm0[4,5,6,7] 838; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 839; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 840; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0 841; AVX2-NEXT: retq 842 %x16 = bitcast <8 x i32> %0 to <16 x i16> 843 %r0 = insertelement <16 x i16> %x16, i16 zeroinitializer, i32 1 844 %r1 = insertelement <16 x i16> %r0, i16 zeroinitializer, i32 3 845 %r2 = insertelement <16 x i16> %r1, i16 zeroinitializer, i32 5 846 %r3 = insertelement <16 x i16> %r2, i16 zeroinitializer, i32 7 847 %r4 = insertelement <16 x i16> %r3, i16 zeroinitializer, i32 9 848 %r5 = insertelement <16 x i16> %r4, i16 zeroinitializer, i32 11 849 %r6 = insertelement <16 x i16> %r5, i16 zeroinitializer, i32 13 850 %r7 = insertelement <16 x i16> %r6, i16 zeroinitializer, i32 15 851 %r = bitcast <16 x i16> %r7 to <8 x i32> 852 ret <8 x i32> %r 853} 854 855define <8 x i16> @_clearupper8xi16b(<8 x i16>) nounwind { 856; SSE-LABEL: _clearupper8xi16b: 857; SSE: # BB#0: 858; SSE-NEXT: andps {{.*}}(%rip), %xmm0 859; SSE-NEXT: retq 860; 861; AVX-LABEL: _clearupper8xi16b: 862; AVX: # BB#0: 863; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 864; AVX-NEXT: retq 865 %x8 = bitcast <8 x i16> %0 to <16 x i8> 866 %r0 = insertelement <16 x i8> %x8, i8 zeroinitializer, i32 1 867 %r1 = insertelement <16 x i8> %r0, i8 zeroinitializer, i32 3 868 %r2 = insertelement <16 x i8> %r1, i8 zeroinitializer, i32 5 869 %r3 = insertelement <16 x i8> %r2, i8 zeroinitializer, i32 7 870 %r4 = insertelement <16 x i8> %r3, i8 zeroinitializer, i32 9 871 %r5 = insertelement <16 x i8> %r4, i8 zeroinitializer, i32 11 872 %r6 = insertelement <16 x i8> %r5, i8 zeroinitializer, i32 13 873 %r7 = insertelement <16 x i8> %r6, i8 zeroinitializer, i32 15 874 %r = bitcast <16 x i8> %r7 to <8 x i16> 875 ret <8 x i16> %r 876} 877 878define <16 x i16> @_clearupper16xi16b(<16 x i16>) nounwind { 879; SSE-LABEL: _clearupper16xi16b: 880; SSE: # BB#0: 881; SSE-NEXT: movaps {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] 882; SSE-NEXT: andps %xmm2, %xmm0 883; SSE-NEXT: andps %xmm2, %xmm1 884; SSE-NEXT: retq 885; 886; AVX1-LABEL: _clearupper16xi16b: 887; AVX1: # BB#0: 888; AVX1-NEXT: vmovaps {{.*#+}} xmm1 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] 889; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm2 890; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm0[4,5,6,7] 891; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 892; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0 893; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 894; AVX1-NEXT: retq 895; 896; AVX2-LABEL: _clearupper16xi16b: 897; AVX2: # BB#0: 898; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] 899; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm2 900; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm0[4,5,6,7] 901; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 902; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 903; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0 904; AVX2-NEXT: retq 905 %x8 = bitcast <16 x i16> %0 to <32 x i8> 906 %r0 = insertelement <32 x i8> %x8, i8 zeroinitializer, i32 1 907 %r1 = insertelement <32 x i8> %r0, i8 zeroinitializer, i32 3 908 %r2 = insertelement <32 x i8> %r1, i8 zeroinitializer, i32 5 909 %r3 = insertelement <32 x i8> %r2, i8 zeroinitializer, i32 7 910 %r4 = insertelement <32 x i8> %r3, i8 zeroinitializer, i32 9 911 %r5 = insertelement <32 x i8> %r4, i8 zeroinitializer, i32 11 912 %r6 = insertelement <32 x i8> %r5, i8 zeroinitializer, i32 13 913 %r7 = insertelement <32 x i8> %r6, i8 zeroinitializer, i32 15 914 %r8 = insertelement <32 x i8> %r7, i8 zeroinitializer, i32 17 915 %r9 = insertelement <32 x i8> %r8, i8 zeroinitializer, i32 19 916 %r10 = insertelement <32 x i8> %r9, i8 zeroinitializer, i32 21 917 %r11 = insertelement <32 x i8> %r10, i8 zeroinitializer, i32 23 918 %r12 = insertelement <32 x i8> %r11, i8 zeroinitializer, i32 25 919 %r13 = insertelement <32 x i8> %r12, i8 zeroinitializer, i32 27 920 %r14 = insertelement <32 x i8> %r13, i8 zeroinitializer, i32 29 921 %r15 = insertelement <32 x i8> %r14, i8 zeroinitializer, i32 31 922 %r = bitcast <32 x i8> %r15 to <16 x i16> 923 ret <16 x i16> %r 924} 925 926define <16 x i8> @_clearupper16xi8b(<16 x i8>) nounwind { 927; SSE-LABEL: _clearupper16xi8b: 928; SSE: # BB#0: 929; SSE-NEXT: pushq %r14 930; SSE-NEXT: pushq %rbx 931; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] 932; SSE-NEXT: movd %xmm0, %rcx 933; SSE-NEXT: movq %rcx, %r8 934; SSE-NEXT: movq %rcx, %r9 935; SSE-NEXT: movq %rcx, %r10 936; SSE-NEXT: movq %rcx, %rax 937; SSE-NEXT: movq %rcx, %rdx 938; SSE-NEXT: movq %rcx, %rsi 939; SSE-NEXT: movq %rcx, %rdi 940; SSE-NEXT: andb $15, %cl 941; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 942; SSE-NEXT: movd %xmm1, %rcx 943; SSE-NEXT: shrq $56, %rdi 944; SSE-NEXT: andb $15, %dil 945; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 946; SSE-NEXT: movq %rcx, %r11 947; SSE-NEXT: shrq $48, %rsi 948; SSE-NEXT: andb $15, %sil 949; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 950; SSE-NEXT: movq %rcx, %r14 951; SSE-NEXT: shrq $40, %rdx 952; SSE-NEXT: andb $15, %dl 953; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 954; SSE-NEXT: movq %rcx, %rdx 955; SSE-NEXT: shrq $32, %rax 956; SSE-NEXT: andb $15, %al 957; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 958; SSE-NEXT: movq %rcx, %rax 959; SSE-NEXT: shrq $24, %r10 960; SSE-NEXT: andb $15, %r10b 961; SSE-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 962; SSE-NEXT: movq %rcx, %rdi 963; SSE-NEXT: shrq $16, %r9 964; SSE-NEXT: andb $15, %r9b 965; SSE-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 966; SSE-NEXT: movq %rcx, %rsi 967; SSE-NEXT: shrq $8, %r8 968; SSE-NEXT: andb $15, %r8b 969; SSE-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 970; SSE-NEXT: movq %rcx, %rbx 971; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 972; SSE-NEXT: andb $15, %cl 973; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 974; SSE-NEXT: shrq $56, %rbx 975; SSE-NEXT: andb $15, %bl 976; SSE-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 977; SSE-NEXT: shrq $48, %rsi 978; SSE-NEXT: andb $15, %sil 979; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 980; SSE-NEXT: shrq $40, %rdi 981; SSE-NEXT: andb $15, %dil 982; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 983; SSE-NEXT: shrq $32, %rax 984; SSE-NEXT: andb $15, %al 985; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 986; SSE-NEXT: shrq $24, %rdx 987; SSE-NEXT: andb $15, %dl 988; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 989; SSE-NEXT: shrq $16, %r14 990; SSE-NEXT: andb $15, %r14b 991; SSE-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 992; SSE-NEXT: shrq $8, %r11 993; SSE-NEXT: andb $15, %r11b 994; SSE-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 995; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 996; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 997; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero 998; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 999; SSE-NEXT: popq %rbx 1000; SSE-NEXT: popq %r14 1001; SSE-NEXT: retq 1002; 1003; AVX-LABEL: _clearupper16xi8b: 1004; AVX: # BB#0: 1005; AVX-NEXT: pushq %rbp 1006; AVX-NEXT: pushq %r15 1007; AVX-NEXT: pushq %r14 1008; AVX-NEXT: pushq %r13 1009; AVX-NEXT: pushq %r12 1010; AVX-NEXT: pushq %rbx 1011; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) 1012; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rcx 1013; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rdx 1014; AVX-NEXT: movq %rcx, %r8 1015; AVX-NEXT: movq %rcx, %r9 1016; AVX-NEXT: movq %rcx, %r10 1017; AVX-NEXT: movq %rcx, %r11 1018; AVX-NEXT: movq %rcx, %r14 1019; AVX-NEXT: movq %rcx, %r15 1020; AVX-NEXT: movq %rdx, %r12 1021; AVX-NEXT: movq %rdx, %r13 1022; AVX-NEXT: movq %rdx, %rdi 1023; AVX-NEXT: movq %rdx, %rax 1024; AVX-NEXT: movq %rdx, %rsi 1025; AVX-NEXT: movq %rdx, %rbx 1026; AVX-NEXT: movq %rdx, %rbp 1027; AVX-NEXT: andb $15, %dl 1028; AVX-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1029; AVX-NEXT: movq %rcx, %rdx 1030; AVX-NEXT: andb $15, %cl 1031; AVX-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1032; AVX-NEXT: shrq $56, %rbp 1033; AVX-NEXT: andb $15, %bpl 1034; AVX-NEXT: movb %bpl, -{{[0-9]+}}(%rsp) 1035; AVX-NEXT: shrq $48, %rbx 1036; AVX-NEXT: andb $15, %bl 1037; AVX-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 1038; AVX-NEXT: shrq $40, %rsi 1039; AVX-NEXT: andb $15, %sil 1040; AVX-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1041; AVX-NEXT: shrq $32, %rax 1042; AVX-NEXT: andb $15, %al 1043; AVX-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1044; AVX-NEXT: shrq $24, %rdi 1045; AVX-NEXT: andb $15, %dil 1046; AVX-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1047; AVX-NEXT: shrq $16, %r13 1048; AVX-NEXT: andb $15, %r13b 1049; AVX-NEXT: movb %r13b, -{{[0-9]+}}(%rsp) 1050; AVX-NEXT: shrq $8, %r12 1051; AVX-NEXT: andb $15, %r12b 1052; AVX-NEXT: movb %r12b, -{{[0-9]+}}(%rsp) 1053; AVX-NEXT: shrq $56, %rdx 1054; AVX-NEXT: andb $15, %dl 1055; AVX-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1056; AVX-NEXT: shrq $48, %r15 1057; AVX-NEXT: andb $15, %r15b 1058; AVX-NEXT: movb %r15b, -{{[0-9]+}}(%rsp) 1059; AVX-NEXT: shrq $40, %r14 1060; AVX-NEXT: andb $15, %r14b 1061; AVX-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 1062; AVX-NEXT: shrq $32, %r11 1063; AVX-NEXT: andb $15, %r11b 1064; AVX-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 1065; AVX-NEXT: shrq $24, %r10 1066; AVX-NEXT: andb $15, %r10b 1067; AVX-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 1068; AVX-NEXT: shrq $16, %r9 1069; AVX-NEXT: andb $15, %r9b 1070; AVX-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 1071; AVX-NEXT: shrq $8, %r8 1072; AVX-NEXT: andb $15, %r8b 1073; AVX-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 1074; AVX-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1075; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0 1076; AVX-NEXT: popq %rbx 1077; AVX-NEXT: popq %r12 1078; AVX-NEXT: popq %r13 1079; AVX-NEXT: popq %r14 1080; AVX-NEXT: popq %r15 1081; AVX-NEXT: popq %rbp 1082; AVX-NEXT: retq 1083 %x4 = bitcast <16 x i8> %0 to <32 x i4> 1084 %r0 = insertelement <32 x i4> %x4, i4 zeroinitializer, i32 1 1085 %r1 = insertelement <32 x i4> %r0, i4 zeroinitializer, i32 3 1086 %r2 = insertelement <32 x i4> %r1, i4 zeroinitializer, i32 5 1087 %r3 = insertelement <32 x i4> %r2, i4 zeroinitializer, i32 7 1088 %r4 = insertelement <32 x i4> %r3, i4 zeroinitializer, i32 9 1089 %r5 = insertelement <32 x i4> %r4, i4 zeroinitializer, i32 11 1090 %r6 = insertelement <32 x i4> %r5, i4 zeroinitializer, i32 13 1091 %r7 = insertelement <32 x i4> %r6, i4 zeroinitializer, i32 15 1092 %r8 = insertelement <32 x i4> %r7, i4 zeroinitializer, i32 17 1093 %r9 = insertelement <32 x i4> %r8, i4 zeroinitializer, i32 19 1094 %r10 = insertelement <32 x i4> %r9, i4 zeroinitializer, i32 21 1095 %r11 = insertelement <32 x i4> %r10, i4 zeroinitializer, i32 23 1096 %r12 = insertelement <32 x i4> %r11, i4 zeroinitializer, i32 25 1097 %r13 = insertelement <32 x i4> %r12, i4 zeroinitializer, i32 27 1098 %r14 = insertelement <32 x i4> %r13, i4 zeroinitializer, i32 29 1099 %r15 = insertelement <32 x i4> %r14, i4 zeroinitializer, i32 31 1100 %r = bitcast <32 x i4> %r15 to <16 x i8> 1101 ret <16 x i8> %r 1102} 1103 1104define <32 x i8> @_clearupper32xi8b(<32 x i8>) nounwind { 1105; SSE-LABEL: _clearupper32xi8b: 1106; SSE: # BB#0: 1107; SSE-NEXT: pushq %r14 1108; SSE-NEXT: pushq %rbx 1109; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1] 1110; SSE-NEXT: movd %xmm0, %rcx 1111; SSE-NEXT: movq %rcx, %r8 1112; SSE-NEXT: movq %rcx, %r9 1113; SSE-NEXT: movq %rcx, %r10 1114; SSE-NEXT: movq %rcx, %rax 1115; SSE-NEXT: movq %rcx, %rdx 1116; SSE-NEXT: movq %rcx, %rsi 1117; SSE-NEXT: movq %rcx, %rdi 1118; SSE-NEXT: andb $15, %cl 1119; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1120; SSE-NEXT: movd %xmm2, %rcx 1121; SSE-NEXT: shrq $56, %rdi 1122; SSE-NEXT: andb $15, %dil 1123; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1124; SSE-NEXT: movq %rcx, %r11 1125; SSE-NEXT: shrq $48, %rsi 1126; SSE-NEXT: andb $15, %sil 1127; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1128; SSE-NEXT: movq %rcx, %r14 1129; SSE-NEXT: shrq $40, %rdx 1130; SSE-NEXT: andb $15, %dl 1131; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1132; SSE-NEXT: movq %rcx, %rdx 1133; SSE-NEXT: shrq $32, %rax 1134; SSE-NEXT: andb $15, %al 1135; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1136; SSE-NEXT: movq %rcx, %rax 1137; SSE-NEXT: shrq $24, %r10 1138; SSE-NEXT: andb $15, %r10b 1139; SSE-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 1140; SSE-NEXT: movq %rcx, %rdi 1141; SSE-NEXT: shrq $16, %r9 1142; SSE-NEXT: andb $15, %r9b 1143; SSE-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 1144; SSE-NEXT: movq %rcx, %rsi 1145; SSE-NEXT: shrq $8, %r8 1146; SSE-NEXT: andb $15, %r8b 1147; SSE-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 1148; SSE-NEXT: movq %rcx, %rbx 1149; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1150; SSE-NEXT: andb $15, %cl 1151; SSE-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1152; SSE-NEXT: shrq $56, %rbx 1153; SSE-NEXT: andb $15, %bl 1154; SSE-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 1155; SSE-NEXT: shrq $48, %rsi 1156; SSE-NEXT: andb $15, %sil 1157; SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1158; SSE-NEXT: shrq $40, %rdi 1159; SSE-NEXT: andb $15, %dil 1160; SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1161; SSE-NEXT: shrq $32, %rax 1162; SSE-NEXT: andb $15, %al 1163; SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1164; SSE-NEXT: shrq $24, %rdx 1165; SSE-NEXT: andb $15, %dl 1166; SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1167; SSE-NEXT: shrq $16, %r14 1168; SSE-NEXT: andb $15, %r14b 1169; SSE-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 1170; SSE-NEXT: shrq $8, %r11 1171; SSE-NEXT: andb $15, %r11b 1172; SSE-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 1173; SSE-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1174; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero 1175; SSE-NEXT: movq {{.*#+}} xmm2 = mem[0],zero 1176; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] 1177; SSE-NEXT: popq %rbx 1178; SSE-NEXT: popq %r14 1179; SSE-NEXT: retq 1180; 1181; AVX1-LABEL: _clearupper32xi8b: 1182; AVX1: # BB#0: 1183; AVX1-NEXT: pushq %rbp 1184; AVX1-NEXT: pushq %r15 1185; AVX1-NEXT: pushq %r14 1186; AVX1-NEXT: pushq %r13 1187; AVX1-NEXT: pushq %r12 1188; AVX1-NEXT: pushq %rbx 1189; AVX1-NEXT: vpextrq $1, %xmm0, -{{[0-9]+}}(%rsp) 1190; AVX1-NEXT: vmovq %xmm0, -{{[0-9]+}}(%rsp) 1191; AVX1-NEXT: movq -{{[0-9]+}}(%rsp), %rcx 1192; AVX1-NEXT: movq -{{[0-9]+}}(%rsp), %rdx 1193; AVX1-NEXT: movq %rcx, %r8 1194; AVX1-NEXT: movq %rcx, %r9 1195; AVX1-NEXT: movq %rcx, %r10 1196; AVX1-NEXT: movq %rcx, %r11 1197; AVX1-NEXT: movq %rcx, %r14 1198; AVX1-NEXT: movq %rcx, %r15 1199; AVX1-NEXT: movq %rdx, %r12 1200; AVX1-NEXT: movq %rdx, %r13 1201; AVX1-NEXT: movq %rdx, %rdi 1202; AVX1-NEXT: movq %rdx, %rax 1203; AVX1-NEXT: movq %rdx, %rsi 1204; AVX1-NEXT: movq %rdx, %rbx 1205; AVX1-NEXT: movq %rdx, %rbp 1206; AVX1-NEXT: andb $15, %dl 1207; AVX1-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1208; AVX1-NEXT: movq %rcx, %rdx 1209; AVX1-NEXT: andb $15, %cl 1210; AVX1-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1211; AVX1-NEXT: shrq $56, %rbp 1212; AVX1-NEXT: andb $15, %bpl 1213; AVX1-NEXT: movb %bpl, -{{[0-9]+}}(%rsp) 1214; AVX1-NEXT: shrq $48, %rbx 1215; AVX1-NEXT: andb $15, %bl 1216; AVX1-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 1217; AVX1-NEXT: shrq $40, %rsi 1218; AVX1-NEXT: andb $15, %sil 1219; AVX1-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1220; AVX1-NEXT: shrq $32, %rax 1221; AVX1-NEXT: andb $15, %al 1222; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1223; AVX1-NEXT: shrq $24, %rdi 1224; AVX1-NEXT: andb $15, %dil 1225; AVX1-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1226; AVX1-NEXT: shrq $16, %r13 1227; AVX1-NEXT: andb $15, %r13b 1228; AVX1-NEXT: movb %r13b, -{{[0-9]+}}(%rsp) 1229; AVX1-NEXT: shrq $8, %r12 1230; AVX1-NEXT: andb $15, %r12b 1231; AVX1-NEXT: movb %r12b, -{{[0-9]+}}(%rsp) 1232; AVX1-NEXT: shrq $8, %r8 1233; AVX1-NEXT: shrq $16, %r9 1234; AVX1-NEXT: shrq $24, %r10 1235; AVX1-NEXT: shrq $32, %r11 1236; AVX1-NEXT: shrq $40, %r14 1237; AVX1-NEXT: shrq $48, %r15 1238; AVX1-NEXT: shrq $56, %rdx 1239; AVX1-NEXT: andb $15, %dl 1240; AVX1-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1241; AVX1-NEXT: andb $15, %r15b 1242; AVX1-NEXT: movb %r15b, -{{[0-9]+}}(%rsp) 1243; AVX1-NEXT: andb $15, %r14b 1244; AVX1-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 1245; AVX1-NEXT: andb $15, %r11b 1246; AVX1-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 1247; AVX1-NEXT: andb $15, %r10b 1248; AVX1-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 1249; AVX1-NEXT: andb $15, %r9b 1250; AVX1-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 1251; AVX1-NEXT: andb $15, %r8b 1252; AVX1-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 1253; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 1254; AVX1-NEXT: vmovq %xmm0, %rax 1255; AVX1-NEXT: movq %rax, %rcx 1256; AVX1-NEXT: movq %rax, %rdx 1257; AVX1-NEXT: movq %rax, %rsi 1258; AVX1-NEXT: movq %rax, %rdi 1259; AVX1-NEXT: movl %eax, %ebp 1260; AVX1-NEXT: movl %eax, %ebx 1261; AVX1-NEXT: vmovd %eax, %xmm1 1262; AVX1-NEXT: shrl $8, %eax 1263; AVX1-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1264; AVX1-NEXT: shrl $16, %ebx 1265; AVX1-NEXT: vpinsrb $2, %ebx, %xmm1, %xmm1 1266; AVX1-NEXT: shrl $24, %ebp 1267; AVX1-NEXT: vpinsrb $3, %ebp, %xmm1, %xmm1 1268; AVX1-NEXT: shrq $32, %rdi 1269; AVX1-NEXT: vpinsrb $4, %edi, %xmm1, %xmm1 1270; AVX1-NEXT: shrq $40, %rsi 1271; AVX1-NEXT: vpinsrb $5, %esi, %xmm1, %xmm1 1272; AVX1-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1273; AVX1-NEXT: vmovdqa -{{[0-9]+}}(%rsp), %xmm2 1274; AVX1-NEXT: shrq $48, %rdx 1275; AVX1-NEXT: vpinsrb $6, %edx, %xmm1, %xmm1 1276; AVX1-NEXT: vpextrq $1, %xmm0, %rax 1277; AVX1-NEXT: shrq $56, %rcx 1278; AVX1-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm0 1279; AVX1-NEXT: movl %eax, %ecx 1280; AVX1-NEXT: shrl $8, %ecx 1281; AVX1-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0 1282; AVX1-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0 1283; AVX1-NEXT: movl %eax, %ecx 1284; AVX1-NEXT: shrl $16, %ecx 1285; AVX1-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0 1286; AVX1-NEXT: movl %eax, %ecx 1287; AVX1-NEXT: shrl $24, %ecx 1288; AVX1-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0 1289; AVX1-NEXT: movq %rax, %rcx 1290; AVX1-NEXT: shrq $32, %rcx 1291; AVX1-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0 1292; AVX1-NEXT: movq %rax, %rcx 1293; AVX1-NEXT: shrq $40, %rcx 1294; AVX1-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0 1295; AVX1-NEXT: movq %rax, %rcx 1296; AVX1-NEXT: shrq $48, %rcx 1297; AVX1-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 1298; AVX1-NEXT: vmovq %xmm2, %rcx 1299; AVX1-NEXT: shrq $56, %rax 1300; AVX1-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 1301; AVX1-NEXT: movl %ecx, %eax 1302; AVX1-NEXT: shrl $8, %eax 1303; AVX1-NEXT: vmovd %ecx, %xmm1 1304; AVX1-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1305; AVX1-NEXT: movl %ecx, %eax 1306; AVX1-NEXT: shrl $16, %eax 1307; AVX1-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1 1308; AVX1-NEXT: movl %ecx, %eax 1309; AVX1-NEXT: shrl $24, %eax 1310; AVX1-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1 1311; AVX1-NEXT: movq %rcx, %rax 1312; AVX1-NEXT: shrq $32, %rax 1313; AVX1-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1 1314; AVX1-NEXT: movq %rcx, %rax 1315; AVX1-NEXT: shrq $40, %rax 1316; AVX1-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1 1317; AVX1-NEXT: movq %rcx, %rax 1318; AVX1-NEXT: shrq $48, %rax 1319; AVX1-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1 1320; AVX1-NEXT: vpextrq $1, %xmm2, %rax 1321; AVX1-NEXT: shrq $56, %rcx 1322; AVX1-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm1 1323; AVX1-NEXT: movl %eax, %ecx 1324; AVX1-NEXT: shrl $8, %ecx 1325; AVX1-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1 1326; AVX1-NEXT: vpinsrb $9, %ecx, %xmm1, %xmm1 1327; AVX1-NEXT: movl %eax, %ecx 1328; AVX1-NEXT: shrl $16, %ecx 1329; AVX1-NEXT: vpinsrb $10, %ecx, %xmm1, %xmm1 1330; AVX1-NEXT: movl %eax, %ecx 1331; AVX1-NEXT: shrl $24, %ecx 1332; AVX1-NEXT: vpinsrb $11, %ecx, %xmm1, %xmm1 1333; AVX1-NEXT: movq %rax, %rcx 1334; AVX1-NEXT: shrq $32, %rcx 1335; AVX1-NEXT: vpinsrb $12, %ecx, %xmm1, %xmm1 1336; AVX1-NEXT: movq %rax, %rcx 1337; AVX1-NEXT: shrq $40, %rcx 1338; AVX1-NEXT: vpinsrb $13, %ecx, %xmm1, %xmm1 1339; AVX1-NEXT: movq %rax, %rcx 1340; AVX1-NEXT: shrq $48, %rcx 1341; AVX1-NEXT: vpinsrb $14, %ecx, %xmm1, %xmm1 1342; AVX1-NEXT: shrq $56, %rax 1343; AVX1-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1 1344; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 1345; AVX1-NEXT: popq %rbx 1346; AVX1-NEXT: popq %r12 1347; AVX1-NEXT: popq %r13 1348; AVX1-NEXT: popq %r14 1349; AVX1-NEXT: popq %r15 1350; AVX1-NEXT: popq %rbp 1351; AVX1-NEXT: retq 1352; 1353; AVX2-LABEL: _clearupper32xi8b: 1354; AVX2: # BB#0: 1355; AVX2-NEXT: pushq %rbp 1356; AVX2-NEXT: pushq %r15 1357; AVX2-NEXT: pushq %r14 1358; AVX2-NEXT: pushq %r13 1359; AVX2-NEXT: pushq %r12 1360; AVX2-NEXT: pushq %rbx 1361; AVX2-NEXT: vpextrq $1, %xmm0, -{{[0-9]+}}(%rsp) 1362; AVX2-NEXT: vmovq %xmm0, -{{[0-9]+}}(%rsp) 1363; AVX2-NEXT: movq -{{[0-9]+}}(%rsp), %rcx 1364; AVX2-NEXT: movq -{{[0-9]+}}(%rsp), %rdx 1365; AVX2-NEXT: movq %rcx, %r8 1366; AVX2-NEXT: movq %rcx, %r9 1367; AVX2-NEXT: movq %rcx, %r10 1368; AVX2-NEXT: movq %rcx, %r11 1369; AVX2-NEXT: movq %rcx, %r14 1370; AVX2-NEXT: movq %rcx, %r15 1371; AVX2-NEXT: movq %rdx, %r12 1372; AVX2-NEXT: movq %rdx, %r13 1373; AVX2-NEXT: movq %rdx, %rdi 1374; AVX2-NEXT: movq %rdx, %rax 1375; AVX2-NEXT: movq %rdx, %rsi 1376; AVX2-NEXT: movq %rdx, %rbx 1377; AVX2-NEXT: movq %rdx, %rbp 1378; AVX2-NEXT: andb $15, %dl 1379; AVX2-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1380; AVX2-NEXT: movq %rcx, %rdx 1381; AVX2-NEXT: andb $15, %cl 1382; AVX2-NEXT: movb %cl, -{{[0-9]+}}(%rsp) 1383; AVX2-NEXT: shrq $56, %rbp 1384; AVX2-NEXT: andb $15, %bpl 1385; AVX2-NEXT: movb %bpl, -{{[0-9]+}}(%rsp) 1386; AVX2-NEXT: shrq $48, %rbx 1387; AVX2-NEXT: andb $15, %bl 1388; AVX2-NEXT: movb %bl, -{{[0-9]+}}(%rsp) 1389; AVX2-NEXT: shrq $40, %rsi 1390; AVX2-NEXT: andb $15, %sil 1391; AVX2-NEXT: movb %sil, -{{[0-9]+}}(%rsp) 1392; AVX2-NEXT: shrq $32, %rax 1393; AVX2-NEXT: andb $15, %al 1394; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp) 1395; AVX2-NEXT: shrq $24, %rdi 1396; AVX2-NEXT: andb $15, %dil 1397; AVX2-NEXT: movb %dil, -{{[0-9]+}}(%rsp) 1398; AVX2-NEXT: shrq $16, %r13 1399; AVX2-NEXT: andb $15, %r13b 1400; AVX2-NEXT: movb %r13b, -{{[0-9]+}}(%rsp) 1401; AVX2-NEXT: shrq $8, %r12 1402; AVX2-NEXT: andb $15, %r12b 1403; AVX2-NEXT: movb %r12b, -{{[0-9]+}}(%rsp) 1404; AVX2-NEXT: shrq $8, %r8 1405; AVX2-NEXT: shrq $16, %r9 1406; AVX2-NEXT: shrq $24, %r10 1407; AVX2-NEXT: shrq $32, %r11 1408; AVX2-NEXT: shrq $40, %r14 1409; AVX2-NEXT: shrq $48, %r15 1410; AVX2-NEXT: shrq $56, %rdx 1411; AVX2-NEXT: andb $15, %dl 1412; AVX2-NEXT: movb %dl, -{{[0-9]+}}(%rsp) 1413; AVX2-NEXT: andb $15, %r15b 1414; AVX2-NEXT: movb %r15b, -{{[0-9]+}}(%rsp) 1415; AVX2-NEXT: andb $15, %r14b 1416; AVX2-NEXT: movb %r14b, -{{[0-9]+}}(%rsp) 1417; AVX2-NEXT: andb $15, %r11b 1418; AVX2-NEXT: movb %r11b, -{{[0-9]+}}(%rsp) 1419; AVX2-NEXT: andb $15, %r10b 1420; AVX2-NEXT: movb %r10b, -{{[0-9]+}}(%rsp) 1421; AVX2-NEXT: andb $15, %r9b 1422; AVX2-NEXT: movb %r9b, -{{[0-9]+}}(%rsp) 1423; AVX2-NEXT: andb $15, %r8b 1424; AVX2-NEXT: movb %r8b, -{{[0-9]+}}(%rsp) 1425; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 1426; AVX2-NEXT: vmovq %xmm0, %rax 1427; AVX2-NEXT: movq %rax, %rcx 1428; AVX2-NEXT: movq %rax, %rdx 1429; AVX2-NEXT: movq %rax, %rsi 1430; AVX2-NEXT: movq %rax, %rdi 1431; AVX2-NEXT: movl %eax, %ebp 1432; AVX2-NEXT: movl %eax, %ebx 1433; AVX2-NEXT: vmovd %eax, %xmm1 1434; AVX2-NEXT: shrl $8, %eax 1435; AVX2-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1436; AVX2-NEXT: shrl $16, %ebx 1437; AVX2-NEXT: vpinsrb $2, %ebx, %xmm1, %xmm1 1438; AVX2-NEXT: shrl $24, %ebp 1439; AVX2-NEXT: vpinsrb $3, %ebp, %xmm1, %xmm1 1440; AVX2-NEXT: shrq $32, %rdi 1441; AVX2-NEXT: vpinsrb $4, %edi, %xmm1, %xmm1 1442; AVX2-NEXT: shrq $40, %rsi 1443; AVX2-NEXT: vpinsrb $5, %esi, %xmm1, %xmm1 1444; AVX2-NEXT: movb $0, -{{[0-9]+}}(%rsp) 1445; AVX2-NEXT: vmovdqa -{{[0-9]+}}(%rsp), %xmm2 1446; AVX2-NEXT: shrq $48, %rdx 1447; AVX2-NEXT: vpinsrb $6, %edx, %xmm1, %xmm1 1448; AVX2-NEXT: vpextrq $1, %xmm0, %rax 1449; AVX2-NEXT: shrq $56, %rcx 1450; AVX2-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm0 1451; AVX2-NEXT: movl %eax, %ecx 1452; AVX2-NEXT: shrl $8, %ecx 1453; AVX2-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0 1454; AVX2-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0 1455; AVX2-NEXT: movl %eax, %ecx 1456; AVX2-NEXT: shrl $16, %ecx 1457; AVX2-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0 1458; AVX2-NEXT: movl %eax, %ecx 1459; AVX2-NEXT: shrl $24, %ecx 1460; AVX2-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0 1461; AVX2-NEXT: movq %rax, %rcx 1462; AVX2-NEXT: shrq $32, %rcx 1463; AVX2-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0 1464; AVX2-NEXT: movq %rax, %rcx 1465; AVX2-NEXT: shrq $40, %rcx 1466; AVX2-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0 1467; AVX2-NEXT: movq %rax, %rcx 1468; AVX2-NEXT: shrq $48, %rcx 1469; AVX2-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 1470; AVX2-NEXT: vmovq %xmm2, %rcx 1471; AVX2-NEXT: shrq $56, %rax 1472; AVX2-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 1473; AVX2-NEXT: movl %ecx, %eax 1474; AVX2-NEXT: shrl $8, %eax 1475; AVX2-NEXT: vmovd %ecx, %xmm1 1476; AVX2-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 1477; AVX2-NEXT: movl %ecx, %eax 1478; AVX2-NEXT: shrl $16, %eax 1479; AVX2-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1 1480; AVX2-NEXT: movl %ecx, %eax 1481; AVX2-NEXT: shrl $24, %eax 1482; AVX2-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1 1483; AVX2-NEXT: movq %rcx, %rax 1484; AVX2-NEXT: shrq $32, %rax 1485; AVX2-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1 1486; AVX2-NEXT: movq %rcx, %rax 1487; AVX2-NEXT: shrq $40, %rax 1488; AVX2-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1 1489; AVX2-NEXT: movq %rcx, %rax 1490; AVX2-NEXT: shrq $48, %rax 1491; AVX2-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1 1492; AVX2-NEXT: vpextrq $1, %xmm2, %rax 1493; AVX2-NEXT: shrq $56, %rcx 1494; AVX2-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm1 1495; AVX2-NEXT: movl %eax, %ecx 1496; AVX2-NEXT: shrl $8, %ecx 1497; AVX2-NEXT: vpinsrb $8, %eax, %xmm1, %xmm1 1498; AVX2-NEXT: vpinsrb $9, %ecx, %xmm1, %xmm1 1499; AVX2-NEXT: movl %eax, %ecx 1500; AVX2-NEXT: shrl $16, %ecx 1501; AVX2-NEXT: vpinsrb $10, %ecx, %xmm1, %xmm1 1502; AVX2-NEXT: movl %eax, %ecx 1503; AVX2-NEXT: shrl $24, %ecx 1504; AVX2-NEXT: vpinsrb $11, %ecx, %xmm1, %xmm1 1505; AVX2-NEXT: movq %rax, %rcx 1506; AVX2-NEXT: shrq $32, %rcx 1507; AVX2-NEXT: vpinsrb $12, %ecx, %xmm1, %xmm1 1508; AVX2-NEXT: movq %rax, %rcx 1509; AVX2-NEXT: shrq $40, %rcx 1510; AVX2-NEXT: vpinsrb $13, %ecx, %xmm1, %xmm1 1511; AVX2-NEXT: movq %rax, %rcx 1512; AVX2-NEXT: shrq $48, %rcx 1513; AVX2-NEXT: vpinsrb $14, %ecx, %xmm1, %xmm1 1514; AVX2-NEXT: shrq $56, %rax 1515; AVX2-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1 1516; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 1517; AVX2-NEXT: popq %rbx 1518; AVX2-NEXT: popq %r12 1519; AVX2-NEXT: popq %r13 1520; AVX2-NEXT: popq %r14 1521; AVX2-NEXT: popq %r15 1522; AVX2-NEXT: popq %rbp 1523; AVX2-NEXT: retq 1524 %x4 = bitcast <32 x i8> %0 to <64 x i4> 1525 %r0 = insertelement <64 x i4> %x4, i4 zeroinitializer, i32 1 1526 %r1 = insertelement <64 x i4> %r0, i4 zeroinitializer, i32 3 1527 %r2 = insertelement <64 x i4> %r1, i4 zeroinitializer, i32 5 1528 %r3 = insertelement <64 x i4> %r2, i4 zeroinitializer, i32 7 1529 %r4 = insertelement <64 x i4> %r3, i4 zeroinitializer, i32 9 1530 %r5 = insertelement <64 x i4> %r4, i4 zeroinitializer, i32 11 1531 %r6 = insertelement <64 x i4> %r5, i4 zeroinitializer, i32 13 1532 %r7 = insertelement <64 x i4> %r6, i4 zeroinitializer, i32 15 1533 %r8 = insertelement <64 x i4> %r7, i4 zeroinitializer, i32 17 1534 %r9 = insertelement <64 x i4> %r8, i4 zeroinitializer, i32 19 1535 %r10 = insertelement <64 x i4> %r9, i4 zeroinitializer, i32 21 1536 %r11 = insertelement <64 x i4> %r10, i4 zeroinitializer, i32 23 1537 %r12 = insertelement <64 x i4> %r11, i4 zeroinitializer, i32 25 1538 %r13 = insertelement <64 x i4> %r12, i4 zeroinitializer, i32 27 1539 %r14 = insertelement <64 x i4> %r13, i4 zeroinitializer, i32 29 1540 %r15 = insertelement <64 x i4> %r14, i4 zeroinitializer, i32 31 1541 %r16 = insertelement <64 x i4> %r15, i4 zeroinitializer, i32 33 1542 %r17 = insertelement <64 x i4> %r16, i4 zeroinitializer, i32 35 1543 %r18 = insertelement <64 x i4> %r17, i4 zeroinitializer, i32 37 1544 %r19 = insertelement <64 x i4> %r18, i4 zeroinitializer, i32 39 1545 %r20 = insertelement <64 x i4> %r19, i4 zeroinitializer, i32 41 1546 %r21 = insertelement <64 x i4> %r20, i4 zeroinitializer, i32 43 1547 %r22 = insertelement <64 x i4> %r21, i4 zeroinitializer, i32 45 1548 %r23 = insertelement <64 x i4> %r22, i4 zeroinitializer, i32 47 1549 %r24 = insertelement <64 x i4> %r23, i4 zeroinitializer, i32 49 1550 %r25 = insertelement <64 x i4> %r24, i4 zeroinitializer, i32 51 1551 %r26 = insertelement <64 x i4> %r25, i4 zeroinitializer, i32 53 1552 %r27 = insertelement <64 x i4> %r26, i4 zeroinitializer, i32 55 1553 %r28 = insertelement <64 x i4> %r27, i4 zeroinitializer, i32 57 1554 %r29 = insertelement <64 x i4> %r28, i4 zeroinitializer, i32 59 1555 %r30 = insertelement <64 x i4> %r29, i4 zeroinitializer, i32 61 1556 %r31 = insertelement <64 x i4> %r30, i4 zeroinitializer, i32 63 1557 %r = bitcast <64 x i4> %r15 to <32 x i8> 1558 ret <32 x i8> %r 1559} 1560 1561define <2 x i64> @_clearupper2xi64c(<2 x i64>) nounwind { 1562; SSE-LABEL: _clearupper2xi64c: 1563; SSE: # BB#0: 1564; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1565; SSE-NEXT: retq 1566; 1567; AVX1-LABEL: _clearupper2xi64c: 1568; AVX1: # BB#0: 1569; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 1570; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 1571; AVX1-NEXT: retq 1572; 1573; AVX2-LABEL: _clearupper2xi64c: 1574; AVX2: # BB#0: 1575; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 1576; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] 1577; AVX2-NEXT: retq 1578 %r = and <2 x i64> <i64 4294967295, i64 4294967295>, %0 1579 ret <2 x i64> %r 1580} 1581 1582define <4 x i64> @_clearupper4xi64c(<4 x i64>) nounwind { 1583; SSE-LABEL: _clearupper4xi64c: 1584; SSE: # BB#0: 1585; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967295,0,4294967295,0] 1586; SSE-NEXT: andps %xmm2, %xmm0 1587; SSE-NEXT: andps %xmm2, %xmm1 1588; SSE-NEXT: retq 1589; 1590; AVX1-LABEL: _clearupper4xi64c: 1591; AVX1: # BB#0: 1592; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1 1593; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 1594; AVX1-NEXT: retq 1595; 1596; AVX2-LABEL: _clearupper4xi64c: 1597; AVX2: # BB#0: 1598; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 1599; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] 1600; AVX2-NEXT: retq 1601 %r = and <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>, %0 1602 ret <4 x i64> %r 1603} 1604 1605define <4 x i32> @_clearupper4xi32c(<4 x i32>) nounwind { 1606; SSE-LABEL: _clearupper4xi32c: 1607; SSE: # BB#0: 1608; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1609; SSE-NEXT: retq 1610; 1611; AVX-LABEL: _clearupper4xi32c: 1612; AVX: # BB#0: 1613; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 1614; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] 1615; AVX-NEXT: retq 1616 %r = and <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>, %0 1617 ret <4 x i32> %r 1618} 1619 1620define <8 x i32> @_clearupper8xi32c(<8 x i32>) nounwind { 1621; SSE-LABEL: _clearupper8xi32c: 1622; SSE: # BB#0: 1623; SSE-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,0,65535,0,65535,0] 1624; SSE-NEXT: andps %xmm2, %xmm0 1625; SSE-NEXT: andps %xmm2, %xmm1 1626; SSE-NEXT: retq 1627; 1628; AVX1-LABEL: _clearupper8xi32c: 1629; AVX1: # BB#0: 1630; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 1631; AVX1-NEXT: retq 1632; 1633; AVX2-LABEL: _clearupper8xi32c: 1634; AVX2: # BB#0: 1635; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1 1636; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] 1637; AVX2-NEXT: retq 1638 %r = and <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>, %0 1639 ret <8 x i32> %r 1640} 1641 1642define <8 x i16> @_clearupper8xi16c(<8 x i16>) nounwind { 1643; SSE-LABEL: _clearupper8xi16c: 1644; SSE: # BB#0: 1645; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1646; SSE-NEXT: retq 1647; 1648; AVX-LABEL: _clearupper8xi16c: 1649; AVX: # BB#0: 1650; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 1651; AVX-NEXT: retq 1652 %r = and <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, %0 1653 ret <8 x i16> %r 1654} 1655 1656define <16 x i16> @_clearupper16xi16c(<16 x i16>) nounwind { 1657; SSE-LABEL: _clearupper16xi16c: 1658; SSE: # BB#0: 1659; SSE-NEXT: movaps {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0] 1660; SSE-NEXT: andps %xmm2, %xmm0 1661; SSE-NEXT: andps %xmm2, %xmm1 1662; SSE-NEXT: retq 1663; 1664; AVX-LABEL: _clearupper16xi16c: 1665; AVX: # BB#0: 1666; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 1667; AVX-NEXT: retq 1668 %r = and <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, %0 1669 ret <16 x i16> %r 1670} 1671 1672define <16 x i8> @_clearupper16xi8c(<16 x i8>) nounwind { 1673; SSE-LABEL: _clearupper16xi8c: 1674; SSE: # BB#0: 1675; SSE-NEXT: andps {{.*}}(%rip), %xmm0 1676; SSE-NEXT: retq 1677; 1678; AVX-LABEL: _clearupper16xi8c: 1679; AVX: # BB#0: 1680; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 1681; AVX-NEXT: retq 1682 %r = and <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, %0 1683 ret <16 x i8> %r 1684} 1685 1686define <32 x i8> @_clearupper32xi8c(<32 x i8>) nounwind { 1687; SSE-LABEL: _clearupper32xi8c: 1688; SSE: # BB#0: 1689; SSE-NEXT: movaps {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] 1690; SSE-NEXT: andps %xmm2, %xmm0 1691; SSE-NEXT: andps %xmm2, %xmm1 1692; SSE-NEXT: retq 1693; 1694; AVX-LABEL: _clearupper32xi8c: 1695; AVX: # BB#0: 1696; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 1697; AVX-NEXT: retq 1698 %r = and <32 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, %0 1699 ret <32 x i8> %r 1700} 1701