1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41 4 5define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind { 6; SSE2-LABEL: foo: 7; SSE2: # %bb.0: 8; SSE2-NEXT: cvttps2dq %xmm0, %xmm0 9; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) 10; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 11; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %ecx 12; SSE2-NEXT: shll $8, %ecx 13; SSE2-NEXT: orl %eax, %ecx 14; SSE2-NEXT: movd %ecx, %xmm0 15; SSE2-NEXT: movl $65280, %eax # imm = 0xFF00 16; SSE2-NEXT: orl -{{[0-9]+}}(%rsp), %eax 17; SSE2-NEXT: pinsrw $1, %eax, %xmm0 18; SSE2-NEXT: movd %xmm0, (%rdi) 19; SSE2-NEXT: retq 20; 21; SSE41-LABEL: foo: 22; SSE41: # %bb.0: 23; SSE41-NEXT: cvttps2dq %xmm0, %xmm0 24; SSE41-NEXT: pextrb $8, %xmm0, %eax 25; SSE41-NEXT: pextrb $4, %xmm0, %ecx 26; SSE41-NEXT: pinsrb $1, %ecx, %xmm0 27; SSE41-NEXT: pinsrb $2, %eax, %xmm0 28; SSE41-NEXT: movl $255, %eax 29; SSE41-NEXT: pinsrb $3, %eax, %xmm0 30; SSE41-NEXT: movd %xmm0, (%rdi) 31; SSE41-NEXT: retq 32 %t0 = fptoui <3 x float> %in to <3 x i8> 33 %t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 34 %t2 = insertelement <4 x i8> %t1, i8 -1, i32 3 35 store <4 x i8> %t2, <4 x i8>* %out, align 4 36 ret void 37} 38 39; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a 40; blend with a zero vector if the build_vector contains negative zero. 41 42define <4 x float> @test_negative_zero_1(<4 x float> %A) { 43; SSE2-LABEL: test_negative_zero_1: 44; SSE2: # %bb.0: # %entry 45; SSE2-NEXT: movaps %xmm0, %xmm1 46; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] 47; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero 48; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 49; SSE2-NEXT: xorps %xmm2, %xmm2 50; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] 51; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 52; SSE2-NEXT: retq 53; 54; SSE41-LABEL: test_negative_zero_1: 55; SSE41: # %bb.0: # %entry 56; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero 57; SSE41-NEXT: retq 58entry: 59 %0 = extractelement <4 x float> %A, i32 0 60 %1 = insertelement <4 x float> undef, float %0, i32 0 61 %2 = insertelement <4 x float> %1, float -0.0, i32 1 62 %3 = extractelement <4 x float> %A, i32 2 63 %4 = insertelement <4 x float> %2, float %3, i32 2 64 %5 = insertelement <4 x float> %4, float 0.0, i32 3 65 ret <4 x float> %5 66} 67 68; FIXME: This could be 'movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]'. 69 70define <2 x double> @test_negative_zero_2(<2 x double> %A) { 71; SSE2-LABEL: test_negative_zero_2: 72; SSE2: # %bb.0: # %entry 73; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[0],mem[1] 74; SSE2-NEXT: retq 75; 76; SSE41-LABEL: test_negative_zero_2: 77; SSE41: # %bb.0: # %entry 78; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] 79; SSE41-NEXT: retq 80entry: 81 %0 = extractelement <2 x double> %A, i32 0 82 %1 = insertelement <2 x double> undef, double %0, i32 0 83 %2 = insertelement <2 x double> %1, double -0.0, i32 1 84 ret <2 x double> %2 85} 86 87define <4 x float> @test_buildvector_v4f32_register(float %f0, float %f1, float %f2, float %f3) { 88; SSE2-LABEL: test_buildvector_v4f32_register: 89; SSE2: # %bb.0: 90; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] 91; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 92; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 93; SSE2-NEXT: retq 94; 95; SSE41-LABEL: test_buildvector_v4f32_register: 96; SSE41: # %bb.0: 97; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 98; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 99; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] 100; SSE41-NEXT: retq 101 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 102 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 103 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 104 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 105 ret <4 x float> %ins3 106} 107 108define <4 x float> @test_buildvector_v4f32_load(float* %p0, float* %p1, float* %p2, float* %p3) { 109; SSE2-LABEL: test_buildvector_v4f32_load: 110; SSE2: # %bb.0: 111; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 112; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero 113; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 114; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero 115; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 116; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 117; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 118; SSE2-NEXT: retq 119; 120; SSE41-LABEL: test_buildvector_v4f32_load: 121; SSE41: # %bb.0: 122; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 123; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] 124; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] 125; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] 126; SSE41-NEXT: retq 127 %f0 = load float, float* %p0, align 4 128 %f1 = load float, float* %p1, align 4 129 %f2 = load float, float* %p2, align 4 130 %f3 = load float, float* %p3, align 4 131 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 132 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 133 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 134 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 135 ret <4 x float> %ins3 136} 137 138define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, float %f2, float* %p3) { 139; SSE2-LABEL: test_buildvector_v4f32_partial_load: 140; SSE2: # %bb.0: 141; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero 142; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] 143; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 144; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 145; SSE2-NEXT: retq 146; 147; SSE41-LABEL: test_buildvector_v4f32_partial_load: 148; SSE41: # %bb.0: 149; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 150; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 151; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] 152; SSE41-NEXT: retq 153 %f3 = load float, float* %p3, align 4 154 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 155 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 156 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 157 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 158 ret <4 x float> %ins3 159} 160 161define <4 x i32> @test_buildvector_v4i32_register(i32 %a0, i32 %a1, i32 %a2, i32 %a3) { 162; SSE2-LABEL: test_buildvector_v4i32_register: 163; SSE2: # %bb.0: 164; SSE2-NEXT: movd %ecx, %xmm0 165; SSE2-NEXT: movd %edx, %xmm1 166; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 167; SSE2-NEXT: movd %esi, %xmm2 168; SSE2-NEXT: movd %edi, %xmm0 169; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 170; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 171; SSE2-NEXT: retq 172; 173; SSE41-LABEL: test_buildvector_v4i32_register: 174; SSE41: # %bb.0: 175; SSE41-NEXT: movd %edi, %xmm0 176; SSE41-NEXT: pinsrd $1, %esi, %xmm0 177; SSE41-NEXT: pinsrd $2, %edx, %xmm0 178; SSE41-NEXT: pinsrd $3, %ecx, %xmm0 179; SSE41-NEXT: retq 180 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 181 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1 182 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 183 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 184 ret <4 x i32> %ins3 185} 186 187define <4 x i32> @test_buildvector_v4i32_partial(i32 %a0, i32 %a3) { 188; SSE2-LABEL: test_buildvector_v4i32_partial: 189; SSE2: # %bb.0: 190; SSE2-NEXT: movd %edi, %xmm0 191; SSE2-NEXT: movd %esi, %xmm1 192; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] 193; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 194; SSE2-NEXT: retq 195; 196; SSE41-LABEL: test_buildvector_v4i32_partial: 197; SSE41: # %bb.0: 198; SSE41-NEXT: movd %edi, %xmm0 199; SSE41-NEXT: pinsrd $3, %esi, %xmm0 200; SSE41-NEXT: retq 201 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 202 %ins1 = insertelement <4 x i32> %ins0, i32 undef, i32 1 203 %ins2 = insertelement <4 x i32> %ins1, i32 undef, i32 2 204 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 205 ret <4 x i32> %ins3 206} 207 208define <4 x i32> @test_buildvector_v4i32_register_zero(i32 %a0, i32 %a2, i32 %a3) { 209; CHECK-LABEL: test_buildvector_v4i32_register_zero: 210; CHECK: # %bb.0: 211; CHECK-NEXT: movd %edx, %xmm0 212; CHECK-NEXT: movd %esi, %xmm1 213; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 214; CHECK-NEXT: movd %edi, %xmm0 215; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 216; CHECK-NEXT: retq 217 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 218 %ins1 = insertelement <4 x i32> %ins0, i32 0, i32 1 219 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 220 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 221 ret <4 x i32> %ins3 222} 223 224define <4 x i32> @test_buildvector_v4i32_register_zero_2(i32 %a1, i32 %a2, i32 %a3) { 225; CHECK-LABEL: test_buildvector_v4i32_register_zero_2: 226; CHECK: # %bb.0: 227; CHECK-NEXT: movd %edx, %xmm0 228; CHECK-NEXT: movd %esi, %xmm1 229; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 230; CHECK-NEXT: movd %edi, %xmm0 231; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1] 232; CHECK-NEXT: retq 233 %ins0 = insertelement <4 x i32> undef, i32 0, i32 0 234 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1 235 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 236 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 237 ret <4 x i32> %ins3 238} 239 240define <8 x i16> @test_buildvector_v8i16_register(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) { 241; SSE2-LABEL: test_buildvector_v8i16_register: 242; SSE2: # %bb.0: 243; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 244; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 245; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 246; SSE2-NEXT: movd %r9d, %xmm0 247; SSE2-NEXT: movd %r8d, %xmm2 248; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] 249; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] 250; SSE2-NEXT: movd %ecx, %xmm0 251; SSE2-NEXT: movd %edx, %xmm1 252; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 253; SSE2-NEXT: movd %esi, %xmm3 254; SSE2-NEXT: movd %edi, %xmm0 255; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] 256; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 257; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] 258; SSE2-NEXT: retq 259; 260; SSE41-LABEL: test_buildvector_v8i16_register: 261; SSE41: # %bb.0: 262; SSE41-NEXT: movd %edi, %xmm0 263; SSE41-NEXT: pinsrw $1, %esi, %xmm0 264; SSE41-NEXT: pinsrw $2, %edx, %xmm0 265; SSE41-NEXT: pinsrw $3, %ecx, %xmm0 266; SSE41-NEXT: pinsrw $4, %r8d, %xmm0 267; SSE41-NEXT: pinsrw $5, %r9d, %xmm0 268; SSE41-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0 269; SSE41-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0 270; SSE41-NEXT: retq 271 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 272 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 273 %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2 274 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 275 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 276 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 277 %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6 278 %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7 279 ret <8 x i16> %ins7 280} 281 282define <8 x i16> @test_buildvector_v8i16_partial(i16 %a1, i16 %a3, i16 %a4, i16 %a5) { 283; CHECK-LABEL: test_buildvector_v8i16_partial: 284; CHECK: # %bb.0: 285; CHECK-NEXT: pxor %xmm0, %xmm0 286; CHECK-NEXT: pinsrw $1, %edi, %xmm0 287; CHECK-NEXT: pinsrw $3, %esi, %xmm0 288; CHECK-NEXT: pinsrw $4, %edx, %xmm0 289; CHECK-NEXT: pinsrw $5, %ecx, %xmm0 290; CHECK-NEXT: retq 291 %ins0 = insertelement <8 x i16> undef, i16 undef, i32 0 292 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 293 %ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2 294 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 295 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 296 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 297 %ins6 = insertelement <8 x i16> %ins5, i16 undef, i32 6 298 %ins7 = insertelement <8 x i16> %ins6, i16 undef, i32 7 299 ret <8 x i16> %ins7 300} 301 302define <8 x i16> @test_buildvector_v8i16_register_zero(i16 %a0, i16 %a3, i16 %a4, i16 %a5) { 303; CHECK-LABEL: test_buildvector_v8i16_register_zero: 304; CHECK: # %bb.0: 305; CHECK-NEXT: movzwl %di, %eax 306; CHECK-NEXT: movd %eax, %xmm0 307; CHECK-NEXT: pinsrw $3, %esi, %xmm0 308; CHECK-NEXT: pinsrw $4, %edx, %xmm0 309; CHECK-NEXT: pinsrw $5, %ecx, %xmm0 310; CHECK-NEXT: retq 311 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 312 %ins1 = insertelement <8 x i16> %ins0, i16 0, i32 1 313 %ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2 314 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 315 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 316 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 317 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6 318 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7 319 ret <8 x i16> %ins7 320} 321 322define <8 x i16> @test_buildvector_v8i16_register_zero_2(i16 %a1, i16 %a3, i16 %a4, i16 %a5) { 323; CHECK-LABEL: test_buildvector_v8i16_register_zero_2: 324; CHECK: # %bb.0: 325; CHECK-NEXT: pxor %xmm0, %xmm0 326; CHECK-NEXT: pinsrw $1, %edi, %xmm0 327; CHECK-NEXT: pinsrw $3, %esi, %xmm0 328; CHECK-NEXT: pinsrw $4, %edx, %xmm0 329; CHECK-NEXT: pinsrw $5, %ecx, %xmm0 330; CHECK-NEXT: retq 331 %ins0 = insertelement <8 x i16> undef, i16 0, i32 0 332 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 333 %ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2 334 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 335 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 336 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 337 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6 338 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7 339 ret <8 x i16> %ins7 340} 341 342define <16 x i8> @test_buildvector_v16i8_register(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) { 343; SSE2-LABEL: test_buildvector_v16i8_register: 344; SSE2: # %bb.0: 345; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 346; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 347; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 348; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 349; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero 350; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 351; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 352; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 353; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 354; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 355; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 356; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero 357; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 358; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3] 359; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] 360; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 361; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 362; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 363; SSE2-NEXT: movd %r9d, %xmm0 364; SSE2-NEXT: movd %r8d, %xmm2 365; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 366; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 367; SSE2-NEXT: movd %ecx, %xmm0 368; SSE2-NEXT: movd %edx, %xmm1 369; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 370; SSE2-NEXT: movd %esi, %xmm4 371; SSE2-NEXT: movd %edi, %xmm0 372; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] 373; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 374; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 375; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] 376; SSE2-NEXT: retq 377; 378; SSE41-LABEL: test_buildvector_v16i8_register: 379; SSE41: # %bb.0: 380; SSE41-NEXT: movd %edi, %xmm0 381; SSE41-NEXT: pinsrb $1, %esi, %xmm0 382; SSE41-NEXT: pinsrb $2, %edx, %xmm0 383; SSE41-NEXT: pinsrb $3, %ecx, %xmm0 384; SSE41-NEXT: pinsrb $4, %r8d, %xmm0 385; SSE41-NEXT: pinsrb $5, %r9d, %xmm0 386; SSE41-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm0 387; SSE41-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm0 388; SSE41-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm0 389; SSE41-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm0 390; SSE41-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm0 391; SSE41-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm0 392; SSE41-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm0 393; SSE41-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm0 394; SSE41-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm0 395; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0 396; SSE41-NEXT: retq 397 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 398 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 399 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 400 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 401 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4 402 %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5 403 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 404 %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7 405 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 406 %ins9 = insertelement <16 x i8> %ins8, i8 %a9, i32 9 407 %ins10 = insertelement <16 x i8> %ins9, i8 %a10, i32 10 408 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 409 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 410 %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13 411 %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14 412 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 413 ret <16 x i8> %ins15 414} 415 416define <16 x i8> @test_buildvector_v16i8_partial(i8 %a2, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) { 417; SSE2-LABEL: test_buildvector_v16i8_partial: 418; SSE2: # %bb.0: 419; SSE2-NEXT: pxor %xmm0, %xmm0 420; SSE2-NEXT: pinsrw $1, %edi, %xmm0 421; SSE2-NEXT: pinsrw $3, %esi, %xmm0 422; SSE2-NEXT: pinsrw $4, %edx, %xmm0 423; SSE2-NEXT: shll $8, %ecx 424; SSE2-NEXT: pinsrw $5, %ecx, %xmm0 425; SSE2-NEXT: pinsrw $6, %r8d, %xmm0 426; SSE2-NEXT: shll $8, %r9d 427; SSE2-NEXT: pinsrw $7, %r9d, %xmm0 428; SSE2-NEXT: retq 429; 430; SSE41-LABEL: test_buildvector_v16i8_partial: 431; SSE41: # %bb.0: 432; SSE41-NEXT: pxor %xmm0, %xmm0 433; SSE41-NEXT: pinsrb $2, %edi, %xmm0 434; SSE41-NEXT: pinsrb $6, %esi, %xmm0 435; SSE41-NEXT: pinsrb $8, %edx, %xmm0 436; SSE41-NEXT: pinsrb $11, %ecx, %xmm0 437; SSE41-NEXT: pinsrb $12, %r8d, %xmm0 438; SSE41-NEXT: pinsrb $15, %r9d, %xmm0 439; SSE41-NEXT: retq 440 %ins0 = insertelement <16 x i8> undef, i8 undef, i32 0 441 %ins1 = insertelement <16 x i8> %ins0, i8 undef, i32 1 442 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 443 %ins3 = insertelement <16 x i8> %ins2, i8 undef, i32 3 444 %ins4 = insertelement <16 x i8> %ins3, i8 undef, i32 4 445 %ins5 = insertelement <16 x i8> %ins4, i8 undef, i32 5 446 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 447 %ins7 = insertelement <16 x i8> %ins6, i8 undef, i32 7 448 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 449 %ins9 = insertelement <16 x i8> %ins8, i8 undef, i32 9 450 %ins10 = insertelement <16 x i8> %ins9, i8 undef, i32 10 451 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 452 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 453 %ins13 = insertelement <16 x i8> %ins12, i8 undef, i32 13 454 %ins14 = insertelement <16 x i8> %ins13, i8 undef, i32 14 455 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 456 ret <16 x i8> %ins15 457} 458 459define <16 x i8> @test_buildvector_v16i8_register_zero(i8 %a0, i8 %a4, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) { 460; SSE2-LABEL: test_buildvector_v16i8_register_zero: 461; SSE2: # %bb.0: 462; SSE2-NEXT: movzbl %sil, %eax 463; SSE2-NEXT: movzbl %dil, %esi 464; SSE2-NEXT: movd %esi, %xmm0 465; SSE2-NEXT: pinsrw $2, %eax, %xmm0 466; SSE2-NEXT: movzbl %dl, %eax 467; SSE2-NEXT: pinsrw $3, %eax, %xmm0 468; SSE2-NEXT: movzbl %cl, %eax 469; SSE2-NEXT: pinsrw $4, %eax, %xmm0 470; SSE2-NEXT: shll $8, %r8d 471; SSE2-NEXT: pinsrw $5, %r8d, %xmm0 472; SSE2-NEXT: movzbl %r9b, %eax 473; SSE2-NEXT: pinsrw $6, %eax, %xmm0 474; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax 475; SSE2-NEXT: shll $8, %eax 476; SSE2-NEXT: pinsrw $7, %eax, %xmm0 477; SSE2-NEXT: retq 478; 479; SSE41-LABEL: test_buildvector_v16i8_register_zero: 480; SSE41: # %bb.0: 481; SSE41-NEXT: movzbl %dil, %eax 482; SSE41-NEXT: movd %eax, %xmm0 483; SSE41-NEXT: pinsrb $4, %esi, %xmm0 484; SSE41-NEXT: pinsrb $6, %edx, %xmm0 485; SSE41-NEXT: pinsrb $8, %ecx, %xmm0 486; SSE41-NEXT: pinsrb $11, %r8d, %xmm0 487; SSE41-NEXT: pinsrb $12, %r9d, %xmm0 488; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0 489; SSE41-NEXT: retq 490 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 491 %ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1 492 %ins2 = insertelement <16 x i8> %ins1, i8 0, i32 2 493 %ins3 = insertelement <16 x i8> %ins2, i8 0, i32 3 494 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4 495 %ins5 = insertelement <16 x i8> %ins4, i8 0, i32 5 496 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 497 %ins7 = insertelement <16 x i8> %ins6, i8 0, i32 7 498 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 499 %ins9 = insertelement <16 x i8> %ins8, i8 0, i32 9 500 %ins10 = insertelement <16 x i8> %ins9, i8 0, i32 10 501 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 502 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 503 %ins13 = insertelement <16 x i8> %ins12, i8 0, i32 13 504 %ins14 = insertelement <16 x i8> %ins13, i8 0, i32 14 505 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 506 ret <16 x i8> %ins15 507} 508 509define <16 x i8> @test_buildvector_v16i8_register_zero_2(i8 %a2, i8 %a3, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) { 510; SSE2-LABEL: test_buildvector_v16i8_register_zero_2: 511; SSE2: # %bb.0: 512; SSE2-NEXT: shll $8, %esi 513; SSE2-NEXT: movzbl %dil, %eax 514; SSE2-NEXT: orl %esi, %eax 515; SSE2-NEXT: pxor %xmm0, %xmm0 516; SSE2-NEXT: pinsrw $1, %eax, %xmm0 517; SSE2-NEXT: movzbl %dl, %eax 518; SSE2-NEXT: pinsrw $3, %eax, %xmm0 519; SSE2-NEXT: movzbl %cl, %eax 520; SSE2-NEXT: pinsrw $4, %eax, %xmm0 521; SSE2-NEXT: shll $8, %r8d 522; SSE2-NEXT: pinsrw $5, %r8d, %xmm0 523; SSE2-NEXT: movzbl %r9b, %eax 524; SSE2-NEXT: pinsrw $6, %eax, %xmm0 525; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax 526; SSE2-NEXT: shll $8, %eax 527; SSE2-NEXT: pinsrw $7, %eax, %xmm0 528; SSE2-NEXT: retq 529; 530; SSE41-LABEL: test_buildvector_v16i8_register_zero_2: 531; SSE41: # %bb.0: 532; SSE41-NEXT: pxor %xmm0, %xmm0 533; SSE41-NEXT: pinsrb $2, %edi, %xmm0 534; SSE41-NEXT: pinsrb $3, %esi, %xmm0 535; SSE41-NEXT: pinsrb $6, %edx, %xmm0 536; SSE41-NEXT: pinsrb $8, %ecx, %xmm0 537; SSE41-NEXT: pinsrb $11, %r8d, %xmm0 538; SSE41-NEXT: pinsrb $12, %r9d, %xmm0 539; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0 540; SSE41-NEXT: retq 541 %ins0 = insertelement <16 x i8> undef, i8 0, i32 0 542 %ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1 543 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 544 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 545 %ins4 = insertelement <16 x i8> %ins3, i8 0, i32 4 546 %ins5 = insertelement <16 x i8> %ins4, i8 0, i32 5 547 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 548 %ins7 = insertelement <16 x i8> %ins6, i8 0, i32 7 549 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 550 %ins9 = insertelement <16 x i8> %ins8, i8 0, i32 9 551 %ins10 = insertelement <16 x i8> %ins9, i8 0, i32 10 552 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 553 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 554 %ins13 = insertelement <16 x i8> %ins12, i8 0, i32 13 555 %ins14 = insertelement <16 x i8> %ins13, i8 0, i32 14 556 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 557 ret <16 x i8> %ins15 558} 559 560; OSS-Fuzz #5688 561; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5688 562define <4 x i32> @ossfuzz5688(i32 %a0) { 563; CHECK-LABEL: ossfuzz5688: 564; CHECK: # %bb.0: 565; CHECK-NEXT: retq 566 %1 = insertelement <4 x i32> zeroinitializer, i32 -2147483648, i32 %a0 567 %2 = extractelement <4 x i32> %1, i32 %a0 568 %3 = extractelement <4 x i32> <i32 30, i32 53, i32 42, i32 12>, i32 %2 569 %4 = extractelement <4 x i32> zeroinitializer, i32 %2 570 %5 = insertelement <4 x i32> undef, i32 %3, i32 undef 571 store i32 %4, i32* undef 572 ret <4 x i32> %5 573} 574