1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s 3 4define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind { 5; CHECK-LABEL: foo: 6; CHECK: # BB#0: 7; CHECK-NEXT: cvttps2dq %xmm0, %xmm0 8; CHECK-NEXT: movl $255, %eax 9; CHECK-NEXT: pinsrd $3, %eax, %xmm0 10; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] 11; CHECK-NEXT: movd %xmm0, (%rdi) 12; CHECK-NEXT: retq 13 %t0 = fptoui <3 x float> %in to <3 x i8> 14 %t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 15 %t2 = insertelement <4 x i8> %t1, i8 -1, i32 3 16 store <4 x i8> %t2, <4 x i8>* %out, align 4 17 ret void 18} 19 20; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a 21; blend with a zero vector if the build_vector contains negative zero. 22 23define <4 x float> @test_negative_zero_1(<4 x float> %A) { 24; CHECK-LABEL: test_negative_zero_1: 25; CHECK: # BB#0: # %entry 26; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero 27; CHECK-NEXT: retq 28entry: 29 %0 = extractelement <4 x float> %A, i32 0 30 %1 = insertelement <4 x float> undef, float %0, i32 0 31 %2 = insertelement <4 x float> %1, float -0.0, i32 1 32 %3 = extractelement <4 x float> %A, i32 2 33 %4 = insertelement <4 x float> %2, float %3, i32 2 34 %5 = insertelement <4 x float> %4, float 0.0, i32 3 35 ret <4 x float> %5 36} 37 38define <2 x double> @test_negative_zero_2(<2 x double> %A) { 39; CHECK-LABEL: test_negative_zero_2: 40; CHECK: # BB#0: # %entry 41; CHECK-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0] 42; CHECK-NEXT: retq 43entry: 44 %0 = extractelement <2 x double> %A, i32 0 45 %1 = insertelement <2 x double> undef, double %0, i32 0 46 %2 = insertelement <2 x double> %1, double -0.0, i32 1 47 ret <2 x double> %2 48} 49 50define <4 x float> @test_buildvector_v4f32_register(float %f0, float %f1, float %f2, float %f3) { 51; CHECK-LABEL: test_buildvector_v4f32_register: 52; CHECK: # BB#0: 53; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 54; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 55; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] 56; CHECK-NEXT: retq 57 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 58 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 59 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 60 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 61 ret <4 x float> %ins3 62} 63 64define <4 x float> @test_buildvector_v4f32_load(float* %p0, float* %p1, float* %p2, float* %p3) { 65; CHECK-LABEL: test_buildvector_v4f32_load: 66; CHECK: # BB#0: 67; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 68; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] 69; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] 70; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] 71; CHECK-NEXT: retq 72 %f0 = load float, float* %p0, align 4 73 %f1 = load float, float* %p1, align 4 74 %f2 = load float, float* %p2, align 4 75 %f3 = load float, float* %p3, align 4 76 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 77 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 78 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 79 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 80 ret <4 x float> %ins3 81} 82 83define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, float %f2, float* %p3) { 84; CHECK-LABEL: test_buildvector_v4f32_partial_load: 85; CHECK: # BB#0: 86; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 87; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 88; CHECK-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] 89; CHECK-NEXT: retq 90 %f3 = load float, float* %p3, align 4 91 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 92 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 93 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 94 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 95 ret <4 x float> %ins3 96} 97