1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41 4 5define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind { 6; SSE2-LABEL: foo: 7; SSE2: # %bb.0: 8; SSE2-NEXT: cvttps2dq %xmm0, %xmm0 9; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) 10; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax 11; SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %ecx 12; SSE2-NEXT: shll $8, %ecx 13; SSE2-NEXT: orl %eax, %ecx 14; SSE2-NEXT: movd %ecx, %xmm0 15; SSE2-NEXT: movl $65280, %eax # imm = 0xFF00 16; SSE2-NEXT: orl -{{[0-9]+}}(%rsp), %eax 17; SSE2-NEXT: pinsrw $1, %eax, %xmm0 18; SSE2-NEXT: movd %xmm0, (%rdi) 19; SSE2-NEXT: retq 20; 21; SSE41-LABEL: foo: 22; SSE41: # %bb.0: 23; SSE41-NEXT: cvttps2dq %xmm0, %xmm0 24; SSE41-NEXT: pextrb $8, %xmm0, %eax 25; SSE41-NEXT: pextrb $4, %xmm0, %ecx 26; SSE41-NEXT: pextrb $0, %xmm0, %edx 27; SSE41-NEXT: movd %edx, %xmm0 28; SSE41-NEXT: pinsrb $1, %ecx, %xmm0 29; SSE41-NEXT: pinsrb $2, %eax, %xmm0 30; SSE41-NEXT: movl $255, %eax 31; SSE41-NEXT: pinsrb $3, %eax, %xmm0 32; SSE41-NEXT: movd %xmm0, (%rdi) 33; SSE41-NEXT: retq 34 %t0 = fptoui <3 x float> %in to <3 x i8> 35 %t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 36 %t2 = insertelement <4 x i8> %t1, i8 -1, i32 3 37 store <4 x i8> %t2, <4 x i8>* %out, align 4 38 ret void 39} 40 41; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a 42; blend with a zero vector if the build_vector contains negative zero. 43 44define <4 x float> @test_negative_zero_1(<4 x float> %A) { 45; SSE2-LABEL: test_negative_zero_1: 46; SSE2: # %bb.0: # %entry 47; SSE2-NEXT: movaps %xmm0, %xmm1 48; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] 49; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero 50; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 51; SSE2-NEXT: xorps %xmm2, %xmm2 52; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] 53; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 54; SSE2-NEXT: retq 55; 56; SSE41-LABEL: test_negative_zero_1: 57; SSE41: # %bb.0: # %entry 58; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero 59; SSE41-NEXT: retq 60entry: 61 %0 = extractelement <4 x float> %A, i32 0 62 %1 = insertelement <4 x float> undef, float %0, i32 0 63 %2 = insertelement <4 x float> %1, float -0.0, i32 1 64 %3 = extractelement <4 x float> %A, i32 2 65 %4 = insertelement <4 x float> %2, float %3, i32 2 66 %5 = insertelement <4 x float> %4, float 0.0, i32 3 67 ret <4 x float> %5 68} 69 70; FIXME: This could be 'movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]'. 71 72define <2 x double> @test_negative_zero_2(<2 x double> %A) { 73; SSE2-LABEL: test_negative_zero_2: 74; SSE2: # %bb.0: # %entry 75; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[0],mem[1] 76; SSE2-NEXT: retq 77; 78; SSE41-LABEL: test_negative_zero_2: 79; SSE41: # %bb.0: # %entry 80; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3] 81; SSE41-NEXT: retq 82entry: 83 %0 = extractelement <2 x double> %A, i32 0 84 %1 = insertelement <2 x double> undef, double %0, i32 0 85 %2 = insertelement <2 x double> %1, double -0.0, i32 1 86 ret <2 x double> %2 87} 88 89define <4 x float> @test_buildvector_v4f32_register(float %f0, float %f1, float %f2, float %f3) { 90; SSE2-LABEL: test_buildvector_v4f32_register: 91; SSE2: # %bb.0: 92; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] 93; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 94; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 95; SSE2-NEXT: retq 96; 97; SSE41-LABEL: test_buildvector_v4f32_register: 98; SSE41: # %bb.0: 99; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 100; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 101; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] 102; SSE41-NEXT: retq 103 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 104 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 105 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 106 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 107 ret <4 x float> %ins3 108} 109 110define <4 x float> @test_buildvector_v4f32_load(float* %p0, float* %p1, float* %p2, float* %p3) { 111; SSE2-LABEL: test_buildvector_v4f32_load: 112; SSE2: # %bb.0: 113; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 114; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero 115; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 116; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero 117; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 118; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 119; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] 120; SSE2-NEXT: retq 121; 122; SSE41-LABEL: test_buildvector_v4f32_load: 123; SSE41: # %bb.0: 124; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero 125; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] 126; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] 127; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] 128; SSE41-NEXT: retq 129 %f0 = load float, float* %p0, align 4 130 %f1 = load float, float* %p1, align 4 131 %f2 = load float, float* %p2, align 4 132 %f3 = load float, float* %p3, align 4 133 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 134 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 135 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 136 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 137 ret <4 x float> %ins3 138} 139 140define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, float %f2, float* %p3) { 141; SSE2-LABEL: test_buildvector_v4f32_partial_load: 142; SSE2: # %bb.0: 143; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero 144; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] 145; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 146; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] 147; SSE2-NEXT: retq 148; 149; SSE41-LABEL: test_buildvector_v4f32_partial_load: 150; SSE41: # %bb.0: 151; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] 152; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] 153; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] 154; SSE41-NEXT: retq 155 %f3 = load float, float* %p3, align 4 156 %ins0 = insertelement <4 x float> undef, float %f0, i32 0 157 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 158 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 159 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 160 ret <4 x float> %ins3 161} 162 163define <4 x i32> @test_buildvector_v4i32_register(i32 %a0, i32 %a1, i32 %a2, i32 %a3) { 164; SSE2-LABEL: test_buildvector_v4i32_register: 165; SSE2: # %bb.0: 166; SSE2-NEXT: movd %ecx, %xmm0 167; SSE2-NEXT: movd %edx, %xmm1 168; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 169; SSE2-NEXT: movd %esi, %xmm2 170; SSE2-NEXT: movd %edi, %xmm0 171; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 172; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 173; SSE2-NEXT: retq 174; 175; SSE41-LABEL: test_buildvector_v4i32_register: 176; SSE41: # %bb.0: 177; SSE41-NEXT: movd %edi, %xmm0 178; SSE41-NEXT: pinsrd $1, %esi, %xmm0 179; SSE41-NEXT: pinsrd $2, %edx, %xmm0 180; SSE41-NEXT: pinsrd $3, %ecx, %xmm0 181; SSE41-NEXT: retq 182 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 183 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1 184 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 185 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 186 ret <4 x i32> %ins3 187} 188 189define <4 x i32> @test_buildvector_v4i32_partial(i32 %a0, i32 %a3) { 190; SSE2-LABEL: test_buildvector_v4i32_partial: 191; SSE2: # %bb.0: 192; SSE2-NEXT: movd %edi, %xmm0 193; SSE2-NEXT: movd %esi, %xmm1 194; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] 195; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 196; SSE2-NEXT: retq 197; 198; SSE41-LABEL: test_buildvector_v4i32_partial: 199; SSE41: # %bb.0: 200; SSE41-NEXT: movd %edi, %xmm0 201; SSE41-NEXT: pinsrd $3, %esi, %xmm0 202; SSE41-NEXT: retq 203 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 204 %ins1 = insertelement <4 x i32> %ins0, i32 undef, i32 1 205 %ins2 = insertelement <4 x i32> %ins1, i32 undef, i32 2 206 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 207 ret <4 x i32> %ins3 208} 209 210define <4 x i32> @test_buildvector_v4i32_register_zero(i32 %a0, i32 %a2, i32 %a3) { 211; CHECK-LABEL: test_buildvector_v4i32_register_zero: 212; CHECK: # %bb.0: 213; CHECK-NEXT: movd %edx, %xmm0 214; CHECK-NEXT: movd %esi, %xmm1 215; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 216; CHECK-NEXT: movd %edi, %xmm0 217; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 218; CHECK-NEXT: retq 219 %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 220 %ins1 = insertelement <4 x i32> %ins0, i32 0, i32 1 221 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 222 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 223 ret <4 x i32> %ins3 224} 225 226define <4 x i32> @test_buildvector_v4i32_register_zero_2(i32 %a1, i32 %a2, i32 %a3) { 227; CHECK-LABEL: test_buildvector_v4i32_register_zero_2: 228; CHECK: # %bb.0: 229; CHECK-NEXT: movd %edx, %xmm0 230; CHECK-NEXT: movd %esi, %xmm1 231; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] 232; CHECK-NEXT: movd %edi, %xmm0 233; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1] 234; CHECK-NEXT: retq 235 %ins0 = insertelement <4 x i32> undef, i32 0, i32 0 236 %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1 237 %ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2 238 %ins3 = insertelement <4 x i32> %ins2, i32 %a3, i32 3 239 ret <4 x i32> %ins3 240} 241 242define <8 x i16> @test_buildvector_v8i16_register(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) { 243; SSE2-LABEL: test_buildvector_v8i16_register: 244; SSE2: # %bb.0: 245; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 246; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 247; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 248; SSE2-NEXT: movd %r9d, %xmm0 249; SSE2-NEXT: movd %r8d, %xmm2 250; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] 251; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] 252; SSE2-NEXT: movd %ecx, %xmm0 253; SSE2-NEXT: movd %edx, %xmm1 254; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] 255; SSE2-NEXT: movd %esi, %xmm3 256; SSE2-NEXT: movd %edi, %xmm0 257; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] 258; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] 259; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] 260; SSE2-NEXT: retq 261; 262; SSE41-LABEL: test_buildvector_v8i16_register: 263; SSE41: # %bb.0: 264; SSE41-NEXT: movd %edi, %xmm0 265; SSE41-NEXT: pinsrw $1, %esi, %xmm0 266; SSE41-NEXT: pinsrw $2, %edx, %xmm0 267; SSE41-NEXT: pinsrw $3, %ecx, %xmm0 268; SSE41-NEXT: pinsrw $4, %r8d, %xmm0 269; SSE41-NEXT: pinsrw $5, %r9d, %xmm0 270; SSE41-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0 271; SSE41-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0 272; SSE41-NEXT: retq 273 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 274 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 275 %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2 276 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 277 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 278 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 279 %ins6 = insertelement <8 x i16> %ins5, i16 %a6, i32 6 280 %ins7 = insertelement <8 x i16> %ins6, i16 %a7, i32 7 281 ret <8 x i16> %ins7 282} 283 284define <8 x i16> @test_buildvector_v8i16_partial(i16 %a1, i16 %a3, i16 %a4, i16 %a5) { 285; CHECK-LABEL: test_buildvector_v8i16_partial: 286; CHECK: # %bb.0: 287; CHECK-NEXT: pxor %xmm0, %xmm0 288; CHECK-NEXT: pinsrw $1, %edi, %xmm0 289; CHECK-NEXT: pinsrw $3, %esi, %xmm0 290; CHECK-NEXT: pinsrw $4, %edx, %xmm0 291; CHECK-NEXT: pinsrw $5, %ecx, %xmm0 292; CHECK-NEXT: retq 293 %ins0 = insertelement <8 x i16> undef, i16 undef, i32 0 294 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 295 %ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2 296 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 297 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 298 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 299 %ins6 = insertelement <8 x i16> %ins5, i16 undef, i32 6 300 %ins7 = insertelement <8 x i16> %ins6, i16 undef, i32 7 301 ret <8 x i16> %ins7 302} 303 304define <8 x i16> @test_buildvector_v8i16_register_zero(i16 %a0, i16 %a3, i16 %a4, i16 %a5) { 305; CHECK-LABEL: test_buildvector_v8i16_register_zero: 306; CHECK: # %bb.0: 307; CHECK-NEXT: pxor %xmm0, %xmm0 308; CHECK-NEXT: pinsrw $0, %edi, %xmm0 309; CHECK-NEXT: pinsrw $3, %esi, %xmm0 310; CHECK-NEXT: pinsrw $4, %edx, %xmm0 311; CHECK-NEXT: pinsrw $5, %ecx, %xmm0 312; CHECK-NEXT: retq 313 %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 314 %ins1 = insertelement <8 x i16> %ins0, i16 0, i32 1 315 %ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2 316 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 317 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 318 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 319 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6 320 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7 321 ret <8 x i16> %ins7 322} 323 324define <8 x i16> @test_buildvector_v8i16_register_zero_2(i16 %a1, i16 %a3, i16 %a4, i16 %a5) { 325; CHECK-LABEL: test_buildvector_v8i16_register_zero_2: 326; CHECK: # %bb.0: 327; CHECK-NEXT: pxor %xmm0, %xmm0 328; CHECK-NEXT: pinsrw $1, %edi, %xmm0 329; CHECK-NEXT: pinsrw $3, %esi, %xmm0 330; CHECK-NEXT: pinsrw $4, %edx, %xmm0 331; CHECK-NEXT: pinsrw $5, %ecx, %xmm0 332; CHECK-NEXT: retq 333 %ins0 = insertelement <8 x i16> undef, i16 0, i32 0 334 %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 335 %ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2 336 %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 337 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 338 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 339 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6 340 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7 341 ret <8 x i16> %ins7 342} 343 344define <16 x i8> @test_buildvector_v16i8_register(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) { 345; SSE2-LABEL: test_buildvector_v16i8_register: 346; SSE2: # %bb.0: 347; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 348; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 349; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 350; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 351; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero 352; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 353; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 354; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 355; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 356; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 357; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 358; SSE2-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero 359; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] 360; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3] 361; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] 362; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero 363; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero 364; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 365; SSE2-NEXT: movd %r9d, %xmm0 366; SSE2-NEXT: movd %r8d, %xmm2 367; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] 368; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] 369; SSE2-NEXT: movd %ecx, %xmm0 370; SSE2-NEXT: movd %edx, %xmm1 371; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] 372; SSE2-NEXT: movd %esi, %xmm4 373; SSE2-NEXT: movd %edi, %xmm0 374; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] 375; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] 376; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] 377; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] 378; SSE2-NEXT: retq 379; 380; SSE41-LABEL: test_buildvector_v16i8_register: 381; SSE41: # %bb.0: 382; SSE41-NEXT: movd %edi, %xmm0 383; SSE41-NEXT: pinsrb $1, %esi, %xmm0 384; SSE41-NEXT: pinsrb $2, %edx, %xmm0 385; SSE41-NEXT: pinsrb $3, %ecx, %xmm0 386; SSE41-NEXT: pinsrb $4, %r8d, %xmm0 387; SSE41-NEXT: pinsrb $5, %r9d, %xmm0 388; SSE41-NEXT: pinsrb $6, {{[0-9]+}}(%rsp), %xmm0 389; SSE41-NEXT: pinsrb $7, {{[0-9]+}}(%rsp), %xmm0 390; SSE41-NEXT: pinsrb $8, {{[0-9]+}}(%rsp), %xmm0 391; SSE41-NEXT: pinsrb $9, {{[0-9]+}}(%rsp), %xmm0 392; SSE41-NEXT: pinsrb $10, {{[0-9]+}}(%rsp), %xmm0 393; SSE41-NEXT: pinsrb $11, {{[0-9]+}}(%rsp), %xmm0 394; SSE41-NEXT: pinsrb $12, {{[0-9]+}}(%rsp), %xmm0 395; SSE41-NEXT: pinsrb $13, {{[0-9]+}}(%rsp), %xmm0 396; SSE41-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm0 397; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0 398; SSE41-NEXT: retq 399 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 400 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 401 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 402 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 403 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4 404 %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5 405 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 406 %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7 407 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 408 %ins9 = insertelement <16 x i8> %ins8, i8 %a9, i32 9 409 %ins10 = insertelement <16 x i8> %ins9, i8 %a10, i32 10 410 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 411 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 412 %ins13 = insertelement <16 x i8> %ins12, i8 %a13, i32 13 413 %ins14 = insertelement <16 x i8> %ins13, i8 %a14, i32 14 414 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 415 ret <16 x i8> %ins15 416} 417 418define <16 x i8> @test_buildvector_v16i8_partial(i8 %a2, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) { 419; SSE2-LABEL: test_buildvector_v16i8_partial: 420; SSE2: # %bb.0: 421; SSE2-NEXT: pxor %xmm0, %xmm0 422; SSE2-NEXT: pinsrw $1, %edi, %xmm0 423; SSE2-NEXT: pinsrw $3, %esi, %xmm0 424; SSE2-NEXT: pinsrw $4, %edx, %xmm0 425; SSE2-NEXT: shll $8, %ecx 426; SSE2-NEXT: pinsrw $5, %ecx, %xmm0 427; SSE2-NEXT: pinsrw $6, %r8d, %xmm0 428; SSE2-NEXT: shll $8, %r9d 429; SSE2-NEXT: pinsrw $7, %r9d, %xmm0 430; SSE2-NEXT: retq 431; 432; SSE41-LABEL: test_buildvector_v16i8_partial: 433; SSE41: # %bb.0: 434; SSE41-NEXT: pxor %xmm0, %xmm0 435; SSE41-NEXT: pinsrb $2, %edi, %xmm0 436; SSE41-NEXT: pinsrb $6, %esi, %xmm0 437; SSE41-NEXT: pinsrb $8, %edx, %xmm0 438; SSE41-NEXT: pinsrb $11, %ecx, %xmm0 439; SSE41-NEXT: pinsrb $12, %r8d, %xmm0 440; SSE41-NEXT: pinsrb $15, %r9d, %xmm0 441; SSE41-NEXT: retq 442 %ins0 = insertelement <16 x i8> undef, i8 undef, i32 0 443 %ins1 = insertelement <16 x i8> %ins0, i8 undef, i32 1 444 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 445 %ins3 = insertelement <16 x i8> %ins2, i8 undef, i32 3 446 %ins4 = insertelement <16 x i8> %ins3, i8 undef, i32 4 447 %ins5 = insertelement <16 x i8> %ins4, i8 undef, i32 5 448 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 449 %ins7 = insertelement <16 x i8> %ins6, i8 undef, i32 7 450 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 451 %ins9 = insertelement <16 x i8> %ins8, i8 undef, i32 9 452 %ins10 = insertelement <16 x i8> %ins9, i8 undef, i32 10 453 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 454 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 455 %ins13 = insertelement <16 x i8> %ins12, i8 undef, i32 13 456 %ins14 = insertelement <16 x i8> %ins13, i8 undef, i32 14 457 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 458 ret <16 x i8> %ins15 459} 460 461define <16 x i8> @test_buildvector_v16i8_register_zero(i8 %a0, i8 %a4, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) { 462; SSE2-LABEL: test_buildvector_v16i8_register_zero: 463; SSE2: # %bb.0: 464; SSE2-NEXT: movzbl %sil, %eax 465; SSE2-NEXT: movzbl %dil, %esi 466; SSE2-NEXT: movd %esi, %xmm0 467; SSE2-NEXT: pinsrw $2, %eax, %xmm0 468; SSE2-NEXT: movzbl %dl, %eax 469; SSE2-NEXT: pinsrw $3, %eax, %xmm0 470; SSE2-NEXT: movzbl %cl, %eax 471; SSE2-NEXT: pinsrw $4, %eax, %xmm0 472; SSE2-NEXT: shll $8, %r8d 473; SSE2-NEXT: pinsrw $5, %r8d, %xmm0 474; SSE2-NEXT: movzbl %r9b, %eax 475; SSE2-NEXT: pinsrw $6, %eax, %xmm0 476; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax 477; SSE2-NEXT: shll $8, %eax 478; SSE2-NEXT: pinsrw $7, %eax, %xmm0 479; SSE2-NEXT: retq 480; 481; SSE41-LABEL: test_buildvector_v16i8_register_zero: 482; SSE41: # %bb.0: 483; SSE41-NEXT: pxor %xmm0, %xmm0 484; SSE41-NEXT: pinsrb $0, %edi, %xmm0 485; SSE41-NEXT: pinsrb $4, %esi, %xmm0 486; SSE41-NEXT: pinsrb $6, %edx, %xmm0 487; SSE41-NEXT: pinsrb $8, %ecx, %xmm0 488; SSE41-NEXT: pinsrb $11, %r8d, %xmm0 489; SSE41-NEXT: pinsrb $12, %r9d, %xmm0 490; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0 491; SSE41-NEXT: retq 492 %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 493 %ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1 494 %ins2 = insertelement <16 x i8> %ins1, i8 0, i32 2 495 %ins3 = insertelement <16 x i8> %ins2, i8 0, i32 3 496 %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4 497 %ins5 = insertelement <16 x i8> %ins4, i8 0, i32 5 498 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 499 %ins7 = insertelement <16 x i8> %ins6, i8 0, i32 7 500 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 501 %ins9 = insertelement <16 x i8> %ins8, i8 0, i32 9 502 %ins10 = insertelement <16 x i8> %ins9, i8 0, i32 10 503 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 504 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 505 %ins13 = insertelement <16 x i8> %ins12, i8 0, i32 13 506 %ins14 = insertelement <16 x i8> %ins13, i8 0, i32 14 507 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 508 ret <16 x i8> %ins15 509} 510 511define <16 x i8> @test_buildvector_v16i8_register_zero_2(i8 %a2, i8 %a3, i8 %a6, i8 %a8, i8 %a11, i8 %a12, i8 %a15) { 512; SSE2-LABEL: test_buildvector_v16i8_register_zero_2: 513; SSE2: # %bb.0: 514; SSE2-NEXT: shll $8, %esi 515; SSE2-NEXT: movzbl %dil, %eax 516; SSE2-NEXT: orl %esi, %eax 517; SSE2-NEXT: pxor %xmm0, %xmm0 518; SSE2-NEXT: pinsrw $1, %eax, %xmm0 519; SSE2-NEXT: movzbl %dl, %eax 520; SSE2-NEXT: pinsrw $3, %eax, %xmm0 521; SSE2-NEXT: movzbl %cl, %eax 522; SSE2-NEXT: pinsrw $4, %eax, %xmm0 523; SSE2-NEXT: shll $8, %r8d 524; SSE2-NEXT: pinsrw $5, %r8d, %xmm0 525; SSE2-NEXT: movzbl %r9b, %eax 526; SSE2-NEXT: pinsrw $6, %eax, %xmm0 527; SSE2-NEXT: movl {{[0-9]+}}(%rsp), %eax 528; SSE2-NEXT: shll $8, %eax 529; SSE2-NEXT: pinsrw $7, %eax, %xmm0 530; SSE2-NEXT: retq 531; 532; SSE41-LABEL: test_buildvector_v16i8_register_zero_2: 533; SSE41: # %bb.0: 534; SSE41-NEXT: pxor %xmm0, %xmm0 535; SSE41-NEXT: pinsrb $2, %edi, %xmm0 536; SSE41-NEXT: pinsrb $3, %esi, %xmm0 537; SSE41-NEXT: pinsrb $6, %edx, %xmm0 538; SSE41-NEXT: pinsrb $8, %ecx, %xmm0 539; SSE41-NEXT: pinsrb $11, %r8d, %xmm0 540; SSE41-NEXT: pinsrb $12, %r9d, %xmm0 541; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0 542; SSE41-NEXT: retq 543 %ins0 = insertelement <16 x i8> undef, i8 0, i32 0 544 %ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1 545 %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 546 %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 547 %ins4 = insertelement <16 x i8> %ins3, i8 0, i32 4 548 %ins5 = insertelement <16 x i8> %ins4, i8 0, i32 5 549 %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 550 %ins7 = insertelement <16 x i8> %ins6, i8 0, i32 7 551 %ins8 = insertelement <16 x i8> %ins7, i8 %a8, i32 8 552 %ins9 = insertelement <16 x i8> %ins8, i8 0, i32 9 553 %ins10 = insertelement <16 x i8> %ins9, i8 0, i32 10 554 %ins11 = insertelement <16 x i8> %ins10, i8 %a11, i32 11 555 %ins12 = insertelement <16 x i8> %ins11, i8 %a12, i32 12 556 %ins13 = insertelement <16 x i8> %ins12, i8 0, i32 13 557 %ins14 = insertelement <16 x i8> %ins13, i8 0, i32 14 558 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 559 ret <16 x i8> %ins15 560} 561 562; OSS-Fuzz #5688 563; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5688 564define <4 x i32> @ossfuzz5688(i32 %a0) { 565; CHECK-LABEL: ossfuzz5688: 566; CHECK: # %bb.0: 567; CHECK-NEXT: retq 568 %1 = insertelement <4 x i32> zeroinitializer, i32 -2147483648, i32 %a0 569 %2 = extractelement <4 x i32> %1, i32 %a0 570 %3 = extractelement <4 x i32> <i32 30, i32 53, i32 42, i32 12>, i32 %2 571 %4 = extractelement <4 x i32> zeroinitializer, i32 %2 572 %5 = insertelement <4 x i32> undef, i32 %3, i32 undef 573 store i32 %4, i32* undef 574 ret <4 x i32> %5 575} 576