1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl  | FileCheck %s
3
4define <16 x i32> @select00(i32 %a, <16 x i32> %b) nounwind {
5; CHECK-LABEL: select00:
6; CHECK:       ## BB#0:
7; CHECK-NEXT:    vpxord %zmm1, %zmm1, %zmm1
8; CHECK-NEXT:    cmpl $255, %edi
9; CHECK-NEXT:    je LBB0_2
10; CHECK-NEXT:  ## BB#1:
11; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm1
12; CHECK-NEXT:  LBB0_2:
13; CHECK-NEXT:    vpxorq %zmm1, %zmm0, %zmm0
14; CHECK-NEXT:    retq
15  %cmpres = icmp eq i32 %a, 255
16  %selres = select i1 %cmpres, <16 x i32> zeroinitializer, <16 x i32> %b
17  %res = xor <16 x i32> %b, %selres
18  ret <16 x i32> %res
19}
20
21define <8 x i64> @select01(i32 %a, <8 x i64> %b) nounwind {
22; CHECK-LABEL: select01:
23; CHECK:       ## BB#0:
24; CHECK-NEXT:    vpxord %zmm1, %zmm1, %zmm1
25; CHECK-NEXT:    cmpl $255, %edi
26; CHECK-NEXT:    je LBB1_2
27; CHECK-NEXT:  ## BB#1:
28; CHECK-NEXT:    vmovdqa64 %zmm0, %zmm1
29; CHECK-NEXT:  LBB1_2:
30; CHECK-NEXT:    vpxorq %zmm1, %zmm0, %zmm0
31; CHECK-NEXT:    retq
32  %cmpres = icmp eq i32 %a, 255
33  %selres = select i1 %cmpres, <8 x i64> zeroinitializer, <8 x i64> %b
34  %res = xor <8 x i64> %b, %selres
35  ret <8 x i64> %res
36}
37
38define float @select02(float %a, float %b, float %c, float %eps) {
39; CHECK-LABEL: select02:
40; CHECK:       ## BB#0:
41; CHECK-NEXT:    vcmpless %xmm0, %xmm3, %k1
42; CHECK-NEXT:    vmovss %xmm2, %xmm0, %xmm1 {%k1}
43; CHECK-NEXT:    vmovaps %xmm1, %xmm0
44; CHECK-NEXT:    retq
45  %cmp = fcmp oge float %a, %eps
46  %cond = select i1 %cmp, float %c, float %b
47  ret float %cond
48}
49
50define double @select03(double %a, double %b, double %c, double %eps) {
51; CHECK-LABEL: select03:
52; CHECK:       ## BB#0:
53; CHECK-NEXT:    vcmplesd %xmm0, %xmm3, %k1
54; CHECK-NEXT:    vmovsd %xmm2, %xmm0, %xmm1 {%k1}
55; CHECK-NEXT:    vmovapd %xmm1, %xmm0
56; CHECK-NEXT:    retq
57  %cmp = fcmp oge double %a, %eps
58  %cond = select i1 %cmp, double %c, double %b
59  ret double %cond
60}
61
62define <16 x double> @select04(<16 x double> %a, <16 x double> %b) {
63; CHECK-LABEL: select04:
64; CHECK:       ## BB#0:
65; CHECK-NEXT:    vmovaps %zmm3, %zmm1
66; CHECK-NEXT:    retq
67  %sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
68  ret <16 x double> %sel
69}
70
71define i8 @select05(i8 %a.0, i8 %m) {
72; CHECK-LABEL: select05:
73; CHECK:       ## BB#0:
74; CHECK-NEXT:    orl %esi, %edi
75; CHECK-NEXT:    movl %edi, %eax
76; CHECK-NEXT:    retq
77  %mask = bitcast i8 %m to <8 x i1>
78  %a = bitcast i8 %a.0 to <8 x i1>
79  %r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
80  %res = bitcast <8 x i1> %r to i8
81  ret i8 %res;
82}
83
84define i8 @select05_mem(<8 x i1>* %a.0, <8 x i1>* %m) {
85; CHECK-LABEL: select05_mem:
86; CHECK:       ## BB#0:
87; CHECK-NEXT:    movzbl (%rsi), %eax
88; CHECK-NEXT:    kmovw %eax, %k0
89; CHECK-NEXT:    movzbl (%rdi), %eax
90; CHECK-NEXT:    kmovw %eax, %k1
91; CHECK-NEXT:    korw %k1, %k0, %k0
92; CHECK-NEXT:    kmovw %k0, %eax
93; CHECK-NEXT:    retq
94  %mask = load <8 x i1> , <8 x i1>* %m
95  %a = load <8 x i1> , <8 x i1>* %a.0
96  %r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
97  %res = bitcast <8 x i1> %r to i8
98  ret i8 %res;
99}
100
101define i8 @select06(i8 %a.0, i8 %m) {
102; CHECK-LABEL: select06:
103; CHECK:       ## BB#0:
104; CHECK-NEXT:    andl %esi, %edi
105; CHECK-NEXT:    movl %edi, %eax
106; CHECK-NEXT:    retq
107  %mask = bitcast i8 %m to <8 x i1>
108  %a = bitcast i8 %a.0 to <8 x i1>
109  %r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
110  %res = bitcast <8 x i1> %r to i8
111  ret i8 %res;
112}
113
114define i8 @select06_mem(<8 x i1>* %a.0, <8 x i1>* %m) {
115; CHECK-LABEL: select06_mem:
116; CHECK:       ## BB#0:
117; CHECK-NEXT:    movzbl (%rsi), %eax
118; CHECK-NEXT:    kmovw %eax, %k0
119; CHECK-NEXT:    movzbl (%rdi), %eax
120; CHECK-NEXT:    kmovw %eax, %k1
121; CHECK-NEXT:    kandw %k1, %k0, %k0
122; CHECK-NEXT:    kmovw %k0, %eax
123; CHECK-NEXT:    retq
124  %mask = load <8 x i1> , <8 x i1>* %m
125  %a = load <8 x i1> , <8 x i1>* %a.0
126  %r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
127  %res = bitcast <8 x i1> %r to i8
128  ret i8 %res;
129}
130define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) {
131; CHECK-LABEL: select07:
132; CHECK:       ## BB#0:
133; CHECK-NEXT:    kmovw %edx, %k0
134; CHECK-NEXT:    kmovw %edi, %k1
135; CHECK-NEXT:    kmovw %esi, %k2
136; CHECK-NEXT:    kandnw %k2, %k0, %k2
137; CHECK-NEXT:    kandw %k0, %k1, %k0
138; CHECK-NEXT:    korw %k2, %k0, %k0
139; CHECK-NEXT:    kmovw %k0, %eax
140; CHECK-NEXT:    retq
141  %mask = bitcast i8 %m to <8 x i1>
142  %a = bitcast i8 %a.0 to <8 x i1>
143  %b = bitcast i8 %b.0 to <8 x i1>
144  %r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> %b
145  %res = bitcast <8 x i1> %r to i8
146  ret i8 %res;
147}
148
149define i64 @pr30249() {
150; CHECK-LABEL: pr30249:
151; CHECK:       ## BB#0:
152; CHECK-NEXT:    xorl %ecx, %ecx
153; CHECK-NEXT:    cmpb $1, %cl
154; CHECK-NEXT:    movl $1, %eax
155; CHECK-NEXT:    adcxq %rcx, %rax
156; CHECK-NEXT:    retq
157  %v = select i1 undef , i64 1, i64 2
158  ret i64 %v
159}
160
161define double @pr30561_f64(double %b, double %a, i1 %c) {
162; CHECK-LABEL: pr30561_f64:
163; CHECK:       ## BB#0:
164; CHECK-NEXT:    andl $1, %edi
165; CHECK-NEXT:    kmovw %edi, %k1
166; CHECK-NEXT:    vmovsd %xmm1, %xmm0, %xmm0 {%k1}
167; CHECK-NEXT:    retq
168  %cond = select i1 %c, double %a, double %b
169  ret double %cond
170}
171
172define float @pr30561_f32(float %b, float %a, i1 %c) {
173; CHECK-LABEL: pr30561_f32:
174; CHECK:       ## BB#0:
175; CHECK-NEXT:    andl $1, %edi
176; CHECK-NEXT:    kmovw %edi, %k1
177; CHECK-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
178; CHECK-NEXT:    retq
179  %cond = select i1 %c, float %a, float %b
180  ret float %cond
181}
182