1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
3
4--- |
5
6  define i8 @test_i8(i32 %a, i8 %f, i8 %t) {
7  entry:
8    %cmp = icmp sgt i32 %a, 0
9    br i1 %cmp, label %cond.true, label %cond.false
10
11  cond.true:                                        ; preds = %entry
12    br label %cond.end
13
14  cond.false:                                       ; preds = %entry
15    br label %cond.end
16
17  cond.end:                                         ; preds = %cond.false, %cond.true
18    %cond = phi i8 [ %f, %cond.true ], [ %t, %cond.false ]
19    ret i8 %cond
20  }
21
22  define i16 @test_i16(i32 %a, i16 %f, i16 %t) {
23  entry:
24    %cmp = icmp sgt i32 %a, 0
25    br i1 %cmp, label %cond.true, label %cond.false
26
27  cond.true:                                        ; preds = %entry
28    br label %cond.end
29
30  cond.false:                                       ; preds = %entry
31    br label %cond.end
32
33  cond.end:                                         ; preds = %cond.false, %cond.true
34    %cond = phi i16 [ %f, %cond.true ], [ %t, %cond.false ]
35    ret i16 %cond
36  }
37
38  define i32 @test_i32(i32 %a, i32 %f, i32 %t) {
39  entry:
40    %cmp = icmp sgt i32 %a, 0
41    br i1 %cmp, label %cond.true, label %cond.false
42
43  cond.true:                                        ; preds = %entry
44    br label %cond.end
45
46  cond.false:                                       ; preds = %entry
47    br label %cond.end
48
49  cond.end:                                         ; preds = %cond.false, %cond.true
50    %cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ]
51    ret i32 %cond
52  }
53
54  define i64 @test_i64(i32 %a, i64 %f, i64 %t) {
55  entry:
56    %cmp = icmp sgt i32 %a, 0
57    br i1 %cmp, label %cond.true, label %cond.false
58
59  cond.true:                                        ; preds = %entry
60    br label %cond.end
61
62  cond.false:                                       ; preds = %entry
63    br label %cond.end
64
65  cond.end:                                         ; preds = %cond.false, %cond.true
66    %cond = phi i64 [ %f, %cond.true ], [ %t, %cond.false ]
67    ret i64 %cond
68  }
69
70  define float @test_float(i32 %a, float %f, float %t) {
71  entry:
72    %cmp = icmp sgt i32 %a, 0
73    br i1 %cmp, label %cond.true, label %cond.false
74
75  cond.true:                                        ; preds = %entry
76    br label %cond.end
77
78  cond.false:                                       ; preds = %entry
79    br label %cond.end
80
81  cond.end:                                         ; preds = %cond.false, %cond.true
82    %cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]
83    ret float %cond
84  }
85
86  define double @test_double(i32 %a, double %f, double %t) {
87  entry:
88    %cmp = icmp sgt i32 %a, 0
89    br i1 %cmp, label %cond.true, label %cond.false
90
91  cond.true:                                        ; preds = %entry
92    br label %cond.end
93
94  cond.false:                                       ; preds = %entry
95    br label %cond.end
96
97  cond.end:                                         ; preds = %cond.false, %cond.true
98    %cond = phi double [ %f, %cond.true ], [ %t, %cond.false ]
99    ret double %cond
100  }
101
102...
103---
104name:            test_i8
105alignment:       16
106legalized:       true
107regBankSelected: true
108tracksRegLiveness: true
109registers:
110  - { id: 0, class: gpr, preferred-register: '' }
111  - { id: 1, class: gpr, preferred-register: '' }
112  - { id: 2, class: gpr, preferred-register: '' }
113  - { id: 3, class: gpr, preferred-register: '' }
114  - { id: 4, class: gpr, preferred-register: '' }
115  - { id: 5, class: gpr, preferred-register: '' }
116  - { id: 6, class: gpr, preferred-register: '' }
117  - { id: 7, class: gpr, preferred-register: '' }
118body:             |
119  ; ALL-LABEL: name: test_i8
120  ; ALL: bb.0.entry:
121  ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
122  ; ALL-NEXT:   liveins: $edi, $edx, $esi
123  ; ALL-NEXT: {{  $}}
124  ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
125  ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
126  ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
127  ; ALL-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
128  ; ALL-NEXT:   [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
129  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
130  ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
131  ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
132  ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
133  ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
134  ; ALL-NEXT: {{  $}}
135  ; ALL-NEXT: bb.1.cond.false:
136  ; ALL-NEXT:   successors: %bb.2(0x80000000)
137  ; ALL-NEXT: {{  $}}
138  ; ALL-NEXT: {{  $}}
139  ; ALL-NEXT: bb.2.cond.end:
140  ; ALL-NEXT:   [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
141  ; ALL-NEXT:   $al = COPY [[PHI]]
142  ; ALL-NEXT:   RET 0, implicit $al
143  bb.1.entry:
144    successors: %bb.3(0x40000000), %bb.2(0x40000000)
145    liveins: $edi, $edx, $esi
146
147    %0:gpr(s32) = COPY $edi
148    %3:gpr(s32) = COPY $esi
149    %1:gpr(s8) = G_TRUNC %3(s32)
150    %4:gpr(s32) = COPY $edx
151    %2:gpr(s8) = G_TRUNC %4(s32)
152    %5:gpr(s32) = G_CONSTANT i32 0
153    %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
154    %6:gpr(s1) = G_TRUNC %8(s8)
155    G_BRCOND %6(s1), %bb.3
156
157  bb.2.cond.false:
158    successors: %bb.3(0x80000000)
159
160
161  bb.3.cond.end:
162    %7:gpr(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1
163    $al = COPY %7(s8)
164    RET 0, implicit $al
165
166...
167---
168name:            test_i16
169alignment:       16
170legalized:       true
171regBankSelected: true
172tracksRegLiveness: true
173registers:
174  - { id: 0, class: gpr, preferred-register: '' }
175  - { id: 1, class: gpr, preferred-register: '' }
176  - { id: 2, class: gpr, preferred-register: '' }
177  - { id: 3, class: gpr, preferred-register: '' }
178  - { id: 4, class: gpr, preferred-register: '' }
179  - { id: 5, class: gpr, preferred-register: '' }
180  - { id: 6, class: gpr, preferred-register: '' }
181  - { id: 7, class: gpr, preferred-register: '' }
182body:             |
183  ; ALL-LABEL: name: test_i16
184  ; ALL: bb.0.entry:
185  ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
186  ; ALL-NEXT:   liveins: $edi, $edx, $esi
187  ; ALL-NEXT: {{  $}}
188  ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
189  ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
190  ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
191  ; ALL-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY $edx
192  ; ALL-NEXT:   [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
193  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
194  ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
195  ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
196  ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
197  ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
198  ; ALL-NEXT: {{  $}}
199  ; ALL-NEXT: bb.1.cond.false:
200  ; ALL-NEXT:   successors: %bb.2(0x80000000)
201  ; ALL-NEXT: {{  $}}
202  ; ALL-NEXT: {{  $}}
203  ; ALL-NEXT: bb.2.cond.end:
204  ; ALL-NEXT:   [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
205  ; ALL-NEXT:   $ax = COPY [[PHI]]
206  ; ALL-NEXT:   RET 0, implicit $ax
207  bb.1.entry:
208    successors: %bb.3(0x40000000), %bb.2(0x40000000)
209    liveins: $edi, $edx, $esi
210
211    %0:gpr(s32) = COPY $edi
212    %3:gpr(s32) = COPY $esi
213    %1:gpr(s16) = G_TRUNC %3(s32)
214    %4:gpr(s32) = COPY $edx
215    %2:gpr(s16) = G_TRUNC %4(s32)
216    %5:gpr(s32) = G_CONSTANT i32 0
217    %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
218    %6:gpr(s1) = G_TRUNC %8(s8)
219    G_BRCOND %6(s1), %bb.3
220
221  bb.2.cond.false:
222    successors: %bb.3(0x80000000)
223
224
225  bb.3.cond.end:
226    %7:gpr(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1
227    $ax = COPY %7(s16)
228    RET 0, implicit $ax
229
230...
231---
232name:            test_i32
233alignment:       16
234legalized:       true
235regBankSelected: true
236tracksRegLiveness: true
237registers:
238  - { id: 0, class: gpr, preferred-register: '' }
239  - { id: 1, class: gpr, preferred-register: '' }
240  - { id: 2, class: gpr, preferred-register: '' }
241  - { id: 3, class: gpr, preferred-register: '' }
242  - { id: 4, class: gpr, preferred-register: '' }
243  - { id: 5, class: gpr, preferred-register: '' }
244  - { id: 6, class: gpr, preferred-register: '' }
245body:             |
246  ; ALL-LABEL: name: test_i32
247  ; ALL: bb.0.entry:
248  ; ALL-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
249  ; ALL-NEXT:   liveins: $edi, $edx, $esi
250  ; ALL-NEXT: {{  $}}
251  ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
252  ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
253  ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $edx
254  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
255  ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
256  ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
257  ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
258  ; ALL-NEXT:   JCC_1 %bb.1, 5, implicit $eflags
259  ; ALL-NEXT:   JMP_1 %bb.2
260  ; ALL-NEXT: {{  $}}
261  ; ALL-NEXT: bb.1.cond.true:
262  ; ALL-NEXT:   successors: %bb.3(0x80000000)
263  ; ALL-NEXT: {{  $}}
264  ; ALL-NEXT:   JMP_1 %bb.3
265  ; ALL-NEXT: {{  $}}
266  ; ALL-NEXT: bb.2.cond.false:
267  ; ALL-NEXT:   successors: %bb.3(0x80000000)
268  ; ALL-NEXT: {{  $}}
269  ; ALL-NEXT: {{  $}}
270  ; ALL-NEXT: bb.3.cond.end:
271  ; ALL-NEXT:   [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
272  ; ALL-NEXT:   $eax = COPY [[PHI]]
273  ; ALL-NEXT:   RET 0, implicit $eax
274  bb.1.entry:
275    successors: %bb.2(0x40000000), %bb.3(0x40000000)
276    liveins: $edi, $edx, $esi
277
278    %0(s32) = COPY $edi
279    %1(s32) = COPY $esi
280    %2(s32) = COPY $edx
281    %3(s32) = G_CONSTANT i32 0
282    %6(s8) = G_ICMP intpred(sgt), %0(s32), %3
283    %4:gpr(s1) = G_TRUNC %6(s8)
284    G_BRCOND %4(s1), %bb.2
285    G_BR %bb.3
286
287  bb.2.cond.true:
288    successors: %bb.4(0x80000000)
289
290    G_BR %bb.4
291
292  bb.3.cond.false:
293    successors: %bb.4(0x80000000)
294
295
296  bb.4.cond.end:
297    %5(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
298    $eax = COPY %5(s32)
299    RET 0, implicit $eax
300
301...
302---
303name:            test_i64
304alignment:       16
305legalized:       true
306regBankSelected: true
307tracksRegLiveness: true
308registers:
309  - { id: 0, class: gpr, preferred-register: '' }
310  - { id: 1, class: gpr, preferred-register: '' }
311  - { id: 2, class: gpr, preferred-register: '' }
312  - { id: 3, class: gpr, preferred-register: '' }
313  - { id: 4, class: gpr, preferred-register: '' }
314  - { id: 5, class: gpr, preferred-register: '' }
315  - { id: 6, class: gpr, preferred-register: '' }
316body:             |
317  ; ALL-LABEL: name: test_i64
318  ; ALL: bb.0.entry:
319  ; ALL-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
320  ; ALL-NEXT:   liveins: $edi, $rdx, $rsi
321  ; ALL-NEXT: {{  $}}
322  ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
323  ; ALL-NEXT:   [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
324  ; ALL-NEXT:   [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
325  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
326  ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
327  ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
328  ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
329  ; ALL-NEXT:   JCC_1 %bb.1, 5, implicit $eflags
330  ; ALL-NEXT:   JMP_1 %bb.2
331  ; ALL-NEXT: {{  $}}
332  ; ALL-NEXT: bb.1.cond.true:
333  ; ALL-NEXT:   successors: %bb.3(0x80000000)
334  ; ALL-NEXT: {{  $}}
335  ; ALL-NEXT:   JMP_1 %bb.3
336  ; ALL-NEXT: {{  $}}
337  ; ALL-NEXT: bb.2.cond.false:
338  ; ALL-NEXT:   successors: %bb.3(0x80000000)
339  ; ALL-NEXT: {{  $}}
340  ; ALL-NEXT: {{  $}}
341  ; ALL-NEXT: bb.3.cond.end:
342  ; ALL-NEXT:   [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
343  ; ALL-NEXT:   $rax = COPY [[PHI]]
344  ; ALL-NEXT:   RET 0, implicit $rax
345  bb.1.entry:
346    successors: %bb.2(0x40000000), %bb.3(0x40000000)
347    liveins: $edi, $rdx, $rsi
348
349    %0(s32) = COPY $edi
350    %1(s64) = COPY $rsi
351    %2(s64) = COPY $rdx
352    %3(s32) = G_CONSTANT i32 0
353    %6(s8) = G_ICMP intpred(sgt), %0(s32), %3
354    %4:gpr(s1) = G_TRUNC %6(s8)
355    G_BRCOND %4(s1), %bb.2
356    G_BR %bb.3
357
358  bb.2.cond.true:
359    successors: %bb.4(0x80000000)
360
361    G_BR %bb.4
362
363  bb.3.cond.false:
364    successors: %bb.4(0x80000000)
365
366
367  bb.4.cond.end:
368    %5(s64) = G_PHI %1(s64), %bb.2, %2(s64), %bb.3
369    $rax = COPY %5(s64)
370    RET 0, implicit $rax
371
372...
373---
374name:            test_float
375alignment:       16
376legalized:       true
377regBankSelected: true
378tracksRegLiveness: true
379registers:
380  - { id: 0, class: gpr, preferred-register: '' }
381  - { id: 1, class: vecr, preferred-register: '' }
382  - { id: 2, class: vecr, preferred-register: '' }
383  - { id: 3, class: vecr, preferred-register: '' }
384  - { id: 4, class: vecr, preferred-register: '' }
385  - { id: 5, class: gpr, preferred-register: '' }
386  - { id: 6, class: gpr, preferred-register: '' }
387  - { id: 7, class: vecr, preferred-register: '' }
388  - { id: 8, class: vecr, preferred-register: '' }
389liveins:
390fixedStack:
391stack:
392constants:
393body:             |
394  ; ALL-LABEL: name: test_float
395  ; ALL: bb.0.entry:
396  ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
397  ; ALL-NEXT:   liveins: $edi, $xmm0, $xmm1
398  ; ALL-NEXT: {{  $}}
399  ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
400  ; ALL-NEXT:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
401  ; ALL-NEXT:   [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
402  ; ALL-NEXT:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
403  ; ALL-NEXT:   [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
404  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
405  ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
406  ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
407  ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
408  ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
409  ; ALL-NEXT: {{  $}}
410  ; ALL-NEXT: bb.1.cond.false:
411  ; ALL-NEXT:   successors: %bb.2(0x80000000)
412  ; ALL-NEXT: {{  $}}
413  ; ALL-NEXT: {{  $}}
414  ; ALL-NEXT: bb.2.cond.end:
415  ; ALL-NEXT:   [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
416  ; ALL-NEXT:   [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
417  ; ALL-NEXT:   $xmm0 = COPY [[COPY5]]
418  ; ALL-NEXT:   RET 0, implicit $xmm0
419  bb.1.entry:
420    successors: %bb.3(0x40000000), %bb.2(0x40000000)
421    liveins: $edi, $xmm0, $xmm1
422
423    %0:gpr(s32) = COPY $edi
424    %3:vecr(s128) = COPY $xmm0
425    %1:vecr(s32) = G_TRUNC %3(s128)
426    %4:vecr(s128) = COPY $xmm1
427    %2:vecr(s32) = G_TRUNC %4(s128)
428    %5:gpr(s32) = G_CONSTANT i32 0
429    %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
430    %6:gpr(s1) = G_TRUNC %9(s8)
431    G_BRCOND %6(s1), %bb.3
432
433  bb.2.cond.false:
434    successors: %bb.3(0x80000000)
435
436  bb.3.cond.end:
437    %7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
438    %8:vecr(s128) = G_ANYEXT %7(s32)
439    $xmm0 = COPY %8(s128)
440    RET 0, implicit $xmm0
441
442...
443---
444name:            test_double
445alignment:       16
446legalized:       true
447regBankSelected: true
448tracksRegLiveness: true
449registers:
450  - { id: 0, class: gpr, preferred-register: '' }
451  - { id: 1, class: vecr, preferred-register: '' }
452  - { id: 2, class: vecr, preferred-register: '' }
453  - { id: 3, class: vecr, preferred-register: '' }
454  - { id: 4, class: vecr, preferred-register: '' }
455  - { id: 5, class: gpr, preferred-register: '' }
456  - { id: 6, class: gpr, preferred-register: '' }
457  - { id: 7, class: vecr, preferred-register: '' }
458  - { id: 8, class: vecr, preferred-register: '' }
459body:             |
460  ; ALL-LABEL: name: test_double
461  ; ALL: bb.0.entry:
462  ; ALL-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
463  ; ALL-NEXT:   liveins: $edi, $xmm0, $xmm1
464  ; ALL-NEXT: {{  $}}
465  ; ALL-NEXT:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
466  ; ALL-NEXT:   [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
467  ; ALL-NEXT:   [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
468  ; ALL-NEXT:   [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
469  ; ALL-NEXT:   [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
470  ; ALL-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
471  ; ALL-NEXT:   CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
472  ; ALL-NEXT:   [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
473  ; ALL-NEXT:   TEST8ri [[SETCCr]], 1, implicit-def $eflags
474  ; ALL-NEXT:   JCC_1 %bb.2, 5, implicit $eflags
475  ; ALL-NEXT: {{  $}}
476  ; ALL-NEXT: bb.1.cond.false:
477  ; ALL-NEXT:   successors: %bb.2(0x80000000)
478  ; ALL-NEXT: {{  $}}
479  ; ALL-NEXT: {{  $}}
480  ; ALL-NEXT: bb.2.cond.end:
481  ; ALL-NEXT:   [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
482  ; ALL-NEXT:   [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
483  ; ALL-NEXT:   $xmm0 = COPY [[COPY5]]
484  ; ALL-NEXT:   RET 0, implicit $xmm0
485  bb.1.entry:
486    successors: %bb.3(0x40000000), %bb.2(0x40000000)
487    liveins: $edi, $xmm0, $xmm1
488
489    %0:gpr(s32) = COPY $edi
490    %3:vecr(s128) = COPY $xmm0
491    %1:vecr(s64) = G_TRUNC %3(s128)
492    %4:vecr(s128) = COPY $xmm1
493    %2:vecr(s64) = G_TRUNC %4(s128)
494    %5:gpr(s32) = G_CONSTANT i32 0
495    %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
496    %6:gpr(s1) = G_TRUNC %9(s8)
497    G_BRCOND %6(s1), %bb.3
498
499  bb.2.cond.false:
500    successors: %bb.3(0x80000000)
501
502  bb.3.cond.end:
503    %7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1
504    %8:vecr(s128) = G_ANYEXT %7(s64)
505    $xmm0 = COPY %8(s128)
506    RET 0, implicit $xmm0
507
508...
509