1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK 3 4--- | 5 define i32 @test_icmp_eq_i8(i8 %a, i8 %b) { 6 %r = icmp eq i8 %a, %b 7 %res = zext i1 %r to i32 8 ret i32 %res 9 } 10 11 define i32 @test_icmp_eq_i16(i16 %a, i16 %b) { 12 %r = icmp eq i16 %a, %b 13 %res = zext i1 %r to i32 14 ret i32 %res 15 } 16 17 define i32 @test_icmp_eq_i64(i64 %a, i64 %b) { 18 %r = icmp eq i64 %a, %b 19 %res = zext i1 %r to i32 20 ret i32 %res 21 } 22 23 define i32 @test_icmp_eq_i32(i32 %a, i32 %b) { 24 %r = icmp eq i32 %a, %b 25 %res = zext i1 %r to i32 26 ret i32 %res 27 } 28 29 define i32 @test_icmp_ne_i32(i32 %a, i32 %b) { 30 %r = icmp ne i32 %a, %b 31 %res = zext i1 %r to i32 32 ret i32 %res 33 } 34 35 define i32 @test_icmp_ugt_i32(i32 %a, i32 %b) { 36 %r = icmp ugt i32 %a, %b 37 %res = zext i1 %r to i32 38 ret i32 %res 39 } 40 41 define i32 @test_icmp_uge_i32(i32 %a, i32 %b) { 42 %r = icmp uge i32 %a, %b 43 %res = zext i1 %r to i32 44 ret i32 %res 45 } 46 47 define i32 @test_icmp_ult_i32(i32 %a, i32 %b) { 48 %r = icmp ult i32 %a, %b 49 %res = zext i1 %r to i32 50 ret i32 %res 51 } 52 53 define i32 @test_icmp_ule_i32(i32 %a, i32 %b) { 54 %r = icmp ule i32 %a, %b 55 %res = zext i1 %r to i32 56 ret i32 %res 57 } 58 59 define i32 @test_icmp_sgt_i32(i32 %a, i32 %b) { 60 %r = icmp sgt i32 %a, %b 61 %res = zext i1 %r to i32 62 ret i32 %res 63 } 64 65 define i32 @test_icmp_sge_i32(i32 %a, i32 %b) { 66 %r = icmp sge i32 %a, %b 67 %res = zext i1 %r to i32 68 ret i32 %res 69 } 70 71 define i32 @test_icmp_slt_i32(i32 %a, i32 %b) { 72 %r = icmp slt i32 %a, %b 73 %res = zext i1 %r to i32 74 ret i32 %res 75 } 76 77 define i32 @test_icmp_sle_i32(i32 %a, i32 %b) { 78 %r = icmp sle i32 %a, %b 79 %res = zext i1 %r to i32 80 ret i32 %res 81 } 82 83... 84--- 85name: test_icmp_eq_i8 86alignment: 16 87legalized: true 88regBankSelected: true 89registers: 90 - { id: 0, class: gpr } 91 - { id: 1, class: gpr } 92 - { id: 2, class: _ } 93 - { id: 3, class: gpr } 94 - { id: 4, class: gpr } 95 - { id: 5, class: gpr } 96 - { id: 6, class: gpr } 97body: | 98 bb.1 (%ir-block.0): 99 liveins: $edi, $esi 100 101 ; CHECK-LABEL: name: test_icmp_eq_i8 102 ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $dil 103 ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil 104 ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags 105 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 106 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 107 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 108 ; CHECK: $eax = COPY [[AND32ri8_]] 109 ; CHECK: RET 0, implicit $eax 110 %0(s8) = COPY $dil 111 %1(s8) = COPY $sil 112 %4(s8) = G_ICMP intpred(eq), %0(s8), %1 113 %5(s32) = G_CONSTANT i32 1 114 %6(s32) = G_ANYEXT %4(s8) 115 %3(s32) = G_AND %6, %5 116 $eax = COPY %3(s32) 117 RET 0, implicit $eax 118 119... 120--- 121name: test_icmp_eq_i16 122alignment: 16 123legalized: true 124regBankSelected: true 125registers: 126 - { id: 0, class: gpr } 127 - { id: 1, class: gpr } 128 - { id: 2, class: _ } 129 - { id: 3, class: gpr } 130 - { id: 4, class: gpr } 131 - { id: 5, class: gpr } 132 - { id: 6, class: gpr } 133body: | 134 bb.1 (%ir-block.0): 135 liveins: $edi, $esi 136 137 ; CHECK-LABEL: name: test_icmp_eq_i16 138 ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $di 139 ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si 140 ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags 141 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 142 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 143 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 144 ; CHECK: $eax = COPY [[AND32ri8_]] 145 ; CHECK: RET 0, implicit $eax 146 %0(s16) = COPY $di 147 %1(s16) = COPY $si 148 %4(s8) = G_ICMP intpred(eq), %0(s16), %1 149 %5(s32) = G_CONSTANT i32 1 150 %6(s32) = G_ANYEXT %4(s8) 151 %3(s32) = G_AND %6, %5 152 $eax = COPY %3(s32) 153 RET 0, implicit $eax 154 155... 156--- 157name: test_icmp_eq_i64 158alignment: 16 159legalized: true 160regBankSelected: true 161registers: 162 - { id: 0, class: gpr } 163 - { id: 1, class: gpr } 164 - { id: 2, class: _ } 165 - { id: 3, class: gpr } 166 - { id: 4, class: gpr } 167 - { id: 5, class: gpr } 168 - { id: 6, class: gpr } 169body: | 170 bb.1 (%ir-block.0): 171 liveins: $rdi, $rsi 172 173 ; CHECK-LABEL: name: test_icmp_eq_i64 174 ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 175 ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi 176 ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags 177 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 178 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 179 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 180 ; CHECK: $eax = COPY [[AND32ri8_]] 181 ; CHECK: RET 0, implicit $eax 182 %0(s64) = COPY $rdi 183 %1(s64) = COPY $rsi 184 %4(s8) = G_ICMP intpred(eq), %0(s64), %1 185 %5(s32) = G_CONSTANT i32 1 186 %6(s32) = G_ANYEXT %4(s8) 187 %3(s32) = G_AND %6, %5 188 $eax = COPY %3(s32) 189 RET 0, implicit $eax 190 191... 192--- 193name: test_icmp_eq_i32 194alignment: 16 195legalized: true 196regBankSelected: true 197registers: 198 - { id: 0, class: gpr } 199 - { id: 1, class: gpr } 200 - { id: 2, class: _ } 201 - { id: 3, class: gpr } 202 - { id: 4, class: gpr } 203 - { id: 5, class: gpr } 204 - { id: 6, class: gpr } 205body: | 206 bb.1 (%ir-block.0): 207 liveins: $edi, $esi 208 209 ; CHECK-LABEL: name: test_icmp_eq_i32 210 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 211 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 212 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 213 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags 214 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 215 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 216 ; CHECK: $eax = COPY [[AND32ri8_]] 217 ; CHECK: RET 0, implicit $eax 218 %0(s32) = COPY $edi 219 %1(s32) = COPY $esi 220 %4(s8) = G_ICMP intpred(eq), %0(s32), %1 221 %5(s32) = G_CONSTANT i32 1 222 %6(s32) = G_ANYEXT %4(s8) 223 %3(s32) = G_AND %6, %5 224 $eax = COPY %3(s32) 225 RET 0, implicit $eax 226 227... 228--- 229name: test_icmp_ne_i32 230alignment: 16 231legalized: true 232regBankSelected: true 233registers: 234 - { id: 0, class: gpr } 235 - { id: 1, class: gpr } 236 - { id: 2, class: _ } 237 - { id: 3, class: gpr } 238 - { id: 4, class: gpr } 239 - { id: 5, class: gpr } 240 - { id: 6, class: gpr } 241body: | 242 bb.1 (%ir-block.0): 243 liveins: $edi, $esi 244 245 ; CHECK-LABEL: name: test_icmp_ne_i32 246 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 247 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 248 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 249 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags 250 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 251 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 252 ; CHECK: $eax = COPY [[AND32ri8_]] 253 ; CHECK: RET 0, implicit $eax 254 %0(s32) = COPY $edi 255 %1(s32) = COPY $esi 256 %4(s8) = G_ICMP intpred(ne), %0(s32), %1 257 %5(s32) = G_CONSTANT i32 1 258 %6(s32) = G_ANYEXT %4(s8) 259 %3(s32) = G_AND %6, %5 260 $eax = COPY %3(s32) 261 RET 0, implicit $eax 262 263... 264--- 265name: test_icmp_ugt_i32 266alignment: 16 267legalized: true 268regBankSelected: true 269registers: 270 - { id: 0, class: gpr } 271 - { id: 1, class: gpr } 272 - { id: 2, class: _ } 273 - { id: 3, class: gpr } 274 - { id: 4, class: gpr } 275 - { id: 5, class: gpr } 276 - { id: 6, class: gpr } 277body: | 278 bb.1 (%ir-block.0): 279 liveins: $edi, $esi 280 281 ; CHECK-LABEL: name: test_icmp_ugt_i32 282 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 283 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 284 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 285 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags 286 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 287 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 288 ; CHECK: $eax = COPY [[AND32ri8_]] 289 ; CHECK: RET 0, implicit $eax 290 %0(s32) = COPY $edi 291 %1(s32) = COPY $esi 292 %4(s8) = G_ICMP intpred(ugt), %0(s32), %1 293 %5(s32) = G_CONSTANT i32 1 294 %6(s32) = G_ANYEXT %4(s8) 295 %3(s32) = G_AND %6, %5 296 $eax = COPY %3(s32) 297 RET 0, implicit $eax 298 299... 300--- 301name: test_icmp_uge_i32 302alignment: 16 303legalized: true 304regBankSelected: true 305registers: 306 - { id: 0, class: gpr } 307 - { id: 1, class: gpr } 308 - { id: 2, class: _ } 309 - { id: 3, class: gpr } 310 - { id: 4, class: gpr } 311 - { id: 5, class: gpr } 312 - { id: 6, class: gpr } 313body: | 314 bb.1 (%ir-block.0): 315 liveins: $edi, $esi 316 317 ; CHECK-LABEL: name: test_icmp_uge_i32 318 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 319 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 320 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 321 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags 322 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 323 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 324 ; CHECK: $eax = COPY [[AND32ri8_]] 325 ; CHECK: RET 0, implicit $eax 326 %0(s32) = COPY $edi 327 %1(s32) = COPY $esi 328 %4(s8) = G_ICMP intpred(uge), %0(s32), %1 329 %5(s32) = G_CONSTANT i32 1 330 %6(s32) = G_ANYEXT %4(s8) 331 %3(s32) = G_AND %6, %5 332 $eax = COPY %3(s32) 333 RET 0, implicit $eax 334 335... 336--- 337name: test_icmp_ult_i32 338alignment: 16 339legalized: true 340regBankSelected: true 341registers: 342 - { id: 0, class: gpr } 343 - { id: 1, class: gpr } 344 - { id: 2, class: _ } 345 - { id: 3, class: gpr } 346 - { id: 4, class: gpr } 347 - { id: 5, class: gpr } 348 - { id: 6, class: gpr } 349body: | 350 bb.1 (%ir-block.0): 351 liveins: $edi, $esi 352 353 ; CHECK-LABEL: name: test_icmp_ult_i32 354 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 355 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 356 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 357 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags 358 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 359 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 360 ; CHECK: $eax = COPY [[AND32ri8_]] 361 ; CHECK: RET 0, implicit $eax 362 %0(s32) = COPY $edi 363 %1(s32) = COPY $esi 364 %4(s8) = G_ICMP intpred(ult), %0(s32), %1 365 %5(s32) = G_CONSTANT i32 1 366 %6(s32) = G_ANYEXT %4(s8) 367 %3(s32) = G_AND %6, %5 368 $eax = COPY %3(s32) 369 RET 0, implicit $eax 370 371... 372--- 373name: test_icmp_ule_i32 374alignment: 16 375legalized: true 376regBankSelected: true 377registers: 378 - { id: 0, class: gpr } 379 - { id: 1, class: gpr } 380 - { id: 2, class: _ } 381 - { id: 3, class: gpr } 382 - { id: 4, class: gpr } 383 - { id: 5, class: gpr } 384 - { id: 6, class: gpr } 385body: | 386 bb.1 (%ir-block.0): 387 liveins: $edi, $esi 388 389 ; CHECK-LABEL: name: test_icmp_ule_i32 390 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 391 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 392 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 393 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags 394 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 395 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 396 ; CHECK: $eax = COPY [[AND32ri8_]] 397 ; CHECK: RET 0, implicit $eax 398 %0(s32) = COPY $edi 399 %1(s32) = COPY $esi 400 %4(s8) = G_ICMP intpred(ule), %0(s32), %1 401 %5(s32) = G_CONSTANT i32 1 402 %6(s32) = G_ANYEXT %4(s8) 403 %3(s32) = G_AND %6, %5 404 $eax = COPY %3(s32) 405 RET 0, implicit $eax 406 407... 408--- 409name: test_icmp_sgt_i32 410alignment: 16 411legalized: true 412regBankSelected: true 413registers: 414 - { id: 0, class: gpr } 415 - { id: 1, class: gpr } 416 - { id: 2, class: _ } 417 - { id: 3, class: gpr } 418 - { id: 4, class: gpr } 419 - { id: 5, class: gpr } 420 - { id: 6, class: gpr } 421body: | 422 bb.1 (%ir-block.0): 423 liveins: $edi, $esi 424 425 ; CHECK-LABEL: name: test_icmp_sgt_i32 426 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 427 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 428 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 429 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags 430 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 431 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 432 ; CHECK: $eax = COPY [[AND32ri8_]] 433 ; CHECK: RET 0, implicit $eax 434 %0(s32) = COPY $edi 435 %1(s32) = COPY $esi 436 %4(s8) = G_ICMP intpred(sgt), %0(s32), %1 437 %5(s32) = G_CONSTANT i32 1 438 %6(s32) = G_ANYEXT %4(s8) 439 %3(s32) = G_AND %6, %5 440 $eax = COPY %3(s32) 441 RET 0, implicit $eax 442 443... 444--- 445name: test_icmp_sge_i32 446alignment: 16 447legalized: true 448regBankSelected: true 449registers: 450 - { id: 0, class: gpr } 451 - { id: 1, class: gpr } 452 - { id: 2, class: _ } 453 - { id: 3, class: gpr } 454 - { id: 4, class: gpr } 455 - { id: 5, class: gpr } 456 - { id: 6, class: gpr } 457body: | 458 bb.1 (%ir-block.0): 459 liveins: $edi, $esi 460 461 ; CHECK-LABEL: name: test_icmp_sge_i32 462 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 463 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 464 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 465 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags 466 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 467 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 468 ; CHECK: $eax = COPY [[AND32ri8_]] 469 ; CHECK: RET 0, implicit $eax 470 %0(s32) = COPY $edi 471 %1(s32) = COPY $esi 472 %4(s8) = G_ICMP intpred(sge), %0(s32), %1 473 %5(s32) = G_CONSTANT i32 1 474 %6(s32) = G_ANYEXT %4(s8) 475 %3(s32) = G_AND %6, %5 476 $eax = COPY %3(s32) 477 RET 0, implicit $eax 478 479... 480--- 481name: test_icmp_slt_i32 482alignment: 16 483legalized: true 484regBankSelected: true 485registers: 486 - { id: 0, class: gpr } 487 - { id: 1, class: gpr } 488 - { id: 2, class: _ } 489 - { id: 3, class: gpr } 490 - { id: 4, class: gpr } 491 - { id: 5, class: gpr } 492 - { id: 6, class: gpr } 493body: | 494 bb.1 (%ir-block.0): 495 liveins: $edi, $esi 496 497 ; CHECK-LABEL: name: test_icmp_slt_i32 498 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 499 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 500 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 501 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags 502 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 503 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 504 ; CHECK: $eax = COPY [[AND32ri8_]] 505 ; CHECK: RET 0, implicit $eax 506 %0(s32) = COPY $edi 507 %1(s32) = COPY $esi 508 %4(s8) = G_ICMP intpred(slt), %0(s32), %1 509 %5(s32) = G_CONSTANT i32 1 510 %6(s32) = G_ANYEXT %4(s8) 511 %3(s32) = G_AND %6, %5 512 $eax = COPY %3(s32) 513 RET 0, implicit $eax 514 515... 516--- 517name: test_icmp_sle_i32 518alignment: 16 519legalized: true 520regBankSelected: true 521registers: 522 - { id: 0, class: gpr } 523 - { id: 1, class: gpr } 524 - { id: 2, class: _ } 525 - { id: 3, class: gpr } 526 - { id: 4, class: gpr } 527 - { id: 5, class: gpr } 528 - { id: 6, class: gpr } 529body: | 530 bb.1 (%ir-block.0): 531 liveins: $edi, $esi 532 533 ; CHECK-LABEL: name: test_icmp_sle_i32 534 ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi 535 ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi 536 ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags 537 ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags 538 ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]] 539 ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags 540 ; CHECK: $eax = COPY [[AND32ri8_]] 541 ; CHECK: RET 0, implicit $eax 542 %0(s32) = COPY $edi 543 %1(s32) = COPY $esi 544 %4(s8) = G_ICMP intpred(sle), %0(s32), %1 545 %5(s32) = G_CONSTANT i32 1 546 %6(s32) = G_ANYEXT %4(s8) 547 %3(s32) = G_AND %6, %5 548 $eax = COPY %3(s32) 549 RET 0, implicit $eax 550 551... 552