1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
4
5; Test that vector sign extensions lower to shifts
6
7target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
8target triple = "wasm32-unknown-unknown"
9
10; CHECK-LABEL: sext_inreg_v16i8:
11; NO-SIMD128-NOT: i8x16
12; SIMD128-NEXT: .functype sext_inreg_v16i8 (v128) -> (v128){{$}}
13; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 7{{$}}
14; SIMD128-NEXT: i8x16.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
15; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 7{{$}}
16; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
17; SIMD128-NEXT: return $pop[[R]]{{$}}
18define <16 x i8> @sext_inreg_v16i8(<16 x i1> %x) {
19  %res = sext <16 x i1> %x to <16 x i8>
20  ret <16 x i8> %res
21}
22
23; CHECK-LABEL: sext_inreg_v8i16:
24; NO-SIMD128-NOT: i16x8
25; SIMD128-NEXT: .functype sext_inreg_v8i16 (v128) -> (v128){{$}}
26; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 15{{$}}
27; SIMD128-NEXT: i16x8.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
28; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 15{{$}}
29; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
30; SIMD128-NEXT: return $pop[[R]]{{$}}
31define <8 x i16> @sext_inreg_v8i16(<8 x i1> %x) {
32  %res = sext <8 x i1> %x to <8 x i16>
33  ret <8 x i16> %res
34}
35
36; CHECK-LABEL: sext_inreg_v4i32:
37; NO-SIMD128-NOT: i32x4
38; SIMD128-NEXT: .functype sext_inreg_v4i32 (v128) -> (v128){{$}}
39; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 31{{$}}
40; SIMD128-NEXT: i32x4.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
41; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 31{{$}}
42; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
43; SIMD128-NEXT: return $pop[[R]]{{$}}
44define <4 x i32> @sext_inreg_v4i32(<4 x i1> %x) {
45  %res = sext <4 x i1> %x to <4 x i32>
46  ret <4 x i32> %res
47}
48
49; CHECK-LABEL: sext_inreg_v2i64:
50; NO-SIMD128-NOT: i64x2
51; SDIM128-VM-NOT: i64x2
52; SIMD128-NEXT: .functype sext_inreg_v2i64 (v128) -> (v128){{$}}
53; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 63{{$}}
54; SIMD128-NEXT: i64x2.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
55; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 63{{$}}
56; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
57; SIMD128-NEXT: return $pop[[R]]{{$}}
58define <2 x i64> @sext_inreg_v2i64(<2 x i1> %x) {
59  %res = sext <2 x i1> %x to <2 x i64>
60  ret <2 x i64> %res
61}
62