1; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s 2 3; This tests that indirectbr instructions are lowered to switches. Currently we 4; just re-use the IndirectBrExpand Pass; it has its own IR-level test. 5; So this test just ensures that the pass gets run and we can lower indirectbr 6 7target triple = "wasm32" 8 9@test1.targets = constant [4 x i8*] [i8* blockaddress(@test1, %bb0), 10 i8* blockaddress(@test1, %bb1), 11 i8* blockaddress(@test1, %bb2), 12 i8* blockaddress(@test1, %bb3)] 13 14; Just check the barest skeleton of the structure 15; CHECK-LABEL: test1: 16; CHECK: i32.load 17; CHECK: i32.load $[[DEST:.+]]= 18; CHECK: loop 19; CHECK: block 20; CHECK: block 21; CHECK: end_block 22; CHECK: block 23; CHECK: block 24; CHECK: br_table $[[DEST]] 25; CHECK: end_block 26; CHECK: end_block 27; CHECK: i32.load $[[DEST]]= 28; CHECK: end_loop 29 30; CHECK: test1.targets: 31; CHECK-NEXT: .int32 32; CHECK-NEXT: .int32 33; CHECK-NEXT: .int32 34; CHECK-NEXT: .int32 35 36define void @test1(i32* readonly %p, i32* %sink) #0 { 37 38entry: 39 %i0 = load i32, i32* %p 40 %target.i0 = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i0 41 %target0 = load i8*, i8** %target.i0 42 ; Only a subset of blocks are viable successors here. 43 indirectbr i8* %target0, [label %bb0, label %bb1] 44 45 46bb0: 47 store volatile i32 0, i32* %sink 48 br label %latch 49 50bb1: 51 store volatile i32 1, i32* %sink 52 br label %latch 53 54bb2: 55 store volatile i32 2, i32* %sink 56 br label %latch 57 58bb3: 59 store volatile i32 3, i32* %sink 60 br label %latch 61 62latch: 63 %i.next = load i32, i32* %p 64 %target.i.next = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i.next 65 %target.next = load i8*, i8** %target.i.next 66 ; A different subset of blocks are viable successors here. 67 indirectbr i8* %target.next, [label %bb1, label %bb2] 68} 69